From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F5DA7A for ; Tue, 28 Jun 2022 01:34:19 +0000 (UTC) X-UUID: 171d60aabc544a2a87538658d7fa59f7-20220628 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7,REQID:2bf20d50-2110-4040-b110-2ff891e32e5b,OB:0,LO B:20,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,A CTION:release,TS:45 X-CID-INFO: VERSION:1.1.7,REQID:2bf20d50-2110-4040-b110-2ff891e32e5b,OB:0,LOB: 20,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:45 X-CID-META: VersionHash:87442a2,CLOUDID:881eee85-57f0-47ca-ba27-fe8c57fbf305,C OID:e66581b8edef,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 171d60aabc544a2a87538658d7fa59f7-20220628 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 254101548; Tue, 28 Jun 2022 09:34:14 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 28 Jun 2022 09:34:11 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 28 Jun 2022 09:34:11 +0800 Message-ID: Subject: Re: [PATCH v23 03/14] drm/mediatek: add display MDP RDMA support for MT8195 From: CK Hu To: Nancy.Lin , Rob Herring , Matthias Brugger , Chun-Kuang Hu , Philipp Zabel , , AngeloGioacchino Del Regno , CC: , , Yongqiang Niu , David Airlie , "jason-jh . lin" , , , Nick Desaulniers , , , "Nathan Chancellor" , , Date: Tue, 28 Jun 2022 09:34:11 +0800 In-Reply-To: <20220620091930.27797-4-nancy.lin@mediatek.com> References: <20220620091930.27797-1-nancy.lin@mediatek.com> <20220620091930.27797-4-nancy.lin@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Hi, Nancy: On Mon, 2022-06-20 at 17:19 +0800, Nancy.Lin wrote: > Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of > the ovl_adaptor component. Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, CK > > Signed-off-by: Nancy.Lin > Reviewed-by: Chun-Kuang Hu > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Tested-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Tested-by: Bo-Chen Chen > --- > drivers/gpu/drm/mediatek/Makefile | 3 +- > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 + > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 315 > ++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 20 ++ > 6 files changed, 346 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h > > diff --git a/drivers/gpu/drm/mediatek/Makefile > b/drivers/gpu/drm/mediatek/Makefile > index a38e88e82d12..6e604a933ed0 100644 > --- a/drivers/gpu/drm/mediatek/Makefile > +++ b/drivers/gpu/drm/mediatek/Makefile > @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \ > mtk_drm_gem.o \ > mtk_drm_plane.o \ > mtk_dsi.o \ > - mtk_dpi.o > + mtk_dpi.o \ > + mtk_mdp_rdma.o > > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > index f13a6f5d512a..2cd1c660ace3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > @@ -8,6 +8,7 @@ > > #include > #include "mtk_drm_plane.h" > +#include "mtk_mdp_rdma.h" > > int mtk_aal_clk_enable(struct device *dev); > void mtk_aal_clk_disable(struct device *dev); > @@ -110,4 +111,10 @@ void mtk_rdma_unregister_vblank_cb(struct device > *dev); > void mtk_rdma_enable_vblank(struct device *dev); > void mtk_rdma_disable_vblank(struct device *dev); > > +int mtk_mdp_rdma_clk_enable(struct device *dev); > +void mtk_mdp_rdma_clk_disable(struct device *dev); > +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt > *cmdq_pkt); > +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt > *cmdq_pkt); > +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg > *cfg, > + struct cmdq_pkt *cmdq_pkt); > #endif > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 076ef59c0c0b..685846cc3490 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -873,6 +873,7 @@ static struct platform_driver * const > mtk_drm_drivers[] = { > &mtk_dpi_driver, > &mtk_drm_platform_driver, > &mtk_dsi_driver, > + &mtk_mdp_rdma_driver, > }; > > static int __init mtk_drm_init(void) > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 9fc922b1684f..7b37b5cf9629 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -61,5 +61,6 @@ extern struct platform_driver mtk_disp_ovl_driver; > extern struct platform_driver mtk_disp_rdma_driver; > extern struct platform_driver mtk_dpi_driver; > extern struct platform_driver mtk_dsi_driver; > +extern struct platform_driver mtk_mdp_rdma_driver; > > #endif /* MTK_DRM_DRV_H */ > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c > new file mode 100644 > index 000000000000..eecfa98ff52e > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c > @@ -0,0 +1,315 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "mtk_disp_drv.h" > +#include "mtk_drm_drv.h" > +#include "mtk_mdp_rdma.h" > + > +#define MDP_RDMA_EN 0x000 > +#define FLD_ROT_ENABLE BIT(0) > +#define MDP_RDMA_RESET 0x008 > +#define MDP_RDMA_CON 0x020 > +#define FLD_OUTPUT_10B BIT(5) > +#define FLD_SIMPLE_MODE BIT(4) > +#define MDP_RDMA_GMCIF_CON 0x028 > +#define FLD_COMMAND_DIV BIT(0) > +#define FLD_EXT_PREULTRA_EN BIT(3) > +#define FLD_RD_REQ_TYPE GENMASK(7, 4) > +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7 > +#define FLD_ULTRA_EN GENMASK(13, 12) > +#define VAL_ULTRA_EN_ENABLE 1 > +#define FLD_PRE_ULTRA_EN GENMASK(17, 16) > +#define VAL_PRE_ULTRA_EN_ENABLE 1 > +#define FLD_EXT_ULTRA_EN BIT(18) > +#define MDP_RDMA_SRC_CON 0x030 > +#define FLD_OUTPUT_ARGB BIT(25) > +#define FLD_BIT_NUMBER GENMASK(19, 18) > +#define FLD_SWAP BIT(14) > +#define FLD_UNIFORM_CONFIG BIT(17) > +#define RDMA_INPUT_10BIT BIT(18) > +#define FLD_SRC_FORMAT GENMASK(3, 0) > +#define MDP_RDMA_COMP_CON 0x038 > +#define FLD_AFBC_EN BIT(22) > +#define FLD_AFBC_YUV_TRANSFORM BIT(21) > +#define FLD_UFBDC_EN BIT(12) > +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060 > +#define FLD_MF_BKGD_WB GENMASK(22, 0) > +#define MDP_RDMA_MF_SRC_SIZE 0x070 > +#define FLD_MF_SRC_H GENMASK(30, 16) > +#define FLD_MF_SRC_W GENMASK(14, 0) > +#define MDP_RDMA_MF_CLIP_SIZE 0x078 > +#define FLD_MF_CLIP_H GENMASK(30, 16) > +#define FLD_MF_CLIP_W GENMASK(14, 0) > +#define MDP_RDMA_SRC_OFFSET_0 0x118 > +#define FLD_SRC_OFFSET_0 GENMASK(31, 0) > +#define MDP_RDMA_TRANSFORM_0 0x200 > +#define FLD_INT_MATRIX_SEL GENMASK(27, 23) > +#define FLD_TRANS_EN BIT(16) > +#define MDP_RDMA_SRC_BASE_0 0xf00 > +#define FLD_SRC_BASE_0 GENMASK(31, 0) > + > +#define RDMA_CSC_FULL709_TO_RGB 5 > +#define RDMA_CSC_BT601_TO_RGB 6 > + > +enum rdma_format { > + RDMA_INPUT_FORMAT_RGB565 = 0, > + RDMA_INPUT_FORMAT_RGB888 = 1, > + RDMA_INPUT_FORMAT_RGBA8888 = 2, > + RDMA_INPUT_FORMAT_ARGB8888 = 3, > + RDMA_INPUT_FORMAT_UYVY = 4, > + RDMA_INPUT_FORMAT_YUY2 = 5, > + RDMA_INPUT_FORMAT_Y8 = 7, > + RDMA_INPUT_FORMAT_YV12 = 8, > + RDMA_INPUT_FORMAT_UYVY_3PL = 9, > + RDMA_INPUT_FORMAT_NV12 = 12, > + RDMA_INPUT_FORMAT_UYVY_2PL = 13, > + RDMA_INPUT_FORMAT_Y410 = 14 > +}; > + > +struct mtk_mdp_rdma { > + void __iomem *regs; > + struct clk *clk; > + struct cmdq_client_reg cmdq_reg; > +}; > + > +static unsigned int rdma_fmt_convert(unsigned int fmt) > +{ > + switch (fmt) { > + default: > + case DRM_FORMAT_RGB565: > + return RDMA_INPUT_FORMAT_RGB565; > + case DRM_FORMAT_BGR565: > + return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP; > + case DRM_FORMAT_RGB888: > + return RDMA_INPUT_FORMAT_RGB888; > + case DRM_FORMAT_BGR888: > + return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP; > + case DRM_FORMAT_RGBX8888: > + case DRM_FORMAT_RGBA8888: > + return RDMA_INPUT_FORMAT_ARGB8888; > + case DRM_FORMAT_BGRX8888: > + case DRM_FORMAT_BGRA8888: > + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP; > + case DRM_FORMAT_XRGB8888: > + case DRM_FORMAT_ARGB8888: > + return RDMA_INPUT_FORMAT_RGBA8888; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP; > + case DRM_FORMAT_ABGR2101010: > + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | > RDMA_INPUT_10BIT; > + case DRM_FORMAT_ARGB2101010: > + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT; > + case DRM_FORMAT_RGBA1010102: > + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | > RDMA_INPUT_10BIT; > + case DRM_FORMAT_BGRA1010102: > + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT; > + case DRM_FORMAT_UYVY: > + return RDMA_INPUT_FORMAT_UYVY; > + case DRM_FORMAT_YUYV: > + return RDMA_INPUT_FORMAT_YUY2; > + } > +} > + > +static unsigned int rdma_color_convert(unsigned int color_encoding) > +{ > + switch (color_encoding) { > + default: > + case DRM_COLOR_YCBCR_BT709: > + return RDMA_CSC_FULL709_TO_RGB; > + case DRM_COLOR_YCBCR_BT601: > + return RDMA_CSC_BT601_TO_RGB; > + } > +} > + > +static void mtk_mdp_rdma_fifo_config(struct device *dev, struct > cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | > VAL_PRE_ULTRA_EN_ENABLE << 16 | > + VAL_ULTRA_EN_ENABLE << 12 | > VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 | > + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, > &priv->cmdq_reg, > + priv->regs, MDP_RDMA_GMCIF_CON, > FLD_EXT_ULTRA_EN | > + FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | > FLD_RD_REQ_TYPE | > + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV); > +} > + > +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt > *cmdq_pkt) > +{ > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg, > + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE); > +} > + > +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt > *cmdq_pkt) > +{ > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, > + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE); > + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, > MDP_RDMA_RESET); > + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, > MDP_RDMA_RESET); > +} > + > +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg > *cfg, > + struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); > + const struct drm_format_info *fmt_info = drm_format_info(cfg- > >fmt); > + bool csc_enable = fmt_info->is_yuv ? true : false; > + unsigned int src_pitch_y = cfg->pitch; > + unsigned int offset_y = 0; > + > + mtk_mdp_rdma_fifo_config(dev, cmdq_pkt); > + > + mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv- > >cmdq_reg, priv->regs, > + MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG); > + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv- > >cmdq_reg, priv->regs, > + MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT > | FLD_BIT_NUMBER); > + > + if (!csc_enable && fmt_info->has_alpha) > + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv- > >cmdq_reg, > + priv->regs, MDP_RDMA_SRC_CON, > FLD_OUTPUT_ARGB); > + else > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB); > + > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0); > + > + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, > priv->regs, > + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, > FLD_MF_BKGD_WB); > + > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, > MDP_RDMA_COMP_CON, > + FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | > FLD_AFBC_EN); > + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, > priv->regs, > + MDP_RDMA_CON, FLD_OUTPUT_10B); > + mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, > priv->regs, > + MDP_RDMA_CON, FLD_SIMPLE_MODE); > + if (csc_enable) > + mtk_ddp_write_mask(cmdq_pkt, rdma_color_convert(cfg- > >color_encoding) << 23, > + &priv->cmdq_reg, priv->regs, > MDP_RDMA_TRANSFORM_0, > + FLD_INT_MATRIX_SEL); > + mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, > priv->regs, > + MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN); > + > + offset_y = cfg->x_left * fmt_info->cpp[0] + cfg->y_top * > src_pitch_y; > + > + mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0); > + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W); > + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv- > >cmdq_reg, priv->regs, > + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H); > + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W); > + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv- > >cmdq_reg, priv->regs, > + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H); > +} > + > +int mtk_mdp_rdma_clk_enable(struct device *dev) > +{ > + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev); > + > + clk_prepare_enable(rdma->clk); > + return 0; > +} > + > +void mtk_mdp_rdma_clk_disable(struct device *dev) > +{ > + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev); > + > + clk_disable_unprepare(rdma->clk); > +} > + > +static int mtk_mdp_rdma_bind(struct device *dev, struct device > *master, > + void *data) > +{ > + return 0; > +} > + > +static void mtk_mdp_rdma_unbind(struct device *dev, struct device > *master, > + void *data) > +{ > +} > + > +static const struct component_ops mtk_mdp_rdma_component_ops = { > + .bind = mtk_mdp_rdma_bind, > + .unbind = mtk_mdp_rdma_unbind, > +}; > + > +static int mtk_mdp_rdma_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct resource *res; > + struct mtk_mdp_rdma *priv; > + int ret = 0; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + priv->regs = devm_ioremap_resource(dev, res); > + if (IS_ERR(priv->regs)) { > + dev_err(dev, "failed to ioremap rdma\n"); > + return PTR_ERR(priv->regs); > + } > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) { > + dev_err(dev, "failed to get rdma clk\n"); > + return PTR_ERR(priv->clk); > + } > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); > + if (ret) > + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); > +#endif > + platform_set_drvdata(pdev, priv); > + > + pm_runtime_enable(dev); > + > + ret = component_add(dev, &mtk_mdp_rdma_component_ops); > + if (ret != 0) { > + pm_runtime_disable(dev); > + dev_err(dev, "Failed to add component: %d\n", ret); > + } > + return ret; > +} > + > +static int mtk_mdp_rdma_remove(struct platform_device *pdev) > +{ > + component_del(&pdev->dev, &mtk_mdp_rdma_component_ops); > + pm_runtime_disable(&pdev->dev); > + return 0; > +} > + > +static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = { > + { .compatible = "mediatek,mt8195-vdo1-rdma", }, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match); > + > +struct platform_driver mtk_mdp_rdma_driver = { > + .probe = mtk_mdp_rdma_probe, > + .remove = mtk_mdp_rdma_remove, > + .driver = { > + .name = "mediatek-mdp-rdma", > + .owner = THIS_MODULE, > + .of_match_table = mtk_mdp_rdma_driver_dt_match, > + }, > +}; > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h > new file mode 100644 > index 000000000000..9943ee3aac31 > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#ifndef __MTK_MDP_RDMA_H__ > +#define __MTK_MDP_RDMA_H__ > + > +struct mtk_mdp_rdma_cfg { > + unsigned int pitch; > + unsigned int addr0; > + unsigned int width; > + unsigned int height; > + unsigned int x_left; > + unsigned int y_top; > + int fmt; > + int color_encoding; > +}; > + > +#endif // __MTK_MDP_RDMA_H__ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60384CCA47F for ; Tue, 28 Jun 2022 01:34:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9634510E6E3; Tue, 28 Jun 2022 01:34:21 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id C30B510E1F2 for ; Tue, 28 Jun 2022 01:34:19 +0000 (UTC) X-UUID: 171d60aabc544a2a87538658d7fa59f7-20220628 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7, REQID:2bf20d50-2110-4040-b110-2ff891e32e5b, OB:0, LO B:20,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,A CTION:release,TS:45 X-CID-INFO: VERSION:1.1.7, REQID:2bf20d50-2110-4040-b110-2ff891e32e5b, OB:0, LOB: 20,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:45 X-CID-META: VersionHash:87442a2, CLOUDID:881eee85-57f0-47ca-ba27-fe8c57fbf305, C OID:e66581b8edef,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 171d60aabc544a2a87538658d7fa59f7-20220628 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 254101548; Tue, 28 Jun 2022 09:34:14 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 28 Jun 2022 09:34:11 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 28 Jun 2022 09:34:11 +0800 Message-ID: Subject: Re: [PATCH v23 03/14] drm/mediatek: add display MDP RDMA support for MT8195 From: CK Hu To: Nancy.Lin , Rob Herring , Matthias Brugger , Chun-Kuang Hu , Philipp Zabel , , AngeloGioacchino Del Regno , Date: Tue, 28 Jun 2022 09:34:11 +0800 In-Reply-To: <20220620091930.27797-4-nancy.lin@mediatek.com> References: <20220620091930.27797-1-nancy.lin@mediatek.com> <20220620091930.27797-4-nancy.lin@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, David Airlie , "jason-jh . lin" , singo.chang@mediatek.com, llvm@lists.linux.dev, Nick Desaulniers , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, Yongqiang Niu , Nathan Chancellor , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, Nancy: On Mon, 2022-06-20 at 17:19 +0800, Nancy.Lin wrote: > Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of > the ovl_adaptor component. Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, CK > > Signed-off-by: Nancy.Lin > Reviewed-by: Chun-Kuang Hu > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Tested-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Tested-by: Bo-Chen Chen > --- > drivers/gpu/drm/mediatek/Makefile | 3 +- > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 + > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 315 > ++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 20 ++ > 6 files changed, 346 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h > > diff --git a/drivers/gpu/drm/mediatek/Makefile > b/drivers/gpu/drm/mediatek/Makefile > index a38e88e82d12..6e604a933ed0 100644 > --- a/drivers/gpu/drm/mediatek/Makefile > +++ b/drivers/gpu/drm/mediatek/Makefile > @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \ > mtk_drm_gem.o \ > mtk_drm_plane.o \ > mtk_dsi.o \ > - mtk_dpi.o > + mtk_dpi.o \ > + mtk_mdp_rdma.o > > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > index f13a6f5d512a..2cd1c660ace3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > @@ -8,6 +8,7 @@ > > #include > #include "mtk_drm_plane.h" > +#include "mtk_mdp_rdma.h" > > int mtk_aal_clk_enable(struct device *dev); > void mtk_aal_clk_disable(struct device *dev); > @@ -110,4 +111,10 @@ void mtk_rdma_unregister_vblank_cb(struct device > *dev); > void mtk_rdma_enable_vblank(struct device *dev); > void mtk_rdma_disable_vblank(struct device *dev); > > +int mtk_mdp_rdma_clk_enable(struct device *dev); > +void mtk_mdp_rdma_clk_disable(struct device *dev); > +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt > *cmdq_pkt); > +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt > *cmdq_pkt); > +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg > *cfg, > + struct cmdq_pkt *cmdq_pkt); > #endif > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 076ef59c0c0b..685846cc3490 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -873,6 +873,7 @@ static struct platform_driver * const > mtk_drm_drivers[] = { > &mtk_dpi_driver, > &mtk_drm_platform_driver, > &mtk_dsi_driver, > + &mtk_mdp_rdma_driver, > }; > > static int __init mtk_drm_init(void) > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 9fc922b1684f..7b37b5cf9629 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -61,5 +61,6 @@ extern struct platform_driver mtk_disp_ovl_driver; > extern struct platform_driver mtk_disp_rdma_driver; > extern struct platform_driver mtk_dpi_driver; > extern struct platform_driver mtk_dsi_driver; > +extern struct platform_driver mtk_mdp_rdma_driver; > > #endif /* MTK_DRM_DRV_H */ > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c > new file mode 100644 > index 000000000000..eecfa98ff52e > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c > @@ -0,0 +1,315 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "mtk_disp_drv.h" > +#include "mtk_drm_drv.h" > +#include "mtk_mdp_rdma.h" > + > +#define MDP_RDMA_EN 0x000 > +#define FLD_ROT_ENABLE BIT(0) > +#define MDP_RDMA_RESET 0x008 > +#define MDP_RDMA_CON 0x020 > +#define FLD_OUTPUT_10B BIT(5) > +#define FLD_SIMPLE_MODE BIT(4) > +#define MDP_RDMA_GMCIF_CON 0x028 > +#define FLD_COMMAND_DIV BIT(0) > +#define FLD_EXT_PREULTRA_EN BIT(3) > +#define FLD_RD_REQ_TYPE GENMASK(7, 4) > +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7 > +#define FLD_ULTRA_EN GENMASK(13, 12) > +#define VAL_ULTRA_EN_ENABLE 1 > +#define FLD_PRE_ULTRA_EN GENMASK(17, 16) > +#define VAL_PRE_ULTRA_EN_ENABLE 1 > +#define FLD_EXT_ULTRA_EN BIT(18) > +#define MDP_RDMA_SRC_CON 0x030 > +#define FLD_OUTPUT_ARGB BIT(25) > +#define FLD_BIT_NUMBER GENMASK(19, 18) > +#define FLD_SWAP BIT(14) > +#define FLD_UNIFORM_CONFIG BIT(17) > +#define RDMA_INPUT_10BIT BIT(18) > +#define FLD_SRC_FORMAT GENMASK(3, 0) > +#define MDP_RDMA_COMP_CON 0x038 > +#define FLD_AFBC_EN BIT(22) > +#define FLD_AFBC_YUV_TRANSFORM BIT(21) > +#define FLD_UFBDC_EN BIT(12) > +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060 > +#define FLD_MF_BKGD_WB GENMASK(22, 0) > +#define MDP_RDMA_MF_SRC_SIZE 0x070 > +#define FLD_MF_SRC_H GENMASK(30, 16) > +#define FLD_MF_SRC_W GENMASK(14, 0) > +#define MDP_RDMA_MF_CLIP_SIZE 0x078 > +#define FLD_MF_CLIP_H GENMASK(30, 16) > +#define FLD_MF_CLIP_W GENMASK(14, 0) > +#define MDP_RDMA_SRC_OFFSET_0 0x118 > +#define FLD_SRC_OFFSET_0 GENMASK(31, 0) > +#define MDP_RDMA_TRANSFORM_0 0x200 > +#define FLD_INT_MATRIX_SEL GENMASK(27, 23) > +#define FLD_TRANS_EN BIT(16) > +#define MDP_RDMA_SRC_BASE_0 0xf00 > +#define FLD_SRC_BASE_0 GENMASK(31, 0) > + > +#define RDMA_CSC_FULL709_TO_RGB 5 > +#define RDMA_CSC_BT601_TO_RGB 6 > + > +enum rdma_format { > + RDMA_INPUT_FORMAT_RGB565 = 0, > + RDMA_INPUT_FORMAT_RGB888 = 1, > + RDMA_INPUT_FORMAT_RGBA8888 = 2, > + RDMA_INPUT_FORMAT_ARGB8888 = 3, > + RDMA_INPUT_FORMAT_UYVY = 4, > + RDMA_INPUT_FORMAT_YUY2 = 5, > + RDMA_INPUT_FORMAT_Y8 = 7, > + RDMA_INPUT_FORMAT_YV12 = 8, > + RDMA_INPUT_FORMAT_UYVY_3PL = 9, > + RDMA_INPUT_FORMAT_NV12 = 12, > + RDMA_INPUT_FORMAT_UYVY_2PL = 13, > + RDMA_INPUT_FORMAT_Y410 = 14 > +}; > + > +struct mtk_mdp_rdma { > + void __iomem *regs; > + struct clk *clk; > + struct cmdq_client_reg cmdq_reg; > +}; > + > +static unsigned int rdma_fmt_convert(unsigned int fmt) > +{ > + switch (fmt) { > + default: > + case DRM_FORMAT_RGB565: > + return RDMA_INPUT_FORMAT_RGB565; > + case DRM_FORMAT_BGR565: > + return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP; > + case DRM_FORMAT_RGB888: > + return RDMA_INPUT_FORMAT_RGB888; > + case DRM_FORMAT_BGR888: > + return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP; > + case DRM_FORMAT_RGBX8888: > + case DRM_FORMAT_RGBA8888: > + return RDMA_INPUT_FORMAT_ARGB8888; > + case DRM_FORMAT_BGRX8888: > + case DRM_FORMAT_BGRA8888: > + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP; > + case DRM_FORMAT_XRGB8888: > + case DRM_FORMAT_ARGB8888: > + return RDMA_INPUT_FORMAT_RGBA8888; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP; > + case DRM_FORMAT_ABGR2101010: > + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | > RDMA_INPUT_10BIT; > + case DRM_FORMAT_ARGB2101010: > + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT; > + case DRM_FORMAT_RGBA1010102: > + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | > RDMA_INPUT_10BIT; > + case DRM_FORMAT_BGRA1010102: > + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT; > + case DRM_FORMAT_UYVY: > + return RDMA_INPUT_FORMAT_UYVY; > + case DRM_FORMAT_YUYV: > + return RDMA_INPUT_FORMAT_YUY2; > + } > +} > + > +static unsigned int rdma_color_convert(unsigned int color_encoding) > +{ > + switch (color_encoding) { > + default: > + case DRM_COLOR_YCBCR_BT709: > + return RDMA_CSC_FULL709_TO_RGB; > + case DRM_COLOR_YCBCR_BT601: > + return RDMA_CSC_BT601_TO_RGB; > + } > +} > + > +static void mtk_mdp_rdma_fifo_config(struct device *dev, struct > cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | > VAL_PRE_ULTRA_EN_ENABLE << 16 | > + VAL_ULTRA_EN_ENABLE << 12 | > VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 | > + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, > &priv->cmdq_reg, > + priv->regs, MDP_RDMA_GMCIF_CON, > FLD_EXT_ULTRA_EN | > + FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | > FLD_RD_REQ_TYPE | > + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV); > +} > + > +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt > *cmdq_pkt) > +{ > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg, > + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE); > +} > + > +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt > *cmdq_pkt) > +{ > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, > + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE); > + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, > MDP_RDMA_RESET); > + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, > MDP_RDMA_RESET); > +} > + > +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg > *cfg, > + struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); > + const struct drm_format_info *fmt_info = drm_format_info(cfg- > >fmt); > + bool csc_enable = fmt_info->is_yuv ? true : false; > + unsigned int src_pitch_y = cfg->pitch; > + unsigned int offset_y = 0; > + > + mtk_mdp_rdma_fifo_config(dev, cmdq_pkt); > + > + mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv- > >cmdq_reg, priv->regs, > + MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG); > + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv- > >cmdq_reg, priv->regs, > + MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT > | FLD_BIT_NUMBER); > + > + if (!csc_enable && fmt_info->has_alpha) > + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv- > >cmdq_reg, > + priv->regs, MDP_RDMA_SRC_CON, > FLD_OUTPUT_ARGB); > + else > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB); > + > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0); > + > + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, > priv->regs, > + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, > FLD_MF_BKGD_WB); > + > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, > MDP_RDMA_COMP_CON, > + FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | > FLD_AFBC_EN); > + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, > priv->regs, > + MDP_RDMA_CON, FLD_OUTPUT_10B); > + mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, > priv->regs, > + MDP_RDMA_CON, FLD_SIMPLE_MODE); > + if (csc_enable) > + mtk_ddp_write_mask(cmdq_pkt, rdma_color_convert(cfg- > >color_encoding) << 23, > + &priv->cmdq_reg, priv->regs, > MDP_RDMA_TRANSFORM_0, > + FLD_INT_MATRIX_SEL); > + mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, > priv->regs, > + MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN); > + > + offset_y = cfg->x_left * fmt_info->cpp[0] + cfg->y_top * > src_pitch_y; > + > + mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0); > + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W); > + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv- > >cmdq_reg, priv->regs, > + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H); > + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W); > + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv- > >cmdq_reg, priv->regs, > + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H); > +} > + > +int mtk_mdp_rdma_clk_enable(struct device *dev) > +{ > + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev); > + > + clk_prepare_enable(rdma->clk); > + return 0; > +} > + > +void mtk_mdp_rdma_clk_disable(struct device *dev) > +{ > + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev); > + > + clk_disable_unprepare(rdma->clk); > +} > + > +static int mtk_mdp_rdma_bind(struct device *dev, struct device > *master, > + void *data) > +{ > + return 0; > +} > + > +static void mtk_mdp_rdma_unbind(struct device *dev, struct device > *master, > + void *data) > +{ > +} > + > +static const struct component_ops mtk_mdp_rdma_component_ops = { > + .bind = mtk_mdp_rdma_bind, > + .unbind = mtk_mdp_rdma_unbind, > +}; > + > +static int mtk_mdp_rdma_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct resource *res; > + struct mtk_mdp_rdma *priv; > + int ret = 0; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + priv->regs = devm_ioremap_resource(dev, res); > + if (IS_ERR(priv->regs)) { > + dev_err(dev, "failed to ioremap rdma\n"); > + return PTR_ERR(priv->regs); > + } > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) { > + dev_err(dev, "failed to get rdma clk\n"); > + return PTR_ERR(priv->clk); > + } > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); > + if (ret) > + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); > +#endif > + platform_set_drvdata(pdev, priv); > + > + pm_runtime_enable(dev); > + > + ret = component_add(dev, &mtk_mdp_rdma_component_ops); > + if (ret != 0) { > + pm_runtime_disable(dev); > + dev_err(dev, "Failed to add component: %d\n", ret); > + } > + return ret; > +} > + > +static int mtk_mdp_rdma_remove(struct platform_device *pdev) > +{ > + component_del(&pdev->dev, &mtk_mdp_rdma_component_ops); > + pm_runtime_disable(&pdev->dev); > + return 0; > +} > + > +static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = { > + { .compatible = "mediatek,mt8195-vdo1-rdma", }, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match); > + > +struct platform_driver mtk_mdp_rdma_driver = { > + .probe = mtk_mdp_rdma_probe, > + .remove = mtk_mdp_rdma_remove, > + .driver = { > + .name = "mediatek-mdp-rdma", > + .owner = THIS_MODULE, > + .of_match_table = mtk_mdp_rdma_driver_dt_match, > + }, > +}; > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h > new file mode 100644 > index 000000000000..9943ee3aac31 > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#ifndef __MTK_MDP_RDMA_H__ > +#define __MTK_MDP_RDMA_H__ > + > +struct mtk_mdp_rdma_cfg { > + unsigned int pitch; > + unsigned int addr0; > + unsigned int width; > + unsigned int height; > + unsigned int x_left; > + unsigned int y_top; > + int fmt; > + int color_encoding; > +}; > + > +#endif // __MTK_MDP_RDMA_H__ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA3F3C43334 for ; Tue, 28 Jun 2022 05:59:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 27 Jun 2022 22:52:49 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 28 Jun 2022 09:34:11 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 28 Jun 2022 09:34:11 +0800 Message-ID: Subject: Re: [PATCH v23 03/14] drm/mediatek: add display MDP RDMA support for MT8195 From: CK Hu To: Nancy.Lin , Rob Herring , Matthias Brugger , Chun-Kuang Hu , Philipp Zabel , , AngeloGioacchino Del Regno , CC: , , Yongqiang Niu , David Airlie , "jason-jh . lin" , , , Nick Desaulniers , , , "Nathan Chancellor" , , Date: Tue, 28 Jun 2022 09:34:11 +0800 In-Reply-To: <20220620091930.27797-4-nancy.lin@mediatek.com> References: <20220620091930.27797-1-nancy.lin@mediatek.com> <20220620091930.27797-4-nancy.lin@mediatek.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220627_225252_049124_DF5E78B7 X-CRM114-Status: GOOD ( 27.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Nancy: On Mon, 2022-06-20 at 17:19 +0800, Nancy.Lin wrote: > Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of > the ovl_adaptor component. Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, CK > > Signed-off-by: Nancy.Lin > Reviewed-by: Chun-Kuang Hu > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Tested-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Tested-by: Bo-Chen Chen > --- > drivers/gpu/drm/mediatek/Makefile | 3 +- > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 + > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 315 > ++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 20 ++ > 6 files changed, 346 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h > > diff --git a/drivers/gpu/drm/mediatek/Makefile > b/drivers/gpu/drm/mediatek/Makefile > index a38e88e82d12..6e604a933ed0 100644 > --- a/drivers/gpu/drm/mediatek/Makefile > +++ b/drivers/gpu/drm/mediatek/Makefile > @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \ > mtk_drm_gem.o \ > mtk_drm_plane.o \ > mtk_dsi.o \ > - mtk_dpi.o > + mtk_dpi.o \ > + mtk_mdp_rdma.o > > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > index f13a6f5d512a..2cd1c660ace3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > @@ -8,6 +8,7 @@ > > #include > #include "mtk_drm_plane.h" > +#include "mtk_mdp_rdma.h" > > int mtk_aal_clk_enable(struct device *dev); > void mtk_aal_clk_disable(struct device *dev); > @@ -110,4 +111,10 @@ void mtk_rdma_unregister_vblank_cb(struct device > *dev); > void mtk_rdma_enable_vblank(struct device *dev); > void mtk_rdma_disable_vblank(struct device *dev); > > +int mtk_mdp_rdma_clk_enable(struct device *dev); > +void mtk_mdp_rdma_clk_disable(struct device *dev); > +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt > *cmdq_pkt); > +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt > *cmdq_pkt); > +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg > *cfg, > + struct cmdq_pkt *cmdq_pkt); > #endif > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 076ef59c0c0b..685846cc3490 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -873,6 +873,7 @@ static struct platform_driver * const > mtk_drm_drivers[] = { > &mtk_dpi_driver, > &mtk_drm_platform_driver, > &mtk_dsi_driver, > + &mtk_mdp_rdma_driver, > }; > > static int __init mtk_drm_init(void) > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 9fc922b1684f..7b37b5cf9629 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -61,5 +61,6 @@ extern struct platform_driver mtk_disp_ovl_driver; > extern struct platform_driver mtk_disp_rdma_driver; > extern struct platform_driver mtk_dpi_driver; > extern struct platform_driver mtk_dsi_driver; > +extern struct platform_driver mtk_mdp_rdma_driver; > > #endif /* MTK_DRM_DRV_H */ > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c > new file mode 100644 > index 000000000000..eecfa98ff52e > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c > @@ -0,0 +1,315 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "mtk_disp_drv.h" > +#include "mtk_drm_drv.h" > +#include "mtk_mdp_rdma.h" > + > +#define MDP_RDMA_EN 0x000 > +#define FLD_ROT_ENABLE BIT(0) > +#define MDP_RDMA_RESET 0x008 > +#define MDP_RDMA_CON 0x020 > +#define FLD_OUTPUT_10B BIT(5) > +#define FLD_SIMPLE_MODE BIT(4) > +#define MDP_RDMA_GMCIF_CON 0x028 > +#define FLD_COMMAND_DIV BIT(0) > +#define FLD_EXT_PREULTRA_EN BIT(3) > +#define FLD_RD_REQ_TYPE GENMASK(7, 4) > +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7 > +#define FLD_ULTRA_EN GENMASK(13, 12) > +#define VAL_ULTRA_EN_ENABLE 1 > +#define FLD_PRE_ULTRA_EN GENMASK(17, 16) > +#define VAL_PRE_ULTRA_EN_ENABLE 1 > +#define FLD_EXT_ULTRA_EN BIT(18) > +#define MDP_RDMA_SRC_CON 0x030 > +#define FLD_OUTPUT_ARGB BIT(25) > +#define FLD_BIT_NUMBER GENMASK(19, 18) > +#define FLD_SWAP BIT(14) > +#define FLD_UNIFORM_CONFIG BIT(17) > +#define RDMA_INPUT_10BIT BIT(18) > +#define FLD_SRC_FORMAT GENMASK(3, 0) > +#define MDP_RDMA_COMP_CON 0x038 > +#define FLD_AFBC_EN BIT(22) > +#define FLD_AFBC_YUV_TRANSFORM BIT(21) > +#define FLD_UFBDC_EN BIT(12) > +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060 > +#define FLD_MF_BKGD_WB GENMASK(22, 0) > +#define MDP_RDMA_MF_SRC_SIZE 0x070 > +#define FLD_MF_SRC_H GENMASK(30, 16) > +#define FLD_MF_SRC_W GENMASK(14, 0) > +#define MDP_RDMA_MF_CLIP_SIZE 0x078 > +#define FLD_MF_CLIP_H GENMASK(30, 16) > +#define FLD_MF_CLIP_W GENMASK(14, 0) > +#define MDP_RDMA_SRC_OFFSET_0 0x118 > +#define FLD_SRC_OFFSET_0 GENMASK(31, 0) > +#define MDP_RDMA_TRANSFORM_0 0x200 > +#define FLD_INT_MATRIX_SEL GENMASK(27, 23) > +#define FLD_TRANS_EN BIT(16) > +#define MDP_RDMA_SRC_BASE_0 0xf00 > +#define FLD_SRC_BASE_0 GENMASK(31, 0) > + > +#define RDMA_CSC_FULL709_TO_RGB 5 > +#define RDMA_CSC_BT601_TO_RGB 6 > + > +enum rdma_format { > + RDMA_INPUT_FORMAT_RGB565 = 0, > + RDMA_INPUT_FORMAT_RGB888 = 1, > + RDMA_INPUT_FORMAT_RGBA8888 = 2, > + RDMA_INPUT_FORMAT_ARGB8888 = 3, > + RDMA_INPUT_FORMAT_UYVY = 4, > + RDMA_INPUT_FORMAT_YUY2 = 5, > + RDMA_INPUT_FORMAT_Y8 = 7, > + RDMA_INPUT_FORMAT_YV12 = 8, > + RDMA_INPUT_FORMAT_UYVY_3PL = 9, > + RDMA_INPUT_FORMAT_NV12 = 12, > + RDMA_INPUT_FORMAT_UYVY_2PL = 13, > + RDMA_INPUT_FORMAT_Y410 = 14 > +}; > + > +struct mtk_mdp_rdma { > + void __iomem *regs; > + struct clk *clk; > + struct cmdq_client_reg cmdq_reg; > +}; > + > +static unsigned int rdma_fmt_convert(unsigned int fmt) > +{ > + switch (fmt) { > + default: > + case DRM_FORMAT_RGB565: > + return RDMA_INPUT_FORMAT_RGB565; > + case DRM_FORMAT_BGR565: > + return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP; > + case DRM_FORMAT_RGB888: > + return RDMA_INPUT_FORMAT_RGB888; > + case DRM_FORMAT_BGR888: > + return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP; > + case DRM_FORMAT_RGBX8888: > + case DRM_FORMAT_RGBA8888: > + return RDMA_INPUT_FORMAT_ARGB8888; > + case DRM_FORMAT_BGRX8888: > + case DRM_FORMAT_BGRA8888: > + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP; > + case DRM_FORMAT_XRGB8888: > + case DRM_FORMAT_ARGB8888: > + return RDMA_INPUT_FORMAT_RGBA8888; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP; > + case DRM_FORMAT_ABGR2101010: > + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | > RDMA_INPUT_10BIT; > + case DRM_FORMAT_ARGB2101010: > + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT; > + case DRM_FORMAT_RGBA1010102: > + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | > RDMA_INPUT_10BIT; > + case DRM_FORMAT_BGRA1010102: > + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT; > + case DRM_FORMAT_UYVY: > + return RDMA_INPUT_FORMAT_UYVY; > + case DRM_FORMAT_YUYV: > + return RDMA_INPUT_FORMAT_YUY2; > + } > +} > + > +static unsigned int rdma_color_convert(unsigned int color_encoding) > +{ > + switch (color_encoding) { > + default: > + case DRM_COLOR_YCBCR_BT709: > + return RDMA_CSC_FULL709_TO_RGB; > + case DRM_COLOR_YCBCR_BT601: > + return RDMA_CSC_BT601_TO_RGB; > + } > +} > + > +static void mtk_mdp_rdma_fifo_config(struct device *dev, struct > cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | > VAL_PRE_ULTRA_EN_ENABLE << 16 | > + VAL_ULTRA_EN_ENABLE << 12 | > VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 | > + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, > &priv->cmdq_reg, > + priv->regs, MDP_RDMA_GMCIF_CON, > FLD_EXT_ULTRA_EN | > + FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | > FLD_RD_REQ_TYPE | > + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV); > +} > + > +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt > *cmdq_pkt) > +{ > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg, > + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE); > +} > + > +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt > *cmdq_pkt) > +{ > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, > + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE); > + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, > MDP_RDMA_RESET); > + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, > MDP_RDMA_RESET); > +} > + > +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg > *cfg, > + struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev); > + const struct drm_format_info *fmt_info = drm_format_info(cfg- > >fmt); > + bool csc_enable = fmt_info->is_yuv ? true : false; > + unsigned int src_pitch_y = cfg->pitch; > + unsigned int offset_y = 0; > + > + mtk_mdp_rdma_fifo_config(dev, cmdq_pkt); > + > + mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv- > >cmdq_reg, priv->regs, > + MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG); > + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv- > >cmdq_reg, priv->regs, > + MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT > | FLD_BIT_NUMBER); > + > + if (!csc_enable && fmt_info->has_alpha) > + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv- > >cmdq_reg, > + priv->regs, MDP_RDMA_SRC_CON, > FLD_OUTPUT_ARGB); > + else > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB); > + > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0); > + > + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, > priv->regs, > + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, > FLD_MF_BKGD_WB); > + > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, > MDP_RDMA_COMP_CON, > + FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | > FLD_AFBC_EN); > + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, > priv->regs, > + MDP_RDMA_CON, FLD_OUTPUT_10B); > + mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, > priv->regs, > + MDP_RDMA_CON, FLD_SIMPLE_MODE); > + if (csc_enable) > + mtk_ddp_write_mask(cmdq_pkt, rdma_color_convert(cfg- > >color_encoding) << 23, > + &priv->cmdq_reg, priv->regs, > MDP_RDMA_TRANSFORM_0, > + FLD_INT_MATRIX_SEL); > + mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, > priv->regs, > + MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN); > + > + offset_y = cfg->x_left * fmt_info->cpp[0] + cfg->y_top * > src_pitch_y; > + > + mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0); > + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W); > + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv- > >cmdq_reg, priv->regs, > + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H); > + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv- > >regs, > + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W); > + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv- > >cmdq_reg, priv->regs, > + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H); > +} > + > +int mtk_mdp_rdma_clk_enable(struct device *dev) > +{ > + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev); > + > + clk_prepare_enable(rdma->clk); > + return 0; > +} > + > +void mtk_mdp_rdma_clk_disable(struct device *dev) > +{ > + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev); > + > + clk_disable_unprepare(rdma->clk); > +} > + > +static int mtk_mdp_rdma_bind(struct device *dev, struct device > *master, > + void *data) > +{ > + return 0; > +} > + > +static void mtk_mdp_rdma_unbind(struct device *dev, struct device > *master, > + void *data) > +{ > +} > + > +static const struct component_ops mtk_mdp_rdma_component_ops = { > + .bind = mtk_mdp_rdma_bind, > + .unbind = mtk_mdp_rdma_unbind, > +}; > + > +static int mtk_mdp_rdma_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct resource *res; > + struct mtk_mdp_rdma *priv; > + int ret = 0; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + priv->regs = devm_ioremap_resource(dev, res); > + if (IS_ERR(priv->regs)) { > + dev_err(dev, "failed to ioremap rdma\n"); > + return PTR_ERR(priv->regs); > + } > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) { > + dev_err(dev, "failed to get rdma clk\n"); > + return PTR_ERR(priv->clk); > + } > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); > + if (ret) > + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); > +#endif > + platform_set_drvdata(pdev, priv); > + > + pm_runtime_enable(dev); > + > + ret = component_add(dev, &mtk_mdp_rdma_component_ops); > + if (ret != 0) { > + pm_runtime_disable(dev); > + dev_err(dev, "Failed to add component: %d\n", ret); > + } > + return ret; > +} > + > +static int mtk_mdp_rdma_remove(struct platform_device *pdev) > +{ > + component_del(&pdev->dev, &mtk_mdp_rdma_component_ops); > + pm_runtime_disable(&pdev->dev); > + return 0; > +} > + > +static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = { > + { .compatible = "mediatek,mt8195-vdo1-rdma", }, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match); > + > +struct platform_driver mtk_mdp_rdma_driver = { > + .probe = mtk_mdp_rdma_probe, > + .remove = mtk_mdp_rdma_remove, > + .driver = { > + .name = "mediatek-mdp-rdma", > + .owner = THIS_MODULE, > + .of_match_table = mtk_mdp_rdma_driver_dt_match, > + }, > +}; > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h > new file mode 100644 > index 000000000000..9943ee3aac31 > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#ifndef __MTK_MDP_RDMA_H__ > +#define __MTK_MDP_RDMA_H__ > + > +struct mtk_mdp_rdma_cfg { > + unsigned int pitch; > + unsigned int addr0; > + unsigned int width; > + unsigned int height; > + unsigned int x_left; > + unsigned int y_top; > + int fmt; > + int color_encoding; > +}; > + > +#endif // __MTK_MDP_RDMA_H__ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel