* [PATCH v4 0/7] support subsets of scalar crypto extension
@ 2022-01-11 3:51 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
This patchset implements RISC-V scalar crypto extension v1.0.0 version instructions.
Partial instructions are reused from B-extension.
Specification:
https://github.com/riscv/riscv-crypto
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4
To test rvk implementation, specify cpu argument with 'zks=true,zkn=true'
or
"zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true"
to enable K-extension support. This implementation can pass the ACT tests
for K with our extended act support for qemu (available at
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4-with-act)
v4:
* drop "x-" in exposed properties
* delete unrelated changes
v3:
* add extension check for SEED csr access
v2:
* optimize implementation for brev8, xperm, zip, unzip
* use aes related sbox array from crypto/aes.h
* move sm4_sbox to crypto/sm4.c, and share it with target/arm
Weiwei Li (7):
target/riscv: rvk: add cfg properties for zbk* and zk*
target/riscv: rvk: add implementation of instructions for Zbk*
crypto include/crypto target/arm: move sm4_sbox to crypto
target/riscv: rvk: add implementation of instructions for Zk*
target/riscv: rvk: add CSR support for Zkr
disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
target/riscv: rvk: expose zbk* and zk* properties
crypto/meson.build | 1 +
crypto/sm4.c | 49 +++
disas/riscv.c | 170 +++++++++
include/crypto/sm4.h | 6 +
target/arm/crypto_helper.c | 36 +-
target/riscv/bitmanip_helper.c | 74 ++++
target/riscv/cpu.c | 37 ++
target/riscv/cpu.h | 13 +
target/riscv/cpu_bits.h | 9 +
target/riscv/crypto_helper.c | 446 ++++++++++++++++++++++
target/riscv/csr.c | 74 ++++
target/riscv/helper.h | 42 +++
target/riscv/insn32.decode | 94 ++++-
target/riscv/insn_trans/trans_rvb.c.inc | 127 ++++++-
target/riscv/insn_trans/trans_rvk.c.inc | 467 ++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
target/riscv/pmp.h | 8 +-
target/riscv/translate.c | 8 +
18 files changed, 1594 insertions(+), 70 deletions(-)
create mode 100644 crypto/sm4.c
create mode 100644 include/crypto/sm4.h
create mode 100644 target/riscv/crypto_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
--
2.17.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v4 0/7] support subsets of scalar crypto extension
@ 2022-01-11 3:51 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
This patchset implements RISC-V scalar crypto extension v1.0.0 version instructions.
Partial instructions are reused from B-extension.
Specification:
https://github.com/riscv/riscv-crypto
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4
To test rvk implementation, specify cpu argument with 'zks=true,zkn=true'
or
"zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true"
to enable K-extension support. This implementation can pass the ACT tests
for K with our extended act support for qemu (available at
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4-with-act)
v4:
* drop "x-" in exposed properties
* delete unrelated changes
v3:
* add extension check for SEED csr access
v2:
* optimize implementation for brev8, xperm, zip, unzip
* use aes related sbox array from crypto/aes.h
* move sm4_sbox to crypto/sm4.c, and share it with target/arm
Weiwei Li (7):
target/riscv: rvk: add cfg properties for zbk* and zk*
target/riscv: rvk: add implementation of instructions for Zbk*
crypto include/crypto target/arm: move sm4_sbox to crypto
target/riscv: rvk: add implementation of instructions for Zk*
target/riscv: rvk: add CSR support for Zkr
disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
target/riscv: rvk: expose zbk* and zk* properties
crypto/meson.build | 1 +
crypto/sm4.c | 49 +++
disas/riscv.c | 170 +++++++++
include/crypto/sm4.h | 6 +
target/arm/crypto_helper.c | 36 +-
target/riscv/bitmanip_helper.c | 74 ++++
target/riscv/cpu.c | 37 ++
target/riscv/cpu.h | 13 +
target/riscv/cpu_bits.h | 9 +
target/riscv/crypto_helper.c | 446 ++++++++++++++++++++++
target/riscv/csr.c | 74 ++++
target/riscv/helper.h | 42 +++
target/riscv/insn32.decode | 94 ++++-
target/riscv/insn_trans/trans_rvb.c.inc | 127 ++++++-
target/riscv/insn_trans/trans_rvk.c.inc | 467 ++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
target/riscv/pmp.h | 8 +-
target/riscv/translate.c | 8 +
18 files changed, 1594 insertions(+), 70 deletions(-)
create mode 100644 crypto/sm4.c
create mode 100644 include/crypto/sm4.h
create mode 100644 target/riscv/crypto_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
--
2.17.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v4 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-11 3:51 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 23 +++++++++++++++++++++++
target/riscv/cpu.h | 13 +++++++++++++
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9bc25d3055..b487a8282c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -518,6 +518,29 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
cpu->cfg.ext_d = true;
}
+ if (cpu->cfg.ext_zk) {
+ cpu->cfg.ext_zkn = true;
+ cpu->cfg.ext_zkr = true;
+ cpu->cfg.ext_zkt = true;
+ }
+
+ if (cpu->cfg.ext_zkn) {
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+ cpu->cfg.ext_zkne = true;
+ cpu->cfg.ext_zknd = true;
+ cpu->cfg.ext_zknh = true;
+ }
+
+ if (cpu->cfg.ext_zks) {
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+ cpu->cfg.ext_zksed = true;
+ cpu->cfg.ext_zksh = true;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_i) {
ext |= RVI;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4d63086765..2c14fe8ed9 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -323,7 +323,20 @@ struct RISCVCPU {
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
+ bool ext_zbkb;
+ bool ext_zbkc;
+ bool ext_zbkx;
bool ext_zbs;
+ bool ext_zk;
+ bool ext_zkn;
+ bool ext_zknd;
+ bool ext_zkne;
+ bool ext_zknh;
+ bool ext_zkr;
+ bool ext_zks;
+ bool ext_zksed;
+ bool ext_zksh;
+ bool ext_zkt;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*
@ 2022-01-11 3:51 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 23 +++++++++++++++++++++++
target/riscv/cpu.h | 13 +++++++++++++
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9bc25d3055..b487a8282c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -518,6 +518,29 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
cpu->cfg.ext_d = true;
}
+ if (cpu->cfg.ext_zk) {
+ cpu->cfg.ext_zkn = true;
+ cpu->cfg.ext_zkr = true;
+ cpu->cfg.ext_zkt = true;
+ }
+
+ if (cpu->cfg.ext_zkn) {
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+ cpu->cfg.ext_zkne = true;
+ cpu->cfg.ext_zknd = true;
+ cpu->cfg.ext_zknh = true;
+ }
+
+ if (cpu->cfg.ext_zks) {
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+ cpu->cfg.ext_zksed = true;
+ cpu->cfg.ext_zksh = true;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_i) {
ext |= RVI;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4d63086765..2c14fe8ed9 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -323,7 +323,20 @@ struct RISCVCPU {
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
+ bool ext_zbkb;
+ bool ext_zbkc;
+ bool ext_zbkx;
bool ext_zbs;
+ bool ext_zk;
+ bool ext_zkn;
+ bool ext_zknd;
+ bool ext_zkne;
+ bool ext_zknh;
+ bool ext_zkr;
+ bool ext_zks;
+ bool ext_zksed;
+ bool ext_zksh;
+ bool ext_zkt;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-11 3:51 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- reuse partial instructions of Zbb/Zbc extensions
- add brev8, packh, unzip, zip, etc.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/bitmanip_helper.c | 74 ++++++++++++++
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 52 ++++++----
target/riscv/insn_trans/trans_rvb.c.inc | 127 +++++++++++++++++++++---
target/riscv/translate.c | 7 ++
5 files changed, 234 insertions(+), 31 deletions(-)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index f1b5e5549f..dc3dcf685a 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -49,3 +49,77 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
return result;
}
+
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
+{
+ return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+target_ulong HELPER(brev8)(target_ulong rs1)
+{
+ target_ulong x = rs1;
+ x = do_swap(x, 0x5555555555555555ull, 1);
+ x = do_swap(x, 0x3333333333333333ull, 2);
+ x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
+ return x;
+}
+
+static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
+ uint32_t sz_log2)
+{
+ target_ulong r = 0;
+ target_ulong sz = 1LL << sz_log2;
+ target_ulong mask = (1LL << sz) - 1;
+ for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
+ target_ulong pos = ((rs2 >> i) & mask) << sz_log2;
+ if (pos < sizeof(target_ulong) * 8) {
+ r |= ((rs1 >> pos) & mask) << i;
+ }
+ }
+ return r;
+}
+
+target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
+{
+ return do_xperm(rs1, rs2, 2);
+}
+
+target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
+{
+ return do_xperm(rs1, rs2, 3);
+}
+
+static const uint64_t shuf_masks[] = {
+ dup_const(MO_8, 0x44),
+ dup_const(MO_8, 0x30),
+ dup_const(MO_16, 0x0f00),
+ dup_const(MO_32, 0xff0000)
+};
+
+static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
+ uint64_t maskR, int shift)
+{
+ target_ulong x = src & ~(maskL | maskR);
+ x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
+ return x;
+}
+
+target_ulong HELPER(unzip)(target_ulong rs1)
+{
+ target_ulong x = rs1;
+ x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
+ x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
+ x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
+ x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
+ return x;
+}
+
+target_ulong HELPER(zip)(target_ulong rs1)
+{
+ target_ulong x = rs1;
+ x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
+ x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
+ x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
+ x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
+ return x;
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6cf6d6ce98..2bd6ac8280 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -66,6 +66,11 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
/* Floating Point - Half Precision */
DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5bbedc254c..7491b2d562 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -717,8 +717,22 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r
sh3add_uw 0010000 .......... 110 ..... 0111011 @r
slli_uw 00001 ............ 001 ..... 0011011 @sh
-# *** RV32 Zbb Standard Extension ***
+# *** RV32 Zbb/Zbkb Standard Extension ***
andn 0100000 .......... 111 ..... 0110011 @r
+rol 0110000 .......... 001 ..... 0110011 @r
+ror 0110000 .......... 101 ..... 0110011 @r
+rori 01100 ............ 101 ..... 0010011 @sh
+# The encoding for rev8 differs between RV32 and RV64.
+# rev8_32 denotes the RV32 variant.
+rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
+# The encoding for zext.h differs between RV32 and RV64.
+# zext_h_32 denotes the RV32 variant.
+{
+ zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
+ pack 0000100 ..... ..... 100 ..... 0110011 @r
+}
+xnor 0100000 .......... 100 ..... 0110011 @r
+# *** RV32 extra Zbb Standard Extension ***
clz 011000 000000 ..... 001 ..... 0010011 @r2
cpop 011000 000010 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
@@ -728,23 +742,15 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
orc_b 001010 000111 ..... 101 ..... 0010011 @r2
orn 0100000 .......... 110 ..... 0110011 @r
-# The encoding for rev8 differs between RV32 and RV64.
-# rev8_32 denotes the RV32 variant.
-rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
-rol 0110000 .......... 001 ..... 0110011 @r
-ror 0110000 .......... 101 ..... 0110011 @r
-rori 01100 ............ 101 ..... 0010011 @sh
sext_b 011000 000100 ..... 001 ..... 0010011 @r2
sext_h 011000 000101 ..... 001 ..... 0010011 @r2
-xnor 0100000 .......... 100 ..... 0110011 @r
-# The encoding for zext.h differs between RV32 and RV64.
-# zext_h_32 denotes the RV32 variant.
-zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
+# *** RV32 extra Zbkb Standard Extension ***
+brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
+packh 0000100 .......... 111 ..... 0110011 @r
+unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
+zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
-# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
-clzw 0110000 00000 ..... 001 ..... 0011011 @r2
-ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
-cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
+# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
# The encoding for rev8 differs between RV32 and RV64.
# When executing on RV64, the encoding used in RV32 is an illegal
# instruction, so we use different handler functions to differentiate.
@@ -755,13 +761,25 @@ rorw 0110000 .......... 101 ..... 0111011 @r
# The encoding for zext.h differs between RV32 and RV64.
# When executing on RV64, the encoding used in RV32 is an illegal
# instruction, so we use different handler functions to differentiate.
-zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
+{
+ zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
+ packw 0000100 ..... ..... 100 ..... 0111011 @r
+}
+# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
+cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
-# *** RV32 Zbc Standard Extension ***
+# *** RV32 Zbc/Zbkc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
clmulh 0000101 .......... 011 ..... 0110011 @r
+# *** RV32 extra Zbc Standard Extension ***
clmulr 0000101 .......... 010 ..... 0110011 @r
+# *** RV32 Zbkx Standard Extension ***
+xperm4 0010100 .......... 010 ..... 0110011 @r
+xperm8 0010100 .......... 100 ..... 0110011 @r
+
# *** RV32 Zbs Standard Extension ***
bclr 0100100 .......... 001 ..... 0110011 @r
bclri 01001. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 810431a1d6..a7fb34fb65 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -1,5 +1,5 @@
/*
- * RISC-V translation routines for the Zb[abcs] Standard Extension.
+ * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -42,6 +42,18 @@
} \
} while (0)
+#define REQUIRE_ZBKB(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbkb) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZBKX(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbkx) { \
+ return false; \
+ } \
+} while (0)
+
static void gen_clz(TCGv ret, TCGv arg1)
{
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
@@ -85,19 +97,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
static bool trans_andn(DisasContext *ctx, arg_andn *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_andc_tl);
}
static bool trans_orn(DisasContext *ctx, arg_orn *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_orc_tl);
}
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_eqv_tl);
}
@@ -247,7 +259,7 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
}
@@ -264,7 +276,7 @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
static bool trans_rori(DisasContext *ctx, arg_rori *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
tcg_gen_rotri_tl, gen_roriw, NULL);
}
@@ -289,7 +301,7 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_rol(DisasContext *ctx, arg_rol *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
}
@@ -301,14 +313,14 @@ static void gen_rev8_32(TCGv ret, TCGv src1)
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
REQUIRE_32BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
}
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
}
@@ -403,7 +415,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
}
@@ -411,7 +423,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
}
@@ -419,7 +431,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
}
@@ -483,7 +495,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
{
- REQUIRE_ZBC(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
}
@@ -495,7 +507,7 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
{
- REQUIRE_ZBC(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
}
@@ -504,3 +516,90 @@ static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
REQUIRE_ZBC(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
}
+
+static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
+{
+ tcg_gen_deposit_tl(ret, src1, src2,
+ TARGET_LONG_BITS / 2,
+ TARGET_LONG_BITS / 2);
+}
+
+static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext8u_tl(t, src2);
+ tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
+ tcg_temp_free(t);
+}
+
+static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext16s_tl(t, src2);
+ tcg_gen_deposit_tl(ret, src1, t, 16, 48);
+ tcg_temp_free(t);
+}
+
+static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
+{
+ REQUIRE_ZBKB(ctx);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ gen_helper_brev8(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
+{
+ REQUIRE_ZBKB(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
+}
+
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
+{
+ REQUIRE_ZBKB(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
+}
+
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZBKB(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
+}
+
+static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
+{
+ REQUIRE_ZBKB(ctx);
+ REQUIRE_32BIT(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ gen_helper_unzip(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_zip(DisasContext *ctx, arg_zip *a)
+{
+ REQUIRE_ZBKB(ctx);
+ REQUIRE_32BIT(ctx);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ gen_helper_zip(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
+{
+ REQUIRE_ZBKX(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
+}
+
+static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
+{
+ REQUIRE_ZBKX(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 615048ec87..f3e37ddcd2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -525,6 +525,13 @@ EX_SH(12)
} \
} while (0)
+#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_##A && \
+ !RISCV_CPU(ctx->cs)->cfg.ext_##B) { \
+ return false; \
+ } \
+} while (0)
+
static int ex_rvc_register(DisasContext *ctx, int reg)
{
return 8 + reg;
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
@ 2022-01-11 3:51 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- reuse partial instructions of Zbb/Zbc extensions
- add brev8, packh, unzip, zip, etc.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/bitmanip_helper.c | 74 ++++++++++++++
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 52 ++++++----
target/riscv/insn_trans/trans_rvb.c.inc | 127 +++++++++++++++++++++---
target/riscv/translate.c | 7 ++
5 files changed, 234 insertions(+), 31 deletions(-)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index f1b5e5549f..dc3dcf685a 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -49,3 +49,77 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
return result;
}
+
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
+{
+ return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+target_ulong HELPER(brev8)(target_ulong rs1)
+{
+ target_ulong x = rs1;
+ x = do_swap(x, 0x5555555555555555ull, 1);
+ x = do_swap(x, 0x3333333333333333ull, 2);
+ x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
+ return x;
+}
+
+static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
+ uint32_t sz_log2)
+{
+ target_ulong r = 0;
+ target_ulong sz = 1LL << sz_log2;
+ target_ulong mask = (1LL << sz) - 1;
+ for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
+ target_ulong pos = ((rs2 >> i) & mask) << sz_log2;
+ if (pos < sizeof(target_ulong) * 8) {
+ r |= ((rs1 >> pos) & mask) << i;
+ }
+ }
+ return r;
+}
+
+target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
+{
+ return do_xperm(rs1, rs2, 2);
+}
+
+target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
+{
+ return do_xperm(rs1, rs2, 3);
+}
+
+static const uint64_t shuf_masks[] = {
+ dup_const(MO_8, 0x44),
+ dup_const(MO_8, 0x30),
+ dup_const(MO_16, 0x0f00),
+ dup_const(MO_32, 0xff0000)
+};
+
+static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
+ uint64_t maskR, int shift)
+{
+ target_ulong x = src & ~(maskL | maskR);
+ x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
+ return x;
+}
+
+target_ulong HELPER(unzip)(target_ulong rs1)
+{
+ target_ulong x = rs1;
+ x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
+ x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
+ x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
+ x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
+ return x;
+}
+
+target_ulong HELPER(zip)(target_ulong rs1)
+{
+ target_ulong x = rs1;
+ x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
+ x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
+ x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
+ x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
+ return x;
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6cf6d6ce98..2bd6ac8280 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -66,6 +66,11 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
/* Floating Point - Half Precision */
DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5bbedc254c..7491b2d562 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -717,8 +717,22 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r
sh3add_uw 0010000 .......... 110 ..... 0111011 @r
slli_uw 00001 ............ 001 ..... 0011011 @sh
-# *** RV32 Zbb Standard Extension ***
+# *** RV32 Zbb/Zbkb Standard Extension ***
andn 0100000 .......... 111 ..... 0110011 @r
+rol 0110000 .......... 001 ..... 0110011 @r
+ror 0110000 .......... 101 ..... 0110011 @r
+rori 01100 ............ 101 ..... 0010011 @sh
+# The encoding for rev8 differs between RV32 and RV64.
+# rev8_32 denotes the RV32 variant.
+rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
+# The encoding for zext.h differs between RV32 and RV64.
+# zext_h_32 denotes the RV32 variant.
+{
+ zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
+ pack 0000100 ..... ..... 100 ..... 0110011 @r
+}
+xnor 0100000 .......... 100 ..... 0110011 @r
+# *** RV32 extra Zbb Standard Extension ***
clz 011000 000000 ..... 001 ..... 0010011 @r2
cpop 011000 000010 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
@@ -728,23 +742,15 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
orc_b 001010 000111 ..... 101 ..... 0010011 @r2
orn 0100000 .......... 110 ..... 0110011 @r
-# The encoding for rev8 differs between RV32 and RV64.
-# rev8_32 denotes the RV32 variant.
-rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
-rol 0110000 .......... 001 ..... 0110011 @r
-ror 0110000 .......... 101 ..... 0110011 @r
-rori 01100 ............ 101 ..... 0010011 @sh
sext_b 011000 000100 ..... 001 ..... 0010011 @r2
sext_h 011000 000101 ..... 001 ..... 0010011 @r2
-xnor 0100000 .......... 100 ..... 0110011 @r
-# The encoding for zext.h differs between RV32 and RV64.
-# zext_h_32 denotes the RV32 variant.
-zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
+# *** RV32 extra Zbkb Standard Extension ***
+brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
+packh 0000100 .......... 111 ..... 0110011 @r
+unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
+zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
-# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
-clzw 0110000 00000 ..... 001 ..... 0011011 @r2
-ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
-cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
+# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
# The encoding for rev8 differs between RV32 and RV64.
# When executing on RV64, the encoding used in RV32 is an illegal
# instruction, so we use different handler functions to differentiate.
@@ -755,13 +761,25 @@ rorw 0110000 .......... 101 ..... 0111011 @r
# The encoding for zext.h differs between RV32 and RV64.
# When executing on RV64, the encoding used in RV32 is an illegal
# instruction, so we use different handler functions to differentiate.
-zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
+{
+ zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
+ packw 0000100 ..... ..... 100 ..... 0111011 @r
+}
+# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
+cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
-# *** RV32 Zbc Standard Extension ***
+# *** RV32 Zbc/Zbkc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
clmulh 0000101 .......... 011 ..... 0110011 @r
+# *** RV32 extra Zbc Standard Extension ***
clmulr 0000101 .......... 010 ..... 0110011 @r
+# *** RV32 Zbkx Standard Extension ***
+xperm4 0010100 .......... 010 ..... 0110011 @r
+xperm8 0010100 .......... 100 ..... 0110011 @r
+
# *** RV32 Zbs Standard Extension ***
bclr 0100100 .......... 001 ..... 0110011 @r
bclri 01001. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 810431a1d6..a7fb34fb65 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -1,5 +1,5 @@
/*
- * RISC-V translation routines for the Zb[abcs] Standard Extension.
+ * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -42,6 +42,18 @@
} \
} while (0)
+#define REQUIRE_ZBKB(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbkb) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZBKX(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbkx) { \
+ return false; \
+ } \
+} while (0)
+
static void gen_clz(TCGv ret, TCGv arg1)
{
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
@@ -85,19 +97,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
static bool trans_andn(DisasContext *ctx, arg_andn *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_andc_tl);
}
static bool trans_orn(DisasContext *ctx, arg_orn *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_orc_tl);
}
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_eqv_tl);
}
@@ -247,7 +259,7 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
}
@@ -264,7 +276,7 @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
static bool trans_rori(DisasContext *ctx, arg_rori *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
tcg_gen_rotri_tl, gen_roriw, NULL);
}
@@ -289,7 +301,7 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_rol(DisasContext *ctx, arg_rol *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
}
@@ -301,14 +313,14 @@ static void gen_rev8_32(TCGv ret, TCGv src1)
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
REQUIRE_32BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
}
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
}
@@ -403,7 +415,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
}
@@ -411,7 +423,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
}
@@ -419,7 +431,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
}
@@ -483,7 +495,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
{
- REQUIRE_ZBC(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
}
@@ -495,7 +507,7 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
{
- REQUIRE_ZBC(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
}
@@ -504,3 +516,90 @@ static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
REQUIRE_ZBC(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
}
+
+static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
+{
+ tcg_gen_deposit_tl(ret, src1, src2,
+ TARGET_LONG_BITS / 2,
+ TARGET_LONG_BITS / 2);
+}
+
+static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext8u_tl(t, src2);
+ tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
+ tcg_temp_free(t);
+}
+
+static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext16s_tl(t, src2);
+ tcg_gen_deposit_tl(ret, src1, t, 16, 48);
+ tcg_temp_free(t);
+}
+
+static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
+{
+ REQUIRE_ZBKB(ctx);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ gen_helper_brev8(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
+{
+ REQUIRE_ZBKB(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
+}
+
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
+{
+ REQUIRE_ZBKB(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
+}
+
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZBKB(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
+}
+
+static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
+{
+ REQUIRE_ZBKB(ctx);
+ REQUIRE_32BIT(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ gen_helper_unzip(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_zip(DisasContext *ctx, arg_zip *a)
+{
+ REQUIRE_ZBKB(ctx);
+ REQUIRE_32BIT(ctx);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ gen_helper_zip(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
+{
+ REQUIRE_ZBKX(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
+}
+
+static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
+{
+ REQUIRE_ZBKX(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 615048ec87..f3e37ddcd2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -525,6 +525,13 @@ EX_SH(12)
} \
} while (0)
+#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_##A && \
+ !RISCV_CPU(ctx->cs)->cfg.ext_##B) { \
+ return false; \
+ } \
+} while (0)
+
static int ex_rvc_register(DisasContext *ctx, int reg)
{
return 8 + reg;
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-11 3:51 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
crypto/meson.build | 1 +
crypto/sm4.c | 49 ++++++++++++++++++++++++++++++++++++++
include/crypto/sm4.h | 6 +++++
target/arm/crypto_helper.c | 36 +---------------------------
4 files changed, 57 insertions(+), 35 deletions(-)
create mode 100644 crypto/sm4.c
create mode 100644 include/crypto/sm4.h
diff --git a/crypto/meson.build b/crypto/meson.build
index 95a6a83504..f659fc9035 100644
--- a/crypto/meson.build
+++ b/crypto/meson.build
@@ -38,6 +38,7 @@ crypto_ss.add(when: 'CONFIG_SECRET_KEYRING', if_true: files('secret_keyring.c'))
crypto_ss.add(when: 'CONFIG_AF_ALG', if_true: files('afalg.c', 'cipher-afalg.c', 'hash-afalg.c'))
crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
+util_ss.add(files('sm4.c'))
util_ss.add(files('aes.c'))
util_ss.add(files('init.c'))
if gnutls.found()
diff --git a/crypto/sm4.c b/crypto/sm4.c
new file mode 100644
index 0000000000..9f0cd452c7
--- /dev/null
+++ b/crypto/sm4.c
@@ -0,0 +1,49 @@
+/*
+ * QEMU crypto sm4 support
+ *
+ * Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "crypto/sm4.h"
+
+uint8_t const sm4_sbox[] = {
+ 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
+ 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
+ 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
+ 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+ 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
+ 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
+ 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
+ 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
+ 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
+ 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
+ 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
+ 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
+ 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
+ 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
+ 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
+ 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
+ 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
+ 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
+ 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
+ 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
+ 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
+ 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
+ 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
+ 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
+ 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
+ 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
+ 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
+ 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
+ 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
+ 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
+ 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
+ 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
+};
+
diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
new file mode 100644
index 0000000000..9bd3ebc62e
--- /dev/null
+++ b/include/crypto/sm4.h
@@ -0,0 +1,6 @@
+#ifndef QEMU_SM4_H
+#define QEMU_SM4_H
+
+extern const uint8_t sm4_sbox[256];
+
+#endif
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index 28a84c2dbd..390020672a 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -15,6 +15,7 @@
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
#include "crypto/aes.h"
+#include "crypto/sm4.h"
#include "vec_internal.h"
union CRYPTO_STATE {
@@ -694,41 +695,6 @@ DO_SM3TT(crypto_sm3tt2b, 3)
#undef DO_SM3TT
-static uint8_t const sm4_sbox[] = {
- 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
- 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
- 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
- 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
- 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
- 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
- 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
- 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
- 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
- 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
- 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
- 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
- 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
- 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
- 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
- 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
- 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
- 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
- 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
- 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
- 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
- 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
- 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
- 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
- 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
- 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
- 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
- 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
- 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
- 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
- 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
- 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
-};
-
static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
{
union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
@ 2022-01-11 3:51 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
crypto/meson.build | 1 +
crypto/sm4.c | 49 ++++++++++++++++++++++++++++++++++++++
include/crypto/sm4.h | 6 +++++
target/arm/crypto_helper.c | 36 +---------------------------
4 files changed, 57 insertions(+), 35 deletions(-)
create mode 100644 crypto/sm4.c
create mode 100644 include/crypto/sm4.h
diff --git a/crypto/meson.build b/crypto/meson.build
index 95a6a83504..f659fc9035 100644
--- a/crypto/meson.build
+++ b/crypto/meson.build
@@ -38,6 +38,7 @@ crypto_ss.add(when: 'CONFIG_SECRET_KEYRING', if_true: files('secret_keyring.c'))
crypto_ss.add(when: 'CONFIG_AF_ALG', if_true: files('afalg.c', 'cipher-afalg.c', 'hash-afalg.c'))
crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
+util_ss.add(files('sm4.c'))
util_ss.add(files('aes.c'))
util_ss.add(files('init.c'))
if gnutls.found()
diff --git a/crypto/sm4.c b/crypto/sm4.c
new file mode 100644
index 0000000000..9f0cd452c7
--- /dev/null
+++ b/crypto/sm4.c
@@ -0,0 +1,49 @@
+/*
+ * QEMU crypto sm4 support
+ *
+ * Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "crypto/sm4.h"
+
+uint8_t const sm4_sbox[] = {
+ 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
+ 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
+ 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
+ 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+ 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
+ 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
+ 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
+ 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
+ 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
+ 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
+ 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
+ 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
+ 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
+ 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
+ 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
+ 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
+ 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
+ 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
+ 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
+ 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
+ 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
+ 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
+ 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
+ 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
+ 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
+ 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
+ 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
+ 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
+ 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
+ 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
+ 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
+ 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
+};
+
diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
new file mode 100644
index 0000000000..9bd3ebc62e
--- /dev/null
+++ b/include/crypto/sm4.h
@@ -0,0 +1,6 @@
+#ifndef QEMU_SM4_H
+#define QEMU_SM4_H
+
+extern const uint8_t sm4_sbox[256];
+
+#endif
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index 28a84c2dbd..390020672a 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -15,6 +15,7 @@
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
#include "crypto/aes.h"
+#include "crypto/sm4.h"
#include "vec_internal.h"
union CRYPTO_STATE {
@@ -694,41 +695,6 @@ DO_SM3TT(crypto_sm3tt2b, 3)
#undef DO_SM3TT
-static uint8_t const sm4_sbox[] = {
- 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
- 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
- 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
- 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
- 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
- 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
- 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
- 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
- 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
- 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
- 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
- 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
- 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
- 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
- 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
- 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
- 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
- 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
- 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
- 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
- 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
- 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
- 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
- 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
- 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
- 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
- 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
- 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
- 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
- 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
- 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
- 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
-};
-
static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
{
union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-11 3:51 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/crypto_helper.c | 446 ++++++++++++++++++++++
target/riscv/helper.h | 37 ++
target/riscv/insn32.decode | 42 +++
target/riscv/insn_trans/trans_rvk.c.inc | 467 ++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
target/riscv/translate.c | 1 +
6 files changed, 995 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/crypto_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
new file mode 100644
index 0000000000..344eea4287
--- /dev/null
+++ b/target/riscv/crypto_helper.c
@@ -0,0 +1,446 @@
+/*
+ * RISC-V Crypto Emulation Helpers for QEMU.
+ *
+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "crypto/aes.h"
+#include "crypto/sm4.h"
+
+#define AES_XTIME(a) \
+ ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
+
+#define AES_GFMUL(a, b) (( \
+ (((b) & 0x1) ? (a) : 0) ^ \
+ (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
+ (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
+ (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
+
+#define BY(X, I) ((X >> (8 * I)) & 0xFF)
+
+#define AES_SHIFROWS_LO(RS1, RS2) ( \
+ (((RS1 >> 24) & 0xFF) << 56) | \
+ (((RS2 >> 48) & 0xFF) << 48) | \
+ (((RS2 >> 8) & 0xFF) << 40) | \
+ (((RS1 >> 32) & 0xFF) << 32) | \
+ (((RS2 >> 56) & 0xFF) << 24) | \
+ (((RS2 >> 16) & 0xFF) << 16) | \
+ (((RS1 >> 40) & 0xFF) << 8) | \
+ (((RS1 >> 0) & 0xFF) << 0))
+
+#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
+ (((RS2 >> 24) & 0xFF) << 56) | \
+ (((RS2 >> 48) & 0xFF) << 48) | \
+ (((RS1 >> 8) & 0xFF) << 40) | \
+ (((RS1 >> 32) & 0xFF) << 32) | \
+ (((RS1 >> 56) & 0xFF) << 24) | \
+ (((RS2 >> 16) & 0xFF) << 16) | \
+ (((RS2 >> 40) & 0xFF) << 8) | \
+ (((RS1 >> 0) & 0xFF) << 0))
+
+#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
+ BY(COL, B3) ^ \
+ BY(COL, B2) ^ \
+ AES_GFMUL(BY(COL, B1), 3) ^ \
+ AES_GFMUL(BY(COL, B0), 2) \
+)
+
+#define AES_MIXCOLUMN(COL) ( \
+ AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
+ AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
+ AES_MIXBYTE(COL, 1, 2, 3, 0) << 8 | \
+ AES_MIXBYTE(COL, 0, 1, 2, 3) << 0 \
+)
+
+#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
+ AES_GFMUL(BY(COL, B3), 0x9) ^ \
+ AES_GFMUL(BY(COL, B2), 0xd) ^ \
+ AES_GFMUL(BY(COL, B1), 0xb) ^ \
+ AES_GFMUL(BY(COL, B0), 0xe) \
+)
+
+#define AES_INVMIXCOLUMN(COL) ( \
+ AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
+ AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
+ AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
+ AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0 \
+)
+
+static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
+{
+ uint32_t u;
+ if (fwd) {
+ u = (AES_GFMUL(x, 3) << 24) |
+ (x << 16) |
+ (x << 8) |
+ (AES_GFMUL(x, 2) << 0);
+ } else {
+ u = (AES_GFMUL(x, 0xb) << 24) |
+ (AES_GFMUL(x, 0xd) << 16) |
+ (AES_GFMUL(x, 0x9) << 8) |
+ (AES_GFMUL(x, 0xe) << 0);
+ }
+ return u;
+}
+
+#define XLEN (8 * sizeof(target_ulong))
+#define zext32(x) ((uint64_t)(uint32_t)(x))
+#define sext_xlen(x) (target_ulong)(int32_t)(x)
+
+static inline target_ulong aes32_operation(target_ulong bs, target_ulong rs1,
+ target_ulong rs2, bool enc,
+ bool mix)
+{
+ uint8_t shamt = bs << 3;
+ uint8_t si = rs2 >> shamt;
+ uint8_t so;
+ uint32_t mixed;
+ if (enc) {
+ so = AES_sbox[si];
+ if (mix) {
+ mixed = aes_mixcolumn_byte(so, true);
+ } else {
+ mixed = so;
+ }
+
+ } else {
+ so = AES_isbox[si];
+ if (mix) {
+ mixed = aes_mixcolumn_byte(so, false);
+ } else {
+ mixed = so;
+ }
+ }
+ mixed = (mixed << shamt) | (mixed >> (32 - shamt));
+ target_ulong res = rs1 ^ mixed;
+ return sext_xlen(res);
+}
+
+target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2,
+ target_ulong bs)
+{
+ return aes32_operation(bs, rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2,
+ target_ulong bs)
+{
+ return aes32_operation(bs, rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2,
+ target_ulong bs)
+{
+ return aes32_operation(bs, rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
+ target_ulong bs)
+{
+ return aes32_operation(bs, rs1, rs2, false, false);
+}
+
+static inline target_ulong aes64_operation(target_ulong rs1, target_ulong rs2,
+ bool enc, bool mix)
+{
+ uint64_t RS1 = rs1;
+ uint64_t RS2 = rs2;
+ uint64_t result;
+ uint64_t temp;
+ uint32_t col_0;
+ uint32_t col_1;
+ if (enc) {
+ temp = AES_SHIFROWS_LO(RS1, RS2);
+ temp = (
+ ((uint64_t)AES_sbox[(temp >> 0) & 0xFF] << 0) |
+ ((uint64_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+ ((uint64_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+ ((uint64_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+ ((uint64_t)AES_sbox[(temp >> 32) & 0xFF] << 32) |
+ ((uint64_t)AES_sbox[(temp >> 40) & 0xFF] << 40) |
+ ((uint64_t)AES_sbox[(temp >> 48) & 0xFF] << 48) |
+ ((uint64_t)AES_sbox[(temp >> 56) & 0xFF] << 56)
+ );
+ if (mix) {
+ col_0 = temp & 0xFFFFFFFF;
+ col_1 = temp >> 32 ;
+
+ col_0 = AES_MIXCOLUMN(col_0);
+ col_1 = AES_MIXCOLUMN(col_1);
+
+ result = ((uint64_t)col_1 << 32) | col_0;
+ } else {
+ result = temp;
+ }
+ } else {
+ temp = AES_INVSHIFROWS_LO(RS1, RS2);
+ temp = (
+ ((uint64_t)AES_isbox[(temp >> 0) & 0xFF] << 0) |
+ ((uint64_t)AES_isbox[(temp >> 8) & 0xFF] << 8) |
+ ((uint64_t)AES_isbox[(temp >> 16) & 0xFF] << 16) |
+ ((uint64_t)AES_isbox[(temp >> 24) & 0xFF] << 24) |
+ ((uint64_t)AES_isbox[(temp >> 32) & 0xFF] << 32) |
+ ((uint64_t)AES_isbox[(temp >> 40) & 0xFF] << 40) |
+ ((uint64_t)AES_isbox[(temp >> 48) & 0xFF] << 48) |
+ ((uint64_t)AES_isbox[(temp >> 56) & 0xFF] << 56)
+ );
+ if (mix) {
+ col_0 = temp & 0xFFFFFFFF;
+ col_1 = temp >> 32 ;
+
+ col_0 = AES_INVMIXCOLUMN(col_0);
+ col_1 = AES_INVMIXCOLUMN(col_1);
+
+ result = ((uint64_t)col_1 << 32) | col_0;
+ } else {
+ result = temp;
+ }
+ }
+ return result;
+}
+
+target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes64ds)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, false, false);
+}
+
+target_ulong HELPER(aes64dsm)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes64ks2)(target_ulong rs1, target_ulong rs2)
+{
+ uint64_t RS1 = rs1;
+ uint64_t RS2 = rs2;
+ uint32_t rs1_hi = RS1 >> 32;
+ uint32_t rs2_lo = RS2 ;
+ uint32_t rs2_hi = RS2 >> 32;
+
+ uint32_t r_lo = (rs1_hi ^ rs2_lo) ;
+ uint32_t r_hi = (rs1_hi ^ rs2_lo ^ rs2_hi) ;
+ target_ulong result = ((uint64_t)r_hi << 32) | r_lo ;
+ return result;
+}
+
+target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
+{
+ uint64_t RS1 = rs1;
+ uint8_t round_consts[10] = {
+ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
+ };
+
+ uint8_t enc_rnum = rnum;
+ uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
+ uint8_t rcon_ = 0;
+ target_ulong result;
+
+ if (enc_rnum != 0xA) {
+ temp = (temp >> 8) | (temp << 24); /* Rotate right by 8 */
+ rcon_ = round_consts[enc_rnum];
+ }
+
+ temp =
+ ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+ ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+ ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+ ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0) ;
+
+ temp ^= rcon_;
+
+ result = ((uint64_t)temp << 32) | temp;
+ return result;
+}
+
+target_ulong HELPER(aes64im)(target_ulong rs1)
+{
+ uint64_t RS1 = rs1;
+ uint32_t col_0 = RS1 & 0xFFFFFFFF;
+ uint32_t col_1 = RS1 >> 32 ;
+
+ col_0 = AES_INVMIXCOLUMN(col_0);
+ col_1 = AES_INVMIXCOLUMN(col_1);
+
+ target_ulong result = ((uint64_t)col_1 << 32) | col_0;
+ return result;
+}
+
+#define ROR32(a, amt) ((a << (-amt & 31)) | (a >> (amt & 31)))
+target_ulong HELPER(sha256sig0)(target_ulong rs1)
+{
+ uint32_t a = rs1;
+ return sext_xlen(ROR32(a, 7) ^ ROR32(a, 18) ^ (a >> 3));
+}
+
+target_ulong HELPER(sha256sig1)(target_ulong rs1)
+{
+ uint32_t a = rs1;
+ return sext_xlen(ROR32(a, 17) ^ ROR32(a, 19) ^ (a >> 10));
+}
+
+target_ulong HELPER(sha256sum0)(target_ulong rs1)
+{
+ uint32_t a = rs1;
+ return sext_xlen(ROR32(a, 2) ^ ROR32(a, 13) ^ ROR32(a, 22));
+}
+
+target_ulong HELPER(sha256sum1)(target_ulong rs1)
+{
+ uint32_t a = rs1;
+ return sext_xlen(ROR32(a, 6) ^ ROR32(a, 11) ^ ROR32(a, 25));
+}
+#undef ROR32
+
+target_ulong HELPER(sha512sum0r)(target_ulong RS1, target_ulong RS2)
+{
+ uint64_t result =
+ (zext32(RS1) << 25) ^ (zext32(RS1) << 30) ^ (zext32(RS1) >> 28) ^
+ (zext32(RS2) >> 7) ^ (zext32(RS2) >> 2) ^ (zext32(RS2) << 4);
+ return sext_xlen(result);
+}
+
+target_ulong HELPER(sha512sum1r)(target_ulong RS1, target_ulong RS2)
+{
+ uint64_t result =
+ (zext32(RS1) << 23) ^ (zext32(RS1) >> 14) ^ (zext32(RS1) >> 18) ^
+ (zext32(RS2) >> 9) ^ (zext32(RS2) << 18) ^ (zext32(RS2) << 14);
+ return sext_xlen(result);
+}
+
+target_ulong HELPER(sha512sig0l)(target_ulong RS1, target_ulong RS2)
+{
+ uint64_t result =
+ (zext32(RS1) >> 1) ^ (zext32(RS1) >> 7) ^ (zext32(RS1) >> 8) ^
+ (zext32(RS2) << 31) ^ (zext32(RS2) << 25) ^ (zext32(RS2) << 24);
+ return sext_xlen(result);
+}
+
+target_ulong HELPER(sha512sig0h)(target_ulong RS1, target_ulong RS2)
+{
+ uint64_t result =
+ (zext32(RS1) >> 1) ^ (zext32(RS1) >> 7) ^ (zext32(RS1) >> 8) ^
+ (zext32(RS2) << 31) ^ (zext32(RS2) << 24);
+ return sext_xlen(result);
+}
+
+target_ulong HELPER(sha512sig1l)(target_ulong RS1, target_ulong RS2)
+{
+ uint64_t result =
+ (zext32(RS1) << 3) ^ (zext32(RS1) >> 6) ^ (zext32(RS1) >> 19) ^
+ (zext32(RS2) >> 29) ^ (zext32(RS2) << 26) ^ (zext32(RS2) << 13);
+ return sext_xlen(result);
+}
+
+target_ulong HELPER(sha512sig1h)(target_ulong RS1, target_ulong RS2)
+{
+ uint64_t result =
+ (zext32(RS1) << 3) ^ (zext32(RS1) >> 6) ^ (zext32(RS1) >> 19) ^
+ (zext32(RS2) >> 29) ^ (zext32(RS2) << 13);
+ return sext_xlen(result);
+}
+
+#define ROR64(a, amt) ((a << (-amt & 63)) | (a >> (amt & 63)))
+target_ulong HELPER(sha512sig0)(target_ulong rs1)
+{
+ uint64_t a = rs1;
+ return ROR64(a, 1) ^ ROR64(a, 8) ^ (a >> 7);
+}
+
+target_ulong HELPER(sha512sig1)(target_ulong rs1)
+{
+ uint64_t a = rs1;
+ return ROR64(a, 19) ^ ROR64(a, 61) ^ (a >> 6);
+}
+
+target_ulong HELPER(sha512sum0)(target_ulong rs1)
+{
+ uint64_t a = rs1;
+ return ROR64(a, 28) ^ ROR64(a, 34) ^ ROR64(a, 39);
+}
+
+target_ulong HELPER(sha512sum1)(target_ulong rs1)
+{
+ uint64_t a = rs1;
+ return ROR64(a, 14) ^ ROR64(a, 18) ^ ROR64(a, 41);
+}
+#undef ROR64
+
+#define ROL32(a, amt) ((a >> (-amt & 31)) | (a << (amt & 31)))
+target_ulong HELPER(sm3p0)(target_ulong rs1)
+{
+ uint32_t src = rs1;
+ uint32_t result = src ^ ROL32(src, 9) ^ ROL32(src, 17);
+ return sext_xlen(result);
+}
+target_ulong HELPER(sm3p1)(target_ulong rs1)
+{
+ uint32_t src = rs1;
+ uint32_t result = src ^ ROL32(src, 15) ^ ROL32(src, 23);
+ return sext_xlen(result);
+}
+#undef ROL32
+
+
+target_ulong HELPER(sm4ed)(target_ulong rs2, target_ulong rt, target_ulong bs)
+{
+ uint8_t bs_t = bs;
+
+ uint32_t sb_in = (uint8_t)(rs2 >> (8 * bs_t));
+ uint32_t sb_out = (uint32_t)sm4_sbox[sb_in];
+
+ uint32_t linear = sb_out ^ (sb_out << 8) ^
+ (sb_out << 2) ^
+ (sb_out << 18) ^
+ ((sb_out & 0x3f) << 26) ^
+ ((sb_out & 0xC0) << 10) ;
+
+ uint32_t rotl = (linear << (8 * bs_t)) | (linear >> (32 - 8 * bs_t));
+
+ return sext_xlen(rotl ^ (uint32_t)rt);
+}
+
+target_ulong HELPER(sm4ks)(target_ulong rs2, target_ulong rs1, target_ulong bs)
+{
+ uint8_t bs_t = bs;
+
+ uint32_t sb_in = (uint8_t)(rs2 >> (8 * bs_t));
+ uint32_t sb_out = sm4_sbox[sb_in];
+
+ uint32_t x = sb_out ^
+ ((sb_out & 0x07) << 29) ^ ((sb_out & 0xFE) << 7) ^
+ ((sb_out & 0x01) << 23) ^ ((sb_out & 0xF8) << 13) ;
+
+ uint32_t rotl = (x << (8 * bs_t)) | (x >> (32 - 8 * bs_t));
+
+ return sext_xlen(rotl ^ (uint32_t)rs1);
+}
+#undef XLEN
+#undef zext32
+#undef sext_xlen
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 2bd6ac8280..29319fa26a 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1115,3 +1115,40 @@ DEF_HELPER_5(divu_i128, tl, env, tl, tl, tl, tl)
DEF_HELPER_5(divs_i128, tl, env, tl, tl, tl, tl)
DEF_HELPER_5(remu_i128, tl, env, tl, tl, tl, tl)
DEF_HELPER_5(rems_i128, tl, env, tl, tl, tl, tl)
+
+/* Crypto functions */
+DEF_HELPER_3(aes32esmi, tl, tl, tl, tl)
+DEF_HELPER_3(aes32esi, tl, tl, tl, tl)
+DEF_HELPER_3(aes32dsmi, tl, tl, tl, tl)
+DEF_HELPER_3(aes32dsi, tl, tl, tl, tl)
+
+DEF_HELPER_2(aes64esm, tl, tl, tl)
+DEF_HELPER_2(aes64es, tl, tl, tl)
+DEF_HELPER_2(aes64ds, tl, tl, tl)
+DEF_HELPER_2(aes64dsm, tl, tl, tl)
+DEF_HELPER_2(aes64ks2, tl, tl, tl)
+DEF_HELPER_2(aes64ks1i, tl, tl, tl)
+DEF_HELPER_1(aes64im, tl, tl)
+
+DEF_HELPER_1(sha256sig0, tl, tl)
+DEF_HELPER_1(sha256sig1, tl, tl)
+DEF_HELPER_1(sha256sum0, tl, tl)
+DEF_HELPER_1(sha256sum1, tl, tl)
+
+DEF_HELPER_2(sha512sum0r, tl, tl, tl)
+DEF_HELPER_2(sha512sum1r, tl, tl, tl)
+DEF_HELPER_2(sha512sig0l, tl, tl, tl)
+DEF_HELPER_2(sha512sig0h, tl, tl, tl)
+DEF_HELPER_2(sha512sig1l, tl, tl, tl)
+DEF_HELPER_2(sha512sig1h, tl, tl, tl)
+
+DEF_HELPER_1(sha512sig0, tl, tl)
+DEF_HELPER_1(sha512sig1, tl, tl)
+DEF_HELPER_1(sha512sum0, tl, tl)
+DEF_HELPER_1(sha512sum1, tl, tl)
+
+DEF_HELPER_1(sm3p0, tl, tl)
+DEF_HELPER_1(sm3p1, tl, tl)
+
+DEF_HELPER_3(sm4ed, tl, tl, tl, tl)
+DEF_HELPER_3(sm4ks, tl, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 7491b2d562..a2dd460e81 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -17,8 +17,10 @@
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
+%bs 30:2
%rs3 27:5
%rs2 20:5
+%rnum 20:4
%rs1 15:5
%rd 7:5
%sh5 20:5
@@ -91,6 +93,7 @@
# Formats 64:
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
+@k_aes .. ..... ..... ..... ... ..... ....... %bs %rs2 %rs1 %rd
# Formats 128:
@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
@@ -827,3 +830,42 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
+
+# *** RV32 Zknd Standard Extension ***
+aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
+aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV64 Zknd Standard Extension ***
+aes64dsm 00 11111 ..... ..... 000 ..... 0110011 @r
+aes64ds 00 11101 ..... ..... 000 ..... 0110011 @r
+aes64im 00 11000 00000 ..... 001 ..... 0010011 @r2
+# *** RV32 Zkne Standard Extension ***
+aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
+aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV64 Zkne Standard Extension ***
+aes64es 00 11001 ..... ..... 000 ..... 0110011 @r
+aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
+# *** RV64 Zkne/zknd Standard Extension ***
+aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
+aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 %rnum %rs1 %rd
+# *** RV32 Zknh Standard Extension ***
+sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
+sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
+sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
+sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
+sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
+sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
+sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
+sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
+sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
+sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
+# *** RV64 Zknh Standard Extension ***
+sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
+sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
+sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
+sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
+# *** RV32 Zksh Standard Extension ***
+sm3p0 00 01000 01000 ..... 001 ..... 0010011 @r2
+sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2
+# *** RV32 Zksed Standard Extension ***
+sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes
+sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
new file mode 100644
index 0000000000..da8dea69b8
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -0,0 +1,467 @@
+/*
+ * RISC-V translation routines for the Zk[nd,ne,nh,sed,sh] Standard Extension.
+ *
+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZKND(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zknd) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZKNE(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zkne) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZKNH(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zknh) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZKSED(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zksed) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZKSH(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zksh) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_aes32esmi(DisasContext *ctx, arg_aes32esmi *a)
+{
+ REQUIRE_ZKNE(ctx);
+
+ TCGv bs = tcg_const_tl(a->bs);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes32esmi(dest, src1, src2, bs);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(bs);
+ return true;
+}
+
+static bool trans_aes64esm(DisasContext *ctx, arg_aes64esm *a)
+{
+ REQUIRE_ZKNE(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes64esm(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_aes32esi(DisasContext *ctx, arg_aes32esi *a)
+{
+ REQUIRE_ZKNE(ctx);
+
+ TCGv bs = tcg_const_tl(a->bs);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes32esi(dest, src1, src2, bs);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(bs);
+ return true;
+}
+
+static bool trans_aes64es(DisasContext *ctx, arg_aes64es *a)
+{
+ REQUIRE_ZKNE(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes64es(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_aes32dsmi(DisasContext *ctx, arg_aes32dsmi *a)
+{
+ REQUIRE_ZKND(ctx);
+
+ TCGv bs = tcg_const_tl(a->bs);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes32dsmi(dest, src1, src2, bs);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(bs);
+ return true;
+}
+
+static bool trans_aes64dsm(DisasContext *ctx, arg_aes64dsm *a)
+{
+ REQUIRE_ZKND(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes64dsm(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_aes64ks2(DisasContext *ctx, arg_aes64ks2 *a)
+{
+ REQUIRE_EITHER_EXT(ctx, zknd, zkne);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes64ks2(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(dest);
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+
+ return true;
+}
+
+static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
+{
+ REQUIRE_ZKND(ctx);
+
+ TCGv bs = tcg_const_tl(a->bs);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes32dsi(dest, src1, src2, bs);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(bs);
+ return true;
+}
+
+static bool trans_aes64ds(DisasContext *ctx, arg_aes64ds *a)
+{
+ REQUIRE_ZKND(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes64ds(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_aes64ks1i(DisasContext *ctx, arg_aes64ks1i *a)
+{
+ REQUIRE_EITHER_EXT(ctx, zknd, zkne);
+
+ if (a->rnum > 0xA) {
+ return false;
+ }
+
+ TCGv rnum;
+ rnum = tcg_const_tl(a->rnum);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_aes64ks1i(dest, src1, rnum);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(rnum);
+ return true;
+}
+
+static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
+{
+ REQUIRE_ZKND(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_aes64im(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha256sig0(DisasContext *ctx, arg_sha256sig0 *a)
+{
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha256sig0(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha256sig1(DisasContext *ctx, arg_sha256sig1 *a)
+{
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha256sig1(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha256sum0(DisasContext *ctx, arg_sha256sum0 *a)
+{
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha256sum0(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha256sum1(DisasContext *ctx, arg_sha256sum1 *a)
+{
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha256sum1(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha512sum0r(DisasContext *ctx, arg_sha512sum0r *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sha512sum0r(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha512sum1r(DisasContext *ctx, arg_sha512sum1r *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sha512sum1r(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sha512sig0l(DisasContext *ctx, arg_sha512sig0l *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sha512sig0l(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha512sig0h(DisasContext *ctx, arg_sha512sig0h *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sha512sig0h(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sha512sig1l(DisasContext *ctx, arg_sha512sig1l *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sha512sig1l(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sha512sig1h(DisasContext *ctx, arg_sha512sig1h *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sha512sig1h(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha512sig0(DisasContext *ctx, arg_sha512sig0 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha512sig0(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sha512sig1(DisasContext *ctx, arg_sha512sig1 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha512sig1(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sha512sum0(DisasContext *ctx, arg_sha512sum0 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha512sum0(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sha512sum1(DisasContext *ctx, arg_sha512sum1 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha512sum1(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+/* SM3 */
+static bool trans_sm3p0(DisasContext *ctx, arg_sm3p0 *a)
+{
+ REQUIRE_ZKSH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sm3p0(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sm3p1(DisasContext *ctx, arg_sm3p1 *a)
+{
+ REQUIRE_ZKSH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sm3p1(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+/* SM4 */
+static bool trans_sm4ed(DisasContext *ctx, arg_sm4ed *a)
+{
+ REQUIRE_ZKSED(ctx);
+
+ TCGv bs = tcg_const_tl(a->bs);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sm4ed(dest, src2, src1, bs);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(bs);
+ return true;
+}
+
+static bool trans_sm4ks(DisasContext *ctx, arg_sm4ks *a)
+{
+ REQUIRE_ZKSED(ctx);
+
+ TCGv bs = tcg_const_tl(a->bs);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sm4ks(dest, src2, src1, bs);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(bs);
+ return true;
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index a32158da93..11795a0a9a 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -18,7 +18,8 @@ riscv_ss.add(files(
'vector_helper.c',
'bitmanip_helper.c',
'translate.c',
- 'm128_helper.c'
+ 'm128_helper.c',
+ 'crypto_helper.c'
))
riscv_softmmu_ss = ss.source_set()
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f3e37ddcd2..0ecb7639ea 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -844,6 +844,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvv.c.inc"
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
+#include "insn_trans/trans_rvk.c.inc"
#include "insn_trans/trans_privileged.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
@ 2022-01-11 3:51 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/crypto_helper.c | 446 ++++++++++++++++++++++
target/riscv/helper.h | 37 ++
target/riscv/insn32.decode | 42 +++
target/riscv/insn_trans/trans_rvk.c.inc | 467 ++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
target/riscv/translate.c | 1 +
6 files changed, 995 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/crypto_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
new file mode 100644
index 0000000000..344eea4287
--- /dev/null
+++ b/target/riscv/crypto_helper.c
@@ -0,0 +1,446 @@
+/*
+ * RISC-V Crypto Emulation Helpers for QEMU.
+ *
+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "crypto/aes.h"
+#include "crypto/sm4.h"
+
+#define AES_XTIME(a) \
+ ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
+
+#define AES_GFMUL(a, b) (( \
+ (((b) & 0x1) ? (a) : 0) ^ \
+ (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
+ (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
+ (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
+
+#define BY(X, I) ((X >> (8 * I)) & 0xFF)
+
+#define AES_SHIFROWS_LO(RS1, RS2) ( \
+ (((RS1 >> 24) & 0xFF) << 56) | \
+ (((RS2 >> 48) & 0xFF) << 48) | \
+ (((RS2 >> 8) & 0xFF) << 40) | \
+ (((RS1 >> 32) & 0xFF) << 32) | \
+ (((RS2 >> 56) & 0xFF) << 24) | \
+ (((RS2 >> 16) & 0xFF) << 16) | \
+ (((RS1 >> 40) & 0xFF) << 8) | \
+ (((RS1 >> 0) & 0xFF) << 0))
+
+#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
+ (((RS2 >> 24) & 0xFF) << 56) | \
+ (((RS2 >> 48) & 0xFF) << 48) | \
+ (((RS1 >> 8) & 0xFF) << 40) | \
+ (((RS1 >> 32) & 0xFF) << 32) | \
+ (((RS1 >> 56) & 0xFF) << 24) | \
+ (((RS2 >> 16) & 0xFF) << 16) | \
+ (((RS2 >> 40) & 0xFF) << 8) | \
+ (((RS1 >> 0) & 0xFF) << 0))
+
+#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
+ BY(COL, B3) ^ \
+ BY(COL, B2) ^ \
+ AES_GFMUL(BY(COL, B1), 3) ^ \
+ AES_GFMUL(BY(COL, B0), 2) \
+)
+
+#define AES_MIXCOLUMN(COL) ( \
+ AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
+ AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
+ AES_MIXBYTE(COL, 1, 2, 3, 0) << 8 | \
+ AES_MIXBYTE(COL, 0, 1, 2, 3) << 0 \
+)
+
+#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
+ AES_GFMUL(BY(COL, B3), 0x9) ^ \
+ AES_GFMUL(BY(COL, B2), 0xd) ^ \
+ AES_GFMUL(BY(COL, B1), 0xb) ^ \
+ AES_GFMUL(BY(COL, B0), 0xe) \
+)
+
+#define AES_INVMIXCOLUMN(COL) ( \
+ AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
+ AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
+ AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
+ AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0 \
+)
+
+static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
+{
+ uint32_t u;
+ if (fwd) {
+ u = (AES_GFMUL(x, 3) << 24) |
+ (x << 16) |
+ (x << 8) |
+ (AES_GFMUL(x, 2) << 0);
+ } else {
+ u = (AES_GFMUL(x, 0xb) << 24) |
+ (AES_GFMUL(x, 0xd) << 16) |
+ (AES_GFMUL(x, 0x9) << 8) |
+ (AES_GFMUL(x, 0xe) << 0);
+ }
+ return u;
+}
+
+#define XLEN (8 * sizeof(target_ulong))
+#define zext32(x) ((uint64_t)(uint32_t)(x))
+#define sext_xlen(x) (target_ulong)(int32_t)(x)
+
+static inline target_ulong aes32_operation(target_ulong bs, target_ulong rs1,
+ target_ulong rs2, bool enc,
+ bool mix)
+{
+ uint8_t shamt = bs << 3;
+ uint8_t si = rs2 >> shamt;
+ uint8_t so;
+ uint32_t mixed;
+ if (enc) {
+ so = AES_sbox[si];
+ if (mix) {
+ mixed = aes_mixcolumn_byte(so, true);
+ } else {
+ mixed = so;
+ }
+
+ } else {
+ so = AES_isbox[si];
+ if (mix) {
+ mixed = aes_mixcolumn_byte(so, false);
+ } else {
+ mixed = so;
+ }
+ }
+ mixed = (mixed << shamt) | (mixed >> (32 - shamt));
+ target_ulong res = rs1 ^ mixed;
+ return sext_xlen(res);
+}
+
+target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2,
+ target_ulong bs)
+{
+ return aes32_operation(bs, rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2,
+ target_ulong bs)
+{
+ return aes32_operation(bs, rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2,
+ target_ulong bs)
+{
+ return aes32_operation(bs, rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
+ target_ulong bs)
+{
+ return aes32_operation(bs, rs1, rs2, false, false);
+}
+
+static inline target_ulong aes64_operation(target_ulong rs1, target_ulong rs2,
+ bool enc, bool mix)
+{
+ uint64_t RS1 = rs1;
+ uint64_t RS2 = rs2;
+ uint64_t result;
+ uint64_t temp;
+ uint32_t col_0;
+ uint32_t col_1;
+ if (enc) {
+ temp = AES_SHIFROWS_LO(RS1, RS2);
+ temp = (
+ ((uint64_t)AES_sbox[(temp >> 0) & 0xFF] << 0) |
+ ((uint64_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+ ((uint64_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+ ((uint64_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+ ((uint64_t)AES_sbox[(temp >> 32) & 0xFF] << 32) |
+ ((uint64_t)AES_sbox[(temp >> 40) & 0xFF] << 40) |
+ ((uint64_t)AES_sbox[(temp >> 48) & 0xFF] << 48) |
+ ((uint64_t)AES_sbox[(temp >> 56) & 0xFF] << 56)
+ );
+ if (mix) {
+ col_0 = temp & 0xFFFFFFFF;
+ col_1 = temp >> 32 ;
+
+ col_0 = AES_MIXCOLUMN(col_0);
+ col_1 = AES_MIXCOLUMN(col_1);
+
+ result = ((uint64_t)col_1 << 32) | col_0;
+ } else {
+ result = temp;
+ }
+ } else {
+ temp = AES_INVSHIFROWS_LO(RS1, RS2);
+ temp = (
+ ((uint64_t)AES_isbox[(temp >> 0) & 0xFF] << 0) |
+ ((uint64_t)AES_isbox[(temp >> 8) & 0xFF] << 8) |
+ ((uint64_t)AES_isbox[(temp >> 16) & 0xFF] << 16) |
+ ((uint64_t)AES_isbox[(temp >> 24) & 0xFF] << 24) |
+ ((uint64_t)AES_isbox[(temp >> 32) & 0xFF] << 32) |
+ ((uint64_t)AES_isbox[(temp >> 40) & 0xFF] << 40) |
+ ((uint64_t)AES_isbox[(temp >> 48) & 0xFF] << 48) |
+ ((uint64_t)AES_isbox[(temp >> 56) & 0xFF] << 56)
+ );
+ if (mix) {
+ col_0 = temp & 0xFFFFFFFF;
+ col_1 = temp >> 32 ;
+
+ col_0 = AES_INVMIXCOLUMN(col_0);
+ col_1 = AES_INVMIXCOLUMN(col_1);
+
+ result = ((uint64_t)col_1 << 32) | col_0;
+ } else {
+ result = temp;
+ }
+ }
+ return result;
+}
+
+target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes64ds)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, false, false);
+}
+
+target_ulong HELPER(aes64dsm)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes64ks2)(target_ulong rs1, target_ulong rs2)
+{
+ uint64_t RS1 = rs1;
+ uint64_t RS2 = rs2;
+ uint32_t rs1_hi = RS1 >> 32;
+ uint32_t rs2_lo = RS2 ;
+ uint32_t rs2_hi = RS2 >> 32;
+
+ uint32_t r_lo = (rs1_hi ^ rs2_lo) ;
+ uint32_t r_hi = (rs1_hi ^ rs2_lo ^ rs2_hi) ;
+ target_ulong result = ((uint64_t)r_hi << 32) | r_lo ;
+ return result;
+}
+
+target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
+{
+ uint64_t RS1 = rs1;
+ uint8_t round_consts[10] = {
+ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
+ };
+
+ uint8_t enc_rnum = rnum;
+ uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
+ uint8_t rcon_ = 0;
+ target_ulong result;
+
+ if (enc_rnum != 0xA) {
+ temp = (temp >> 8) | (temp << 24); /* Rotate right by 8 */
+ rcon_ = round_consts[enc_rnum];
+ }
+
+ temp =
+ ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+ ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+ ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+ ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0) ;
+
+ temp ^= rcon_;
+
+ result = ((uint64_t)temp << 32) | temp;
+ return result;
+}
+
+target_ulong HELPER(aes64im)(target_ulong rs1)
+{
+ uint64_t RS1 = rs1;
+ uint32_t col_0 = RS1 & 0xFFFFFFFF;
+ uint32_t col_1 = RS1 >> 32 ;
+
+ col_0 = AES_INVMIXCOLUMN(col_0);
+ col_1 = AES_INVMIXCOLUMN(col_1);
+
+ target_ulong result = ((uint64_t)col_1 << 32) | col_0;
+ return result;
+}
+
+#define ROR32(a, amt) ((a << (-amt & 31)) | (a >> (amt & 31)))
+target_ulong HELPER(sha256sig0)(target_ulong rs1)
+{
+ uint32_t a = rs1;
+ return sext_xlen(ROR32(a, 7) ^ ROR32(a, 18) ^ (a >> 3));
+}
+
+target_ulong HELPER(sha256sig1)(target_ulong rs1)
+{
+ uint32_t a = rs1;
+ return sext_xlen(ROR32(a, 17) ^ ROR32(a, 19) ^ (a >> 10));
+}
+
+target_ulong HELPER(sha256sum0)(target_ulong rs1)
+{
+ uint32_t a = rs1;
+ return sext_xlen(ROR32(a, 2) ^ ROR32(a, 13) ^ ROR32(a, 22));
+}
+
+target_ulong HELPER(sha256sum1)(target_ulong rs1)
+{
+ uint32_t a = rs1;
+ return sext_xlen(ROR32(a, 6) ^ ROR32(a, 11) ^ ROR32(a, 25));
+}
+#undef ROR32
+
+target_ulong HELPER(sha512sum0r)(target_ulong RS1, target_ulong RS2)
+{
+ uint64_t result =
+ (zext32(RS1) << 25) ^ (zext32(RS1) << 30) ^ (zext32(RS1) >> 28) ^
+ (zext32(RS2) >> 7) ^ (zext32(RS2) >> 2) ^ (zext32(RS2) << 4);
+ return sext_xlen(result);
+}
+
+target_ulong HELPER(sha512sum1r)(target_ulong RS1, target_ulong RS2)
+{
+ uint64_t result =
+ (zext32(RS1) << 23) ^ (zext32(RS1) >> 14) ^ (zext32(RS1) >> 18) ^
+ (zext32(RS2) >> 9) ^ (zext32(RS2) << 18) ^ (zext32(RS2) << 14);
+ return sext_xlen(result);
+}
+
+target_ulong HELPER(sha512sig0l)(target_ulong RS1, target_ulong RS2)
+{
+ uint64_t result =
+ (zext32(RS1) >> 1) ^ (zext32(RS1) >> 7) ^ (zext32(RS1) >> 8) ^
+ (zext32(RS2) << 31) ^ (zext32(RS2) << 25) ^ (zext32(RS2) << 24);
+ return sext_xlen(result);
+}
+
+target_ulong HELPER(sha512sig0h)(target_ulong RS1, target_ulong RS2)
+{
+ uint64_t result =
+ (zext32(RS1) >> 1) ^ (zext32(RS1) >> 7) ^ (zext32(RS1) >> 8) ^
+ (zext32(RS2) << 31) ^ (zext32(RS2) << 24);
+ return sext_xlen(result);
+}
+
+target_ulong HELPER(sha512sig1l)(target_ulong RS1, target_ulong RS2)
+{
+ uint64_t result =
+ (zext32(RS1) << 3) ^ (zext32(RS1) >> 6) ^ (zext32(RS1) >> 19) ^
+ (zext32(RS2) >> 29) ^ (zext32(RS2) << 26) ^ (zext32(RS2) << 13);
+ return sext_xlen(result);
+}
+
+target_ulong HELPER(sha512sig1h)(target_ulong RS1, target_ulong RS2)
+{
+ uint64_t result =
+ (zext32(RS1) << 3) ^ (zext32(RS1) >> 6) ^ (zext32(RS1) >> 19) ^
+ (zext32(RS2) >> 29) ^ (zext32(RS2) << 13);
+ return sext_xlen(result);
+}
+
+#define ROR64(a, amt) ((a << (-amt & 63)) | (a >> (amt & 63)))
+target_ulong HELPER(sha512sig0)(target_ulong rs1)
+{
+ uint64_t a = rs1;
+ return ROR64(a, 1) ^ ROR64(a, 8) ^ (a >> 7);
+}
+
+target_ulong HELPER(sha512sig1)(target_ulong rs1)
+{
+ uint64_t a = rs1;
+ return ROR64(a, 19) ^ ROR64(a, 61) ^ (a >> 6);
+}
+
+target_ulong HELPER(sha512sum0)(target_ulong rs1)
+{
+ uint64_t a = rs1;
+ return ROR64(a, 28) ^ ROR64(a, 34) ^ ROR64(a, 39);
+}
+
+target_ulong HELPER(sha512sum1)(target_ulong rs1)
+{
+ uint64_t a = rs1;
+ return ROR64(a, 14) ^ ROR64(a, 18) ^ ROR64(a, 41);
+}
+#undef ROR64
+
+#define ROL32(a, amt) ((a >> (-amt & 31)) | (a << (amt & 31)))
+target_ulong HELPER(sm3p0)(target_ulong rs1)
+{
+ uint32_t src = rs1;
+ uint32_t result = src ^ ROL32(src, 9) ^ ROL32(src, 17);
+ return sext_xlen(result);
+}
+target_ulong HELPER(sm3p1)(target_ulong rs1)
+{
+ uint32_t src = rs1;
+ uint32_t result = src ^ ROL32(src, 15) ^ ROL32(src, 23);
+ return sext_xlen(result);
+}
+#undef ROL32
+
+
+target_ulong HELPER(sm4ed)(target_ulong rs2, target_ulong rt, target_ulong bs)
+{
+ uint8_t bs_t = bs;
+
+ uint32_t sb_in = (uint8_t)(rs2 >> (8 * bs_t));
+ uint32_t sb_out = (uint32_t)sm4_sbox[sb_in];
+
+ uint32_t linear = sb_out ^ (sb_out << 8) ^
+ (sb_out << 2) ^
+ (sb_out << 18) ^
+ ((sb_out & 0x3f) << 26) ^
+ ((sb_out & 0xC0) << 10) ;
+
+ uint32_t rotl = (linear << (8 * bs_t)) | (linear >> (32 - 8 * bs_t));
+
+ return sext_xlen(rotl ^ (uint32_t)rt);
+}
+
+target_ulong HELPER(sm4ks)(target_ulong rs2, target_ulong rs1, target_ulong bs)
+{
+ uint8_t bs_t = bs;
+
+ uint32_t sb_in = (uint8_t)(rs2 >> (8 * bs_t));
+ uint32_t sb_out = sm4_sbox[sb_in];
+
+ uint32_t x = sb_out ^
+ ((sb_out & 0x07) << 29) ^ ((sb_out & 0xFE) << 7) ^
+ ((sb_out & 0x01) << 23) ^ ((sb_out & 0xF8) << 13) ;
+
+ uint32_t rotl = (x << (8 * bs_t)) | (x >> (32 - 8 * bs_t));
+
+ return sext_xlen(rotl ^ (uint32_t)rs1);
+}
+#undef XLEN
+#undef zext32
+#undef sext_xlen
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 2bd6ac8280..29319fa26a 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1115,3 +1115,40 @@ DEF_HELPER_5(divu_i128, tl, env, tl, tl, tl, tl)
DEF_HELPER_5(divs_i128, tl, env, tl, tl, tl, tl)
DEF_HELPER_5(remu_i128, tl, env, tl, tl, tl, tl)
DEF_HELPER_5(rems_i128, tl, env, tl, tl, tl, tl)
+
+/* Crypto functions */
+DEF_HELPER_3(aes32esmi, tl, tl, tl, tl)
+DEF_HELPER_3(aes32esi, tl, tl, tl, tl)
+DEF_HELPER_3(aes32dsmi, tl, tl, tl, tl)
+DEF_HELPER_3(aes32dsi, tl, tl, tl, tl)
+
+DEF_HELPER_2(aes64esm, tl, tl, tl)
+DEF_HELPER_2(aes64es, tl, tl, tl)
+DEF_HELPER_2(aes64ds, tl, tl, tl)
+DEF_HELPER_2(aes64dsm, tl, tl, tl)
+DEF_HELPER_2(aes64ks2, tl, tl, tl)
+DEF_HELPER_2(aes64ks1i, tl, tl, tl)
+DEF_HELPER_1(aes64im, tl, tl)
+
+DEF_HELPER_1(sha256sig0, tl, tl)
+DEF_HELPER_1(sha256sig1, tl, tl)
+DEF_HELPER_1(sha256sum0, tl, tl)
+DEF_HELPER_1(sha256sum1, tl, tl)
+
+DEF_HELPER_2(sha512sum0r, tl, tl, tl)
+DEF_HELPER_2(sha512sum1r, tl, tl, tl)
+DEF_HELPER_2(sha512sig0l, tl, tl, tl)
+DEF_HELPER_2(sha512sig0h, tl, tl, tl)
+DEF_HELPER_2(sha512sig1l, tl, tl, tl)
+DEF_HELPER_2(sha512sig1h, tl, tl, tl)
+
+DEF_HELPER_1(sha512sig0, tl, tl)
+DEF_HELPER_1(sha512sig1, tl, tl)
+DEF_HELPER_1(sha512sum0, tl, tl)
+DEF_HELPER_1(sha512sum1, tl, tl)
+
+DEF_HELPER_1(sm3p0, tl, tl)
+DEF_HELPER_1(sm3p1, tl, tl)
+
+DEF_HELPER_3(sm4ed, tl, tl, tl, tl)
+DEF_HELPER_3(sm4ks, tl, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 7491b2d562..a2dd460e81 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -17,8 +17,10 @@
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
+%bs 30:2
%rs3 27:5
%rs2 20:5
+%rnum 20:4
%rs1 15:5
%rd 7:5
%sh5 20:5
@@ -91,6 +93,7 @@
# Formats 64:
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
+@k_aes .. ..... ..... ..... ... ..... ....... %bs %rs2 %rs1 %rd
# Formats 128:
@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
@@ -827,3 +830,42 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
+
+# *** RV32 Zknd Standard Extension ***
+aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
+aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV64 Zknd Standard Extension ***
+aes64dsm 00 11111 ..... ..... 000 ..... 0110011 @r
+aes64ds 00 11101 ..... ..... 000 ..... 0110011 @r
+aes64im 00 11000 00000 ..... 001 ..... 0010011 @r2
+# *** RV32 Zkne Standard Extension ***
+aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
+aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV64 Zkne Standard Extension ***
+aes64es 00 11001 ..... ..... 000 ..... 0110011 @r
+aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
+# *** RV64 Zkne/zknd Standard Extension ***
+aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
+aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 %rnum %rs1 %rd
+# *** RV32 Zknh Standard Extension ***
+sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
+sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
+sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
+sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
+sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
+sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
+sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
+sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
+sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
+sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
+# *** RV64 Zknh Standard Extension ***
+sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
+sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
+sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
+sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
+# *** RV32 Zksh Standard Extension ***
+sm3p0 00 01000 01000 ..... 001 ..... 0010011 @r2
+sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2
+# *** RV32 Zksed Standard Extension ***
+sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes
+sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
new file mode 100644
index 0000000000..da8dea69b8
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -0,0 +1,467 @@
+/*
+ * RISC-V translation routines for the Zk[nd,ne,nh,sed,sh] Standard Extension.
+ *
+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZKND(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zknd) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZKNE(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zkne) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZKNH(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zknh) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZKSED(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zksed) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZKSH(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zksh) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_aes32esmi(DisasContext *ctx, arg_aes32esmi *a)
+{
+ REQUIRE_ZKNE(ctx);
+
+ TCGv bs = tcg_const_tl(a->bs);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes32esmi(dest, src1, src2, bs);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(bs);
+ return true;
+}
+
+static bool trans_aes64esm(DisasContext *ctx, arg_aes64esm *a)
+{
+ REQUIRE_ZKNE(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes64esm(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_aes32esi(DisasContext *ctx, arg_aes32esi *a)
+{
+ REQUIRE_ZKNE(ctx);
+
+ TCGv bs = tcg_const_tl(a->bs);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes32esi(dest, src1, src2, bs);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(bs);
+ return true;
+}
+
+static bool trans_aes64es(DisasContext *ctx, arg_aes64es *a)
+{
+ REQUIRE_ZKNE(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes64es(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_aes32dsmi(DisasContext *ctx, arg_aes32dsmi *a)
+{
+ REQUIRE_ZKND(ctx);
+
+ TCGv bs = tcg_const_tl(a->bs);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes32dsmi(dest, src1, src2, bs);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(bs);
+ return true;
+}
+
+static bool trans_aes64dsm(DisasContext *ctx, arg_aes64dsm *a)
+{
+ REQUIRE_ZKND(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes64dsm(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_aes64ks2(DisasContext *ctx, arg_aes64ks2 *a)
+{
+ REQUIRE_EITHER_EXT(ctx, zknd, zkne);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes64ks2(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(dest);
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+
+ return true;
+}
+
+static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
+{
+ REQUIRE_ZKND(ctx);
+
+ TCGv bs = tcg_const_tl(a->bs);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes32dsi(dest, src1, src2, bs);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(bs);
+ return true;
+}
+
+static bool trans_aes64ds(DisasContext *ctx, arg_aes64ds *a)
+{
+ REQUIRE_ZKND(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_aes64ds(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_aes64ks1i(DisasContext *ctx, arg_aes64ks1i *a)
+{
+ REQUIRE_EITHER_EXT(ctx, zknd, zkne);
+
+ if (a->rnum > 0xA) {
+ return false;
+ }
+
+ TCGv rnum;
+ rnum = tcg_const_tl(a->rnum);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_aes64ks1i(dest, src1, rnum);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(rnum);
+ return true;
+}
+
+static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
+{
+ REQUIRE_ZKND(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_aes64im(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha256sig0(DisasContext *ctx, arg_sha256sig0 *a)
+{
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha256sig0(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha256sig1(DisasContext *ctx, arg_sha256sig1 *a)
+{
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha256sig1(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha256sum0(DisasContext *ctx, arg_sha256sum0 *a)
+{
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha256sum0(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha256sum1(DisasContext *ctx, arg_sha256sum1 *a)
+{
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha256sum1(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha512sum0r(DisasContext *ctx, arg_sha512sum0r *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sha512sum0r(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha512sum1r(DisasContext *ctx, arg_sha512sum1r *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sha512sum1r(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sha512sig0l(DisasContext *ctx, arg_sha512sig0l *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sha512sig0l(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha512sig0h(DisasContext *ctx, arg_sha512sig0h *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sha512sig0h(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sha512sig1l(DisasContext *ctx, arg_sha512sig1l *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sha512sig1l(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sha512sig1h(DisasContext *ctx, arg_sha512sig1h *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sha512sig1h(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_sha512sig0(DisasContext *ctx, arg_sha512sig0 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha512sig0(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sha512sig1(DisasContext *ctx, arg_sha512sig1 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha512sig1(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sha512sum0(DisasContext *ctx, arg_sha512sum0 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha512sum0(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sha512sum1(DisasContext *ctx, arg_sha512sum1 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sha512sum1(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+/* SM3 */
+static bool trans_sm3p0(DisasContext *ctx, arg_sm3p0 *a)
+{
+ REQUIRE_ZKSH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sm3p0(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_sm3p1(DisasContext *ctx, arg_sm3p1 *a)
+{
+ REQUIRE_ZKSH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ gen_helper_sm3p1(dest, src1);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+/* SM4 */
+static bool trans_sm4ed(DisasContext *ctx, arg_sm4ed *a)
+{
+ REQUIRE_ZKSED(ctx);
+
+ TCGv bs = tcg_const_tl(a->bs);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sm4ed(dest, src2, src1, bs);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(bs);
+ return true;
+}
+
+static bool trans_sm4ks(DisasContext *ctx, arg_sm4ks *a)
+{
+ REQUIRE_ZKSED(ctx);
+
+ TCGv bs = tcg_const_tl(a->bs);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ gen_helper_sm4ks(dest, src2, src1, bs);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free(bs);
+ return true;
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index a32158da93..11795a0a9a 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -18,7 +18,8 @@ riscv_ss.add(files(
'vector_helper.c',
'bitmanip_helper.c',
'translate.c',
- 'm128_helper.c'
+ 'm128_helper.c',
+ 'crypto_helper.c'
))
riscv_softmmu_ss = ss.source_set()
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f3e37ddcd2..0ecb7639ea 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -844,6 +844,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvv.c.inc"
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
+#include "insn_trans/trans_rvk.c.inc"
#include "insn_trans/trans_privileged.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-11 3:51 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- add SEED CSR
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu_bits.h | 9 +++++
target/riscv/csr.c | 74 +++++++++++++++++++++++++++++++++++++++++
target/riscv/pmp.h | 8 +++--
3 files changed, 88 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5a6d49aa64..65c708622b 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -374,6 +374,9 @@
#define CSR_VSPMMASK 0x2c1
#define CSR_VSPMBASE 0x2c2
+/* Crypto Extension */
+#define CSR_SEED 0x015
+
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
@@ -628,4 +631,10 @@ typedef enum RISCVException {
#define UMTE_U_PM_INSN U_PM_INSN
#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
+/* seed CSR bits */
+#define SEED_OPST (0b11 << 30)
+#define SEED_OPST_BIST (0b00 << 30)
+#define SEED_OPST_WAIT (0b01 << 30)
+#define SEED_OPST_ES16 (0b10 << 30)
+#define SEED_OPST_DEAD (0b11 << 30)
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index adb3d4381d..9d93e72f68 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -22,6 +22,8 @@
#include "cpu.h"
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
+#include "qemu/guest-random.h"
+#include "qapi/error.h"
/* CSR function table public API */
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
@@ -222,6 +224,38 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
}
#endif
+/* Predicates */
+static RISCVException seed(CPURISCVState *env, int csrno)
+{
+ RISCVCPU *cpu = env_archcpu(env);
+ if (!cpu->cfg.ext_zkr) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#if !defined(CONFIG_USER_ONLY)
+ if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) {
+ /* Hypervisor extension is supported */
+ if (riscv_cpu_virt_enabled(env) && (env->priv != PRV_M)) {
+ if (env->mseccfg & MSECCFG_SSEED) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ } else {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ }
+ }
+ if (env->priv == PRV_M) {
+ return RISCV_EXCP_NONE;
+ } else if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
+ return RISCV_EXCP_NONE;
+ } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
+ return RISCV_EXCP_NONE;
+ } else {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#else
+ return RISCV_EXCP_NONE;
+#endif
+}
+
/* User Floating-Point CSRs */
static RISCVException read_fflags(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -1785,6 +1819,39 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
#endif
+/* Crypto Extension */
+static int read_seed(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = 0;
+ uint32_t return_status = SEED_OPST_ES16;
+ *val = (*val) | return_status;
+ if (return_status == SEED_OPST_ES16) {
+ uint16_t random_number;
+ Error *err = NULL;
+ if (qemu_guest_getrandom(&random_number, sizeof(random_number),
+ &err) < 0) {
+ qemu_log_mask(LOG_UNIMP, "Seed: Crypto failure: %s",
+ error_get_pretty(err));
+ error_free(err);
+ return -1;
+ }
+ *val = (*val) | random_number;
+ } else if (return_status == SEED_OPST_BIST) {
+ /* Do nothing */
+ } else if (return_status == SEED_OPST_WAIT) {
+ /* Do nothing */
+ } else if (return_status == SEED_OPST_DEAD) {
+ /* Do nothing */
+ }
+ return 0;
+}
+
+static RISCVException write_seed(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ return RISCV_EXCP_NONE;
+}
+
/*
* riscv_csrrw - read and/or update control and status register
*
@@ -1823,6 +1890,10 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST;
}
+ if (!write_mask && (csrno == CSR_SEED)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
/* ensure the CSR extension is enabled. */
if (!cpu->cfg.ext_icsr) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -2011,6 +2082,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_TIME] = { "time", ctr, read_time },
[CSR_TIMEH] = { "timeh", ctr32, read_timeh },
+ /* Crypto Extension */
+ [CSR_SEED] = { "seed", seed, read_seed, write_seed},
+
#if !defined(CONFIG_USER_ONLY)
/* Machine Timers and Counters */
[CSR_MCYCLE] = { "mcycle", any, read_instret },
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index a9a0b363a7..83135849bb 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -37,9 +37,11 @@ typedef enum {
} pmp_am_t;
typedef enum {
- MSECCFG_MML = 1 << 0,
- MSECCFG_MMWP = 1 << 1,
- MSECCFG_RLB = 1 << 2
+ MSECCFG_MML = 1 << 0,
+ MSECCFG_MMWP = 1 << 1,
+ MSECCFG_RLB = 1 << 2,
+ MSECCFG_USEED = 1 << 8,
+ MSECCFG_SSEED = 1 << 9
} mseccfg_field_t;
typedef struct {
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
@ 2022-01-11 3:51 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- add SEED CSR
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu_bits.h | 9 +++++
target/riscv/csr.c | 74 +++++++++++++++++++++++++++++++++++++++++
target/riscv/pmp.h | 8 +++--
3 files changed, 88 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5a6d49aa64..65c708622b 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -374,6 +374,9 @@
#define CSR_VSPMMASK 0x2c1
#define CSR_VSPMBASE 0x2c2
+/* Crypto Extension */
+#define CSR_SEED 0x015
+
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
@@ -628,4 +631,10 @@ typedef enum RISCVException {
#define UMTE_U_PM_INSN U_PM_INSN
#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
+/* seed CSR bits */
+#define SEED_OPST (0b11 << 30)
+#define SEED_OPST_BIST (0b00 << 30)
+#define SEED_OPST_WAIT (0b01 << 30)
+#define SEED_OPST_ES16 (0b10 << 30)
+#define SEED_OPST_DEAD (0b11 << 30)
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index adb3d4381d..9d93e72f68 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -22,6 +22,8 @@
#include "cpu.h"
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
+#include "qemu/guest-random.h"
+#include "qapi/error.h"
/* CSR function table public API */
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
@@ -222,6 +224,38 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
}
#endif
+/* Predicates */
+static RISCVException seed(CPURISCVState *env, int csrno)
+{
+ RISCVCPU *cpu = env_archcpu(env);
+ if (!cpu->cfg.ext_zkr) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#if !defined(CONFIG_USER_ONLY)
+ if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) {
+ /* Hypervisor extension is supported */
+ if (riscv_cpu_virt_enabled(env) && (env->priv != PRV_M)) {
+ if (env->mseccfg & MSECCFG_SSEED) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ } else {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ }
+ }
+ if (env->priv == PRV_M) {
+ return RISCV_EXCP_NONE;
+ } else if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
+ return RISCV_EXCP_NONE;
+ } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
+ return RISCV_EXCP_NONE;
+ } else {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#else
+ return RISCV_EXCP_NONE;
+#endif
+}
+
/* User Floating-Point CSRs */
static RISCVException read_fflags(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -1785,6 +1819,39 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
#endif
+/* Crypto Extension */
+static int read_seed(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = 0;
+ uint32_t return_status = SEED_OPST_ES16;
+ *val = (*val) | return_status;
+ if (return_status == SEED_OPST_ES16) {
+ uint16_t random_number;
+ Error *err = NULL;
+ if (qemu_guest_getrandom(&random_number, sizeof(random_number),
+ &err) < 0) {
+ qemu_log_mask(LOG_UNIMP, "Seed: Crypto failure: %s",
+ error_get_pretty(err));
+ error_free(err);
+ return -1;
+ }
+ *val = (*val) | random_number;
+ } else if (return_status == SEED_OPST_BIST) {
+ /* Do nothing */
+ } else if (return_status == SEED_OPST_WAIT) {
+ /* Do nothing */
+ } else if (return_status == SEED_OPST_DEAD) {
+ /* Do nothing */
+ }
+ return 0;
+}
+
+static RISCVException write_seed(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ return RISCV_EXCP_NONE;
+}
+
/*
* riscv_csrrw - read and/or update control and status register
*
@@ -1823,6 +1890,10 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST;
}
+ if (!write_mask && (csrno == CSR_SEED)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
/* ensure the CSR extension is enabled. */
if (!cpu->cfg.ext_icsr) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -2011,6 +2082,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_TIME] = { "time", ctr, read_time },
[CSR_TIMEH] = { "timeh", ctr32, read_timeh },
+ /* Crypto Extension */
+ [CSR_SEED] = { "seed", seed, read_seed, write_seed},
+
#if !defined(CONFIG_USER_ONLY)
/* Machine Timers and Counters */
[CSR_MCYCLE] = { "mcycle", any, read_instret },
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index a9a0b363a7..83135849bb 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -37,9 +37,11 @@ typedef enum {
} pmp_am_t;
typedef enum {
- MSECCFG_MML = 1 << 0,
- MSECCFG_MMWP = 1 << 1,
- MSECCFG_RLB = 1 << 2
+ MSECCFG_MML = 1 << 0,
+ MSECCFG_MMWP = 1 << 1,
+ MSECCFG_RLB = 1 << 2,
+ MSECCFG_USEED = 1 << 8,
+ MSECCFG_SSEED = 1 << 9
} mseccfg_field_t;
typedef struct {
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 6/7] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-11 3:51 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
disas/riscv.c | 170 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 170 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 03c8dc9961..44a2c16a0b 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -156,6 +156,8 @@ typedef enum {
rv_codec_css_swsp,
rv_codec_css_sdsp,
rv_codec_css_sqsp,
+ rv_codec_k_bs,
+ rv_codec_k_rnum,
} rv_codec;
typedef enum {
@@ -521,6 +523,43 @@ typedef enum {
rv_op_bclr = 359,
rv_op_binv = 360,
rv_op_bext = 361,
+ rv_op_aes32esmi = 362,
+ rv_op_aes32esi = 363,
+ rv_op_aes32dsmi = 364,
+ rv_op_aes32dsi = 365,
+ rv_op_aes64ks1i = 366,
+ rv_op_aes64ks2 = 367,
+ rv_op_aes64im = 368,
+ rv_op_aes64esm = 369,
+ rv_op_aes64es = 370,
+ rv_op_aes64dsm = 371,
+ rv_op_aes64ds = 372,
+ rv_op_sha256sig0 = 373,
+ rv_op_sha256sig1 = 374,
+ rv_op_sha256sum0 = 375,
+ rv_op_sha256sum1 = 376,
+ rv_op_sha512sig0 = 377,
+ rv_op_sha512sig1 = 378,
+ rv_op_sha512sum0 = 379,
+ rv_op_sha512sum1 = 380,
+ rv_op_sha512sum0r = 381,
+ rv_op_sha512sum1r = 382,
+ rv_op_sha512sig0l = 383,
+ rv_op_sha512sig0h = 384,
+ rv_op_sha512sig1l = 385,
+ rv_op_sha512sig1h = 386,
+ rv_op_sm3p0 = 387,
+ rv_op_sm3p1 = 388,
+ rv_op_sm4ed = 389,
+ rv_op_sm4ks = 390,
+ rv_op_brev8 = 391,
+ rv_op_pack = 392,
+ rv_op_packh = 393,
+ rv_op_packw = 394,
+ rv_op_unzip = 395,
+ rv_op_zip = 396,
+ rv_op_xperm4 = 397,
+ rv_op_xperm8 = 398,
} rv_op;
/* structures */
@@ -540,6 +579,8 @@ typedef struct {
uint8_t succ;
uint8_t aq;
uint8_t rl;
+ uint8_t bs;
+ uint8_t rnum;
} rv_decode;
typedef struct {
@@ -615,6 +656,8 @@ static const char rv_freg_name_sym[32][5] = {
#define rv_fmt_rd_rs2 "O\t0,2"
#define rv_fmt_rs1_offset "O\t1,o"
#define rv_fmt_rs2_offset "O\t2,o"
+#define rv_fmt_rs1_rs2_bs "O\t1,2,b"
+#define rv_fmt_rd_rs1_rnum "O\t0,1,n"
/* pseudo-instruction constraints */
@@ -766,6 +809,7 @@ static const rv_comp_data rvcp_csrrw[] = {
{ rv_op_illegal, NULL }
};
+
static const rv_comp_data rvcp_csrrs[] = {
{ rv_op_rdcycle, rvcc_rdcycle },
{ rv_op_rdtime, rvcc_rdtime },
@@ -1203,6 +1247,43 @@ const rv_opcode_data opcode_data[] = {
{ "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
+ { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
};
/* CSR names */
@@ -1216,6 +1297,7 @@ static const char *csr_name(int csrno)
case 0x0003: return "fcsr";
case 0x0004: return "uie";
case 0x0005: return "utvec";
+ case 0x0015: return "seed";
case 0x0040: return "uscratch";
case 0x0041: return "uepc";
case 0x0042: return "ucause";
@@ -1594,7 +1676,36 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 1:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_slli; break;
+ case 0b00001:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0001111: op = rv_op_zip; break;
+ }
+ break;
+ case 0b00010:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0000000: op = rv_op_sha256sum0; break;
+ case 0b0000001: op = rv_op_sha256sum1; break;
+ case 0b0000010: op = rv_op_sha256sig0; break;
+ case 0b0000011: op = rv_op_sha256sig1; break;
+ case 0b0000100: op = rv_op_sha512sum0; break;
+ case 0b0000101: op = rv_op_sha512sum1; break;
+ case 0b0000110: op = rv_op_sha512sig0; break;
+ case 0b0000111: op = rv_op_sha512sig1; break;
+ case 0b0001000: op = rv_op_sm3p0; break;
+ case 0b0001001: op = rv_op_sm3p1; break;
+ }
+ break;
case 0b00101: op = rv_op_bseti; break;
+ case 0b00110:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0000000: op = rv_op_aes64im; break;
+ default:
+ if (((inst >> 24) & 0x111) == 0b001) {
+ op = rv_op_aes64ks1i;
+ }
+ break;
+ }
+ break;
case 0b01001: op = rv_op_bclri; break;
case 0b01101: op = rv_op_binvi; break;
case 0b01100:
@@ -1615,6 +1726,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 5:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_srli; break;
+ case 0b00001:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0001111: op = rv_op_unzip; break;
+ }
+ break;
case 0b00101: op = rv_op_orc_b; break;
case 0b01000: op = rv_op_srai; break;
case 0b01001: op = rv_op_bexti; break;
@@ -1622,6 +1738,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0b01101:
switch ((inst >> 20) & 0b1111111) {
case 0b0111000: op = rv_op_rev8; break;
+ case 0b0000111: op = rv_op_brev8; break;
}
break;
}
@@ -1742,8 +1859,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
+ default: op = rv_op_pack; break;
}
break;
+ case 39: op = rv_op_packh; break;
+
case 41: op = rv_op_clmul; break;
case 42: op = rv_op_clmulr; break;
case 43: op = rv_op_clmulh; break;
@@ -1755,6 +1875,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 132: op = rv_op_sh2add; break;
case 134: op = rv_op_sh3add; break;
case 161: op = rv_op_bset; break;
+ case 162: op = rv_op_xperm4; break;
+ case 164: op = rv_op_xperm8; break;
+ case 200: op = rv_op_aes64es; break;
+ case 216: op = rv_op_aes64esm; break;
+ case 232: op = rv_op_aes64ds; break;
+ case 248: op = rv_op_aes64dsm; break;
case 256: op = rv_op_sub; break;
case 260: op = rv_op_xnor; break;
case 261: op = rv_op_sra; break;
@@ -1762,9 +1888,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 263: op = rv_op_andn; break;
case 289: op = rv_op_bclr; break;
case 293: op = rv_op_bext; break;
+ case 320: op = rv_op_sha512sum0r; break;
+ case 328: op = rv_op_sha512sum1r; break;
+ case 336: op = rv_op_sha512sig0l; break;
+ case 344: op = rv_op_sha512sig1l; break;
+ case 368: op = rv_op_sha512sig0h; break;
+ case 376: op = rv_op_sha512sig1h; break;
case 385: op = rv_op_rol; break;
case 386: op = rv_op_ror; break;
case 417: op = rv_op_binv; break;
+ case 504: op = rv_op_aes64ks2; break;
+ }
+ switch ((inst >> 25) & 0b0011111) {
+ case 17: op = rv_op_aes32esi; break;
+ case 19: op = rv_op_aes32esmi; break;
+ case 21: op = rv_op_aes32dsi; break;
+ case 23: op = rv_op_aes32esmi; break;
+ case 24: op = rv_op_sm4ed; break;
+ case 26: op = rv_op_sm4ks; break;
}
break;
case 13: op = rv_op_lui; break;
@@ -1782,6 +1923,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
+ default: op = rv_op_packw; break;
}
break;
case 130: op = rv_op_sh1add_uw; break;
@@ -2374,6 +2516,16 @@ static uint32_t operand_cimmq(rv_inst inst)
((inst << 57) >> 62) << 6;
}
+static uint32_t operand_bs(rv_inst inst)
+{
+ return (inst << 32) >> 62;
+}
+
+static uint32_t operand_rnum(rv_inst inst)
+{
+ return (inst << 40) >> 60;
+}
+
/* decode operands */
static void decode_inst_operands(rv_decode *dec)
@@ -2653,6 +2805,16 @@ static void decode_inst_operands(rv_decode *dec)
dec->rs2 = operand_crs2(inst);
dec->imm = operand_cimmsqsp(inst);
break;
+ case rv_codec_k_bs:
+ dec->rs1 = operand_rs1(inst);
+ dec->rs2 = operand_rs2(inst);
+ dec->bs = operand_bs(inst);
+ break;
+ case rv_codec_k_rnum:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->rnum = operand_rnum(inst);
+ break;
};
}
@@ -2812,6 +2974,14 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
case ')':
append(buf, ")", buflen);
break;
+ case 'b':
+ snprintf(tmp, sizeof(tmp), "%d", dec->bs);
+ append(buf, tmp, buflen);
+ break;
+ case 'n':
+ snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
+ append(buf, tmp, buflen);
+ break;
case '0':
append(buf, rv_ireg_name_sym[dec->rd], buflen);
break;
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 6/7] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
@ 2022-01-11 3:51 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
disas/riscv.c | 170 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 170 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 03c8dc9961..44a2c16a0b 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -156,6 +156,8 @@ typedef enum {
rv_codec_css_swsp,
rv_codec_css_sdsp,
rv_codec_css_sqsp,
+ rv_codec_k_bs,
+ rv_codec_k_rnum,
} rv_codec;
typedef enum {
@@ -521,6 +523,43 @@ typedef enum {
rv_op_bclr = 359,
rv_op_binv = 360,
rv_op_bext = 361,
+ rv_op_aes32esmi = 362,
+ rv_op_aes32esi = 363,
+ rv_op_aes32dsmi = 364,
+ rv_op_aes32dsi = 365,
+ rv_op_aes64ks1i = 366,
+ rv_op_aes64ks2 = 367,
+ rv_op_aes64im = 368,
+ rv_op_aes64esm = 369,
+ rv_op_aes64es = 370,
+ rv_op_aes64dsm = 371,
+ rv_op_aes64ds = 372,
+ rv_op_sha256sig0 = 373,
+ rv_op_sha256sig1 = 374,
+ rv_op_sha256sum0 = 375,
+ rv_op_sha256sum1 = 376,
+ rv_op_sha512sig0 = 377,
+ rv_op_sha512sig1 = 378,
+ rv_op_sha512sum0 = 379,
+ rv_op_sha512sum1 = 380,
+ rv_op_sha512sum0r = 381,
+ rv_op_sha512sum1r = 382,
+ rv_op_sha512sig0l = 383,
+ rv_op_sha512sig0h = 384,
+ rv_op_sha512sig1l = 385,
+ rv_op_sha512sig1h = 386,
+ rv_op_sm3p0 = 387,
+ rv_op_sm3p1 = 388,
+ rv_op_sm4ed = 389,
+ rv_op_sm4ks = 390,
+ rv_op_brev8 = 391,
+ rv_op_pack = 392,
+ rv_op_packh = 393,
+ rv_op_packw = 394,
+ rv_op_unzip = 395,
+ rv_op_zip = 396,
+ rv_op_xperm4 = 397,
+ rv_op_xperm8 = 398,
} rv_op;
/* structures */
@@ -540,6 +579,8 @@ typedef struct {
uint8_t succ;
uint8_t aq;
uint8_t rl;
+ uint8_t bs;
+ uint8_t rnum;
} rv_decode;
typedef struct {
@@ -615,6 +656,8 @@ static const char rv_freg_name_sym[32][5] = {
#define rv_fmt_rd_rs2 "O\t0,2"
#define rv_fmt_rs1_offset "O\t1,o"
#define rv_fmt_rs2_offset "O\t2,o"
+#define rv_fmt_rs1_rs2_bs "O\t1,2,b"
+#define rv_fmt_rd_rs1_rnum "O\t0,1,n"
/* pseudo-instruction constraints */
@@ -766,6 +809,7 @@ static const rv_comp_data rvcp_csrrw[] = {
{ rv_op_illegal, NULL }
};
+
static const rv_comp_data rvcp_csrrs[] = {
{ rv_op_rdcycle, rvcc_rdcycle },
{ rv_op_rdtime, rvcc_rdtime },
@@ -1203,6 +1247,43 @@ const rv_opcode_data opcode_data[] = {
{ "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
+ { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
};
/* CSR names */
@@ -1216,6 +1297,7 @@ static const char *csr_name(int csrno)
case 0x0003: return "fcsr";
case 0x0004: return "uie";
case 0x0005: return "utvec";
+ case 0x0015: return "seed";
case 0x0040: return "uscratch";
case 0x0041: return "uepc";
case 0x0042: return "ucause";
@@ -1594,7 +1676,36 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 1:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_slli; break;
+ case 0b00001:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0001111: op = rv_op_zip; break;
+ }
+ break;
+ case 0b00010:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0000000: op = rv_op_sha256sum0; break;
+ case 0b0000001: op = rv_op_sha256sum1; break;
+ case 0b0000010: op = rv_op_sha256sig0; break;
+ case 0b0000011: op = rv_op_sha256sig1; break;
+ case 0b0000100: op = rv_op_sha512sum0; break;
+ case 0b0000101: op = rv_op_sha512sum1; break;
+ case 0b0000110: op = rv_op_sha512sig0; break;
+ case 0b0000111: op = rv_op_sha512sig1; break;
+ case 0b0001000: op = rv_op_sm3p0; break;
+ case 0b0001001: op = rv_op_sm3p1; break;
+ }
+ break;
case 0b00101: op = rv_op_bseti; break;
+ case 0b00110:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0000000: op = rv_op_aes64im; break;
+ default:
+ if (((inst >> 24) & 0x111) == 0b001) {
+ op = rv_op_aes64ks1i;
+ }
+ break;
+ }
+ break;
case 0b01001: op = rv_op_bclri; break;
case 0b01101: op = rv_op_binvi; break;
case 0b01100:
@@ -1615,6 +1726,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 5:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_srli; break;
+ case 0b00001:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0001111: op = rv_op_unzip; break;
+ }
+ break;
case 0b00101: op = rv_op_orc_b; break;
case 0b01000: op = rv_op_srai; break;
case 0b01001: op = rv_op_bexti; break;
@@ -1622,6 +1738,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0b01101:
switch ((inst >> 20) & 0b1111111) {
case 0b0111000: op = rv_op_rev8; break;
+ case 0b0000111: op = rv_op_brev8; break;
}
break;
}
@@ -1742,8 +1859,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
+ default: op = rv_op_pack; break;
}
break;
+ case 39: op = rv_op_packh; break;
+
case 41: op = rv_op_clmul; break;
case 42: op = rv_op_clmulr; break;
case 43: op = rv_op_clmulh; break;
@@ -1755,6 +1875,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 132: op = rv_op_sh2add; break;
case 134: op = rv_op_sh3add; break;
case 161: op = rv_op_bset; break;
+ case 162: op = rv_op_xperm4; break;
+ case 164: op = rv_op_xperm8; break;
+ case 200: op = rv_op_aes64es; break;
+ case 216: op = rv_op_aes64esm; break;
+ case 232: op = rv_op_aes64ds; break;
+ case 248: op = rv_op_aes64dsm; break;
case 256: op = rv_op_sub; break;
case 260: op = rv_op_xnor; break;
case 261: op = rv_op_sra; break;
@@ -1762,9 +1888,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 263: op = rv_op_andn; break;
case 289: op = rv_op_bclr; break;
case 293: op = rv_op_bext; break;
+ case 320: op = rv_op_sha512sum0r; break;
+ case 328: op = rv_op_sha512sum1r; break;
+ case 336: op = rv_op_sha512sig0l; break;
+ case 344: op = rv_op_sha512sig1l; break;
+ case 368: op = rv_op_sha512sig0h; break;
+ case 376: op = rv_op_sha512sig1h; break;
case 385: op = rv_op_rol; break;
case 386: op = rv_op_ror; break;
case 417: op = rv_op_binv; break;
+ case 504: op = rv_op_aes64ks2; break;
+ }
+ switch ((inst >> 25) & 0b0011111) {
+ case 17: op = rv_op_aes32esi; break;
+ case 19: op = rv_op_aes32esmi; break;
+ case 21: op = rv_op_aes32dsi; break;
+ case 23: op = rv_op_aes32esmi; break;
+ case 24: op = rv_op_sm4ed; break;
+ case 26: op = rv_op_sm4ks; break;
}
break;
case 13: op = rv_op_lui; break;
@@ -1782,6 +1923,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
+ default: op = rv_op_packw; break;
}
break;
case 130: op = rv_op_sh1add_uw; break;
@@ -2374,6 +2516,16 @@ static uint32_t operand_cimmq(rv_inst inst)
((inst << 57) >> 62) << 6;
}
+static uint32_t operand_bs(rv_inst inst)
+{
+ return (inst << 32) >> 62;
+}
+
+static uint32_t operand_rnum(rv_inst inst)
+{
+ return (inst << 40) >> 60;
+}
+
/* decode operands */
static void decode_inst_operands(rv_decode *dec)
@@ -2653,6 +2805,16 @@ static void decode_inst_operands(rv_decode *dec)
dec->rs2 = operand_crs2(inst);
dec->imm = operand_cimmsqsp(inst);
break;
+ case rv_codec_k_bs:
+ dec->rs1 = operand_rs1(inst);
+ dec->rs2 = operand_rs2(inst);
+ dec->bs = operand_bs(inst);
+ break;
+ case rv_codec_k_rnum:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->rnum = operand_rnum(inst);
+ break;
};
}
@@ -2812,6 +2974,14 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
case ')':
append(buf, ")", buflen);
break;
+ case 'b':
+ snprintf(tmp, sizeof(tmp), "%d", dec->bs);
+ append(buf, tmp, buflen);
+ break;
+ case 'n':
+ snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
+ append(buf, tmp, buflen);
+ break;
case '0':
append(buf, rv_ireg_name_sym[dec->rd], buflen);
break;
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-11 3:51 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b487a8282c..628a782ba9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -694,9 +694,23 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+ DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
+ DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
+ DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
+ DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
+ DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
+ DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
+ DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
+ DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
+ DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
+ DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
+ DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
+ DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
/* These are experimental so mark with 'x-' */
+ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
@ 2022-01-11 3:51 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-11 3:51 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b487a8282c..628a782ba9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -694,9 +694,23 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+ DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
+ DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
+ DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
+ DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
+ DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
+ DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
+ DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
+ DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
+ DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
+ DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
+ DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
+ DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
/* These are experimental so mark with 'x-' */
+ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
--
2.17.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-17 23:28 ` Alistair Francis
-1 siblings, 0 replies; 40+ messages in thread
From: Alistair Francis @ 2022-01-17 23:28 UTC (permalink / raw)
To: Weiwei Li
Cc: lazyparser, open list:RISC-V, lustrew, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, luruibo2000, Alistair Francis
On Tue, Jan 11, 2022 at 1:57 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - share it between target/arm and target/riscv
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Do you mind fixing up the commit title?
Maybe something more like:
crypto: move sm4_sbox from target/arm
Otherwise:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
Alistair
> ---
> crypto/meson.build | 1 +
> crypto/sm4.c | 49 ++++++++++++++++++++++++++++++++++++++
> include/crypto/sm4.h | 6 +++++
> target/arm/crypto_helper.c | 36 +---------------------------
> 4 files changed, 57 insertions(+), 35 deletions(-)
> create mode 100644 crypto/sm4.c
> create mode 100644 include/crypto/sm4.h
>
> diff --git a/crypto/meson.build b/crypto/meson.build
> index 95a6a83504..f659fc9035 100644
> --- a/crypto/meson.build
> +++ b/crypto/meson.build
> @@ -38,6 +38,7 @@ crypto_ss.add(when: 'CONFIG_SECRET_KEYRING', if_true: files('secret_keyring.c'))
> crypto_ss.add(when: 'CONFIG_AF_ALG', if_true: files('afalg.c', 'cipher-afalg.c', 'hash-afalg.c'))
> crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
>
> +util_ss.add(files('sm4.c'))
> util_ss.add(files('aes.c'))
> util_ss.add(files('init.c'))
> if gnutls.found()
> diff --git a/crypto/sm4.c b/crypto/sm4.c
> new file mode 100644
> index 0000000000..9f0cd452c7
> --- /dev/null
> +++ b/crypto/sm4.c
> @@ -0,0 +1,49 @@
> +/*
> + * QEMU crypto sm4 support
> + *
> + * Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "crypto/sm4.h"
> +
> +uint8_t const sm4_sbox[] = {
> + 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
> + 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
> + 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
> + 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
> + 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
> + 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
> + 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
> + 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
> + 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
> + 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
> + 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
> + 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
> + 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
> + 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
> + 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
> + 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
> + 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
> + 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
> + 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
> + 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
> + 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
> + 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
> + 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
> + 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
> + 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
> + 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
> + 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
> + 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
> + 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
> + 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
> + 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
> + 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
> +};
> +
> diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
> new file mode 100644
> index 0000000000..9bd3ebc62e
> --- /dev/null
> +++ b/include/crypto/sm4.h
> @@ -0,0 +1,6 @@
> +#ifndef QEMU_SM4_H
> +#define QEMU_SM4_H
> +
> +extern const uint8_t sm4_sbox[256];
> +
> +#endif
> diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
> index 28a84c2dbd..390020672a 100644
> --- a/target/arm/crypto_helper.c
> +++ b/target/arm/crypto_helper.c
> @@ -15,6 +15,7 @@
> #include "exec/helper-proto.h"
> #include "tcg/tcg-gvec-desc.h"
> #include "crypto/aes.h"
> +#include "crypto/sm4.h"
> #include "vec_internal.h"
>
> union CRYPTO_STATE {
> @@ -694,41 +695,6 @@ DO_SM3TT(crypto_sm3tt2b, 3)
>
> #undef DO_SM3TT
>
> -static uint8_t const sm4_sbox[] = {
> - 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
> - 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
> - 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
> - 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
> - 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
> - 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
> - 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
> - 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
> - 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
> - 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
> - 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
> - 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
> - 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
> - 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
> - 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
> - 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
> - 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
> - 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
> - 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
> - 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
> - 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
> - 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
> - 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
> - 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
> - 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
> - 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
> - 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
> - 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
> - 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
> - 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
> - 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
> - 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
> -};
> -
> static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
> {
> union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
@ 2022-01-17 23:28 ` Alistair Francis
0 siblings, 0 replies; 40+ messages in thread
From: Alistair Francis @ 2022-01-17 23:28 UTC (permalink / raw)
To: Weiwei Li
Cc: Richard Henderson, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
lazyparser, luruibo2000, lustrew
On Tue, Jan 11, 2022 at 1:57 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - share it between target/arm and target/riscv
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Do you mind fixing up the commit title?
Maybe something more like:
crypto: move sm4_sbox from target/arm
Otherwise:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
Alistair
> ---
> crypto/meson.build | 1 +
> crypto/sm4.c | 49 ++++++++++++++++++++++++++++++++++++++
> include/crypto/sm4.h | 6 +++++
> target/arm/crypto_helper.c | 36 +---------------------------
> 4 files changed, 57 insertions(+), 35 deletions(-)
> create mode 100644 crypto/sm4.c
> create mode 100644 include/crypto/sm4.h
>
> diff --git a/crypto/meson.build b/crypto/meson.build
> index 95a6a83504..f659fc9035 100644
> --- a/crypto/meson.build
> +++ b/crypto/meson.build
> @@ -38,6 +38,7 @@ crypto_ss.add(when: 'CONFIG_SECRET_KEYRING', if_true: files('secret_keyring.c'))
> crypto_ss.add(when: 'CONFIG_AF_ALG', if_true: files('afalg.c', 'cipher-afalg.c', 'hash-afalg.c'))
> crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
>
> +util_ss.add(files('sm4.c'))
> util_ss.add(files('aes.c'))
> util_ss.add(files('init.c'))
> if gnutls.found()
> diff --git a/crypto/sm4.c b/crypto/sm4.c
> new file mode 100644
> index 0000000000..9f0cd452c7
> --- /dev/null
> +++ b/crypto/sm4.c
> @@ -0,0 +1,49 @@
> +/*
> + * QEMU crypto sm4 support
> + *
> + * Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "crypto/sm4.h"
> +
> +uint8_t const sm4_sbox[] = {
> + 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
> + 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
> + 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
> + 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
> + 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
> + 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
> + 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
> + 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
> + 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
> + 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
> + 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
> + 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
> + 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
> + 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
> + 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
> + 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
> + 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
> + 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
> + 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
> + 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
> + 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
> + 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
> + 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
> + 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
> + 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
> + 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
> + 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
> + 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
> + 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
> + 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
> + 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
> + 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
> +};
> +
> diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
> new file mode 100644
> index 0000000000..9bd3ebc62e
> --- /dev/null
> +++ b/include/crypto/sm4.h
> @@ -0,0 +1,6 @@
> +#ifndef QEMU_SM4_H
> +#define QEMU_SM4_H
> +
> +extern const uint8_t sm4_sbox[256];
> +
> +#endif
> diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
> index 28a84c2dbd..390020672a 100644
> --- a/target/arm/crypto_helper.c
> +++ b/target/arm/crypto_helper.c
> @@ -15,6 +15,7 @@
> #include "exec/helper-proto.h"
> #include "tcg/tcg-gvec-desc.h"
> #include "crypto/aes.h"
> +#include "crypto/sm4.h"
> #include "vec_internal.h"
>
> union CRYPTO_STATE {
> @@ -694,41 +695,6 @@ DO_SM3TT(crypto_sm3tt2b, 3)
>
> #undef DO_SM3TT
>
> -static uint8_t const sm4_sbox[] = {
> - 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
> - 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
> - 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
> - 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
> - 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
> - 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
> - 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
> - 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
> - 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
> - 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
> - 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
> - 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
> - 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
> - 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
> - 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
> - 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
> - 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
> - 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
> - 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
> - 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
> - 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
> - 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
> - 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
> - 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
> - 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
> - 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
> - 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
> - 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
> - 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
> - 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
> - 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
> - 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
> -};
> -
> static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
> {
> union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
2022-01-17 23:28 ` Alistair Francis
@ 2022-01-18 1:09 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-18 1:09 UTC (permalink / raw)
To: Alistair Francis
Cc: lazyparser, open list:RISC-V, lustrew, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, luruibo2000, Alistair Francis
在 2022/1/18 上午7:28, Alistair Francis 写道:
> On Tue, Jan 11, 2022 at 1:57 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> - share it between target/arm and target/riscv
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Do you mind fixing up the commit title?
>
> Maybe something more like:
>
> crypto: move sm4_sbox from target/arm
>
> Otherwise:
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>
> Alistair
>
> Alistair
OK. I'll change this. Thanks for your comment.
Regards,
Weiwei Li
>> ---
>> crypto/meson.build | 1 +
>> crypto/sm4.c | 49 ++++++++++++++++++++++++++++++++++++++
>> include/crypto/sm4.h | 6 +++++
>> target/arm/crypto_helper.c | 36 +---------------------------
>> 4 files changed, 57 insertions(+), 35 deletions(-)
>> create mode 100644 crypto/sm4.c
>> create mode 100644 include/crypto/sm4.h
>>
>> diff --git a/crypto/meson.build b/crypto/meson.build
>> index 95a6a83504..f659fc9035 100644
>> --- a/crypto/meson.build
>> +++ b/crypto/meson.build
>> @@ -38,6 +38,7 @@ crypto_ss.add(when: 'CONFIG_SECRET_KEYRING', if_true: files('secret_keyring.c'))
>> crypto_ss.add(when: 'CONFIG_AF_ALG', if_true: files('afalg.c', 'cipher-afalg.c', 'hash-afalg.c'))
>> crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
>>
>> +util_ss.add(files('sm4.c'))
>> util_ss.add(files('aes.c'))
>> util_ss.add(files('init.c'))
>> if gnutls.found()
>> diff --git a/crypto/sm4.c b/crypto/sm4.c
>> new file mode 100644
>> index 0000000000..9f0cd452c7
>> --- /dev/null
>> +++ b/crypto/sm4.c
>> @@ -0,0 +1,49 @@
>> +/*
>> + * QEMU crypto sm4 support
>> + *
>> + * Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
>> + *
>> + * This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU Lesser General Public
>> + * License as published by the Free Software Foundation; either
>> + * version 2.1 of the License, or (at your option) any later version.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "crypto/sm4.h"
>> +
>> +uint8_t const sm4_sbox[] = {
>> + 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
>> + 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
>> + 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
>> + 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
>> + 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
>> + 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
>> + 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
>> + 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
>> + 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
>> + 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
>> + 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
>> + 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
>> + 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
>> + 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
>> + 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
>> + 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
>> + 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
>> + 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
>> + 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
>> + 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
>> + 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
>> + 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
>> + 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
>> + 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
>> + 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
>> + 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
>> + 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
>> + 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
>> + 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
>> + 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
>> + 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
>> + 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
>> +};
>> +
>> diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
>> new file mode 100644
>> index 0000000000..9bd3ebc62e
>> --- /dev/null
>> +++ b/include/crypto/sm4.h
>> @@ -0,0 +1,6 @@
>> +#ifndef QEMU_SM4_H
>> +#define QEMU_SM4_H
>> +
>> +extern const uint8_t sm4_sbox[256];
>> +
>> +#endif
>> diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
>> index 28a84c2dbd..390020672a 100644
>> --- a/target/arm/crypto_helper.c
>> +++ b/target/arm/crypto_helper.c
>> @@ -15,6 +15,7 @@
>> #include "exec/helper-proto.h"
>> #include "tcg/tcg-gvec-desc.h"
>> #include "crypto/aes.h"
>> +#include "crypto/sm4.h"
>> #include "vec_internal.h"
>>
>> union CRYPTO_STATE {
>> @@ -694,41 +695,6 @@ DO_SM3TT(crypto_sm3tt2b, 3)
>>
>> #undef DO_SM3TT
>>
>> -static uint8_t const sm4_sbox[] = {
>> - 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
>> - 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
>> - 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
>> - 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
>> - 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
>> - 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
>> - 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
>> - 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
>> - 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
>> - 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
>> - 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
>> - 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
>> - 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
>> - 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
>> - 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
>> - 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
>> - 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
>> - 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
>> - 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
>> - 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
>> - 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
>> - 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
>> - 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
>> - 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
>> - 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
>> - 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
>> - 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
>> - 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
>> - 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
>> - 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
>> - 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
>> - 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
>> -};
>> -
>> static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
>> {
>> union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
@ 2022-01-18 1:09 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-18 1:09 UTC (permalink / raw)
To: Alistair Francis
Cc: Richard Henderson, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
lazyparser, luruibo2000, lustrew
在 2022/1/18 上午7:28, Alistair Francis 写道:
> On Tue, Jan 11, 2022 at 1:57 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> - share it between target/arm and target/riscv
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Do you mind fixing up the commit title?
>
> Maybe something more like:
>
> crypto: move sm4_sbox from target/arm
>
> Otherwise:
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>
> Alistair
>
> Alistair
OK. I'll change this. Thanks for your comment.
Regards,
Weiwei Li
>> ---
>> crypto/meson.build | 1 +
>> crypto/sm4.c | 49 ++++++++++++++++++++++++++++++++++++++
>> include/crypto/sm4.h | 6 +++++
>> target/arm/crypto_helper.c | 36 +---------------------------
>> 4 files changed, 57 insertions(+), 35 deletions(-)
>> create mode 100644 crypto/sm4.c
>> create mode 100644 include/crypto/sm4.h
>>
>> diff --git a/crypto/meson.build b/crypto/meson.build
>> index 95a6a83504..f659fc9035 100644
>> --- a/crypto/meson.build
>> +++ b/crypto/meson.build
>> @@ -38,6 +38,7 @@ crypto_ss.add(when: 'CONFIG_SECRET_KEYRING', if_true: files('secret_keyring.c'))
>> crypto_ss.add(when: 'CONFIG_AF_ALG', if_true: files('afalg.c', 'cipher-afalg.c', 'hash-afalg.c'))
>> crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
>>
>> +util_ss.add(files('sm4.c'))
>> util_ss.add(files('aes.c'))
>> util_ss.add(files('init.c'))
>> if gnutls.found()
>> diff --git a/crypto/sm4.c b/crypto/sm4.c
>> new file mode 100644
>> index 0000000000..9f0cd452c7
>> --- /dev/null
>> +++ b/crypto/sm4.c
>> @@ -0,0 +1,49 @@
>> +/*
>> + * QEMU crypto sm4 support
>> + *
>> + * Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
>> + *
>> + * This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU Lesser General Public
>> + * License as published by the Free Software Foundation; either
>> + * version 2.1 of the License, or (at your option) any later version.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "crypto/sm4.h"
>> +
>> +uint8_t const sm4_sbox[] = {
>> + 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
>> + 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
>> + 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
>> + 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
>> + 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
>> + 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
>> + 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
>> + 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
>> + 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
>> + 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
>> + 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
>> + 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
>> + 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
>> + 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
>> + 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
>> + 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
>> + 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
>> + 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
>> + 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
>> + 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
>> + 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
>> + 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
>> + 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
>> + 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
>> + 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
>> + 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
>> + 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
>> + 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
>> + 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
>> + 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
>> + 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
>> + 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
>> +};
>> +
>> diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
>> new file mode 100644
>> index 0000000000..9bd3ebc62e
>> --- /dev/null
>> +++ b/include/crypto/sm4.h
>> @@ -0,0 +1,6 @@
>> +#ifndef QEMU_SM4_H
>> +#define QEMU_SM4_H
>> +
>> +extern const uint8_t sm4_sbox[256];
>> +
>> +#endif
>> diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
>> index 28a84c2dbd..390020672a 100644
>> --- a/target/arm/crypto_helper.c
>> +++ b/target/arm/crypto_helper.c
>> @@ -15,6 +15,7 @@
>> #include "exec/helper-proto.h"
>> #include "tcg/tcg-gvec-desc.h"
>> #include "crypto/aes.h"
>> +#include "crypto/sm4.h"
>> #include "vec_internal.h"
>>
>> union CRYPTO_STATE {
>> @@ -694,41 +695,6 @@ DO_SM3TT(crypto_sm3tt2b, 3)
>>
>> #undef DO_SM3TT
>>
>> -static uint8_t const sm4_sbox[] = {
>> - 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
>> - 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
>> - 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
>> - 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
>> - 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
>> - 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
>> - 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
>> - 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
>> - 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
>> - 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
>> - 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
>> - 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
>> - 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
>> - 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
>> - 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
>> - 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
>> - 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
>> - 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
>> - 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
>> - 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
>> - 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
>> - 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
>> - 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
>> - 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
>> - 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
>> - 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
>> - 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
>> - 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
>> - 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
>> - 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
>> - 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
>> - 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
>> -};
>> -
>> static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
>> {
>> union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-18 4:21 ` Alistair Francis
-1 siblings, 0 replies; 40+ messages in thread
From: Alistair Francis @ 2022-01-18 4:21 UTC (permalink / raw)
To: Weiwei Li
Cc: lazyparser, open list:RISC-V, lustrew, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, luruibo2000, Alistair Francis
On Tue, Jan 11, 2022 at 2:01 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Co-authored-by: Ruibo Lu <luruibo2000@163.com>
> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/crypto_helper.c | 446 ++++++++++++++++++++++
> target/riscv/helper.h | 37 ++
> target/riscv/insn32.decode | 42 +++
> target/riscv/insn_trans/trans_rvk.c.inc | 467 ++++++++++++++++++++++++
> target/riscv/meson.build | 3 +-
> target/riscv/translate.c | 1 +
> 6 files changed, 995 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/crypto_helper.c
> create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>
> diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
> new file mode 100644
> index 0000000000..344eea4287
> --- /dev/null
> +++ b/target/riscv/crypto_helper.c
> @@ -0,0 +1,446 @@
> +/*
> + * RISC-V Crypto Emulation Helpers for QEMU.
> + *
> + * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
> + * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +#include "exec/exec-all.h"
> +#include "exec/helper-proto.h"
> +#include "crypto/aes.h"
> +#include "crypto/sm4.h"
> +
> +#define AES_XTIME(a) \
> + ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
> +
> +#define AES_GFMUL(a, b) (( \
> + (((b) & 0x1) ? (a) : 0) ^ \
> + (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
> + (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
> + (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
> +
> +#define BY(X, I) ((X >> (8 * I)) & 0xFF)
> +
> +#define AES_SHIFROWS_LO(RS1, RS2) ( \
> + (((RS1 >> 24) & 0xFF) << 56) | \
> + (((RS2 >> 48) & 0xFF) << 48) | \
> + (((RS2 >> 8) & 0xFF) << 40) | \
> + (((RS1 >> 32) & 0xFF) << 32) | \
> + (((RS2 >> 56) & 0xFF) << 24) | \
> + (((RS2 >> 16) & 0xFF) << 16) | \
> + (((RS1 >> 40) & 0xFF) << 8) | \
> + (((RS1 >> 0) & 0xFF) << 0))
> +
> +#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
> + (((RS2 >> 24) & 0xFF) << 56) | \
> + (((RS2 >> 48) & 0xFF) << 48) | \
> + (((RS1 >> 8) & 0xFF) << 40) | \
> + (((RS1 >> 32) & 0xFF) << 32) | \
> + (((RS1 >> 56) & 0xFF) << 24) | \
> + (((RS2 >> 16) & 0xFF) << 16) | \
> + (((RS2 >> 40) & 0xFF) << 8) | \
> + (((RS1 >> 0) & 0xFF) << 0))
> +
> +#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
> + BY(COL, B3) ^ \
> + BY(COL, B2) ^ \
> + AES_GFMUL(BY(COL, B1), 3) ^ \
> + AES_GFMUL(BY(COL, B0), 2) \
> +)
> +
> +#define AES_MIXCOLUMN(COL) ( \
> + AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
> + AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
> + AES_MIXBYTE(COL, 1, 2, 3, 0) << 8 | \
> + AES_MIXBYTE(COL, 0, 1, 2, 3) << 0 \
> +)
> +
> +#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
> + AES_GFMUL(BY(COL, B3), 0x9) ^ \
> + AES_GFMUL(BY(COL, B2), 0xd) ^ \
> + AES_GFMUL(BY(COL, B1), 0xb) ^ \
> + AES_GFMUL(BY(COL, B0), 0xe) \
> +)
> +
> +#define AES_INVMIXCOLUMN(COL) ( \
> + AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
> + AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
> + AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
> + AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0 \
> +)
> +
> +static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
> +{
> + uint32_t u;
> + if (fwd) {
> + u = (AES_GFMUL(x, 3) << 24) |
> + (x << 16) |
> + (x << 8) |
> + (AES_GFMUL(x, 2) << 0);
> + } else {
> + u = (AES_GFMUL(x, 0xb) << 24) |
> + (AES_GFMUL(x, 0xd) << 16) |
> + (AES_GFMUL(x, 0x9) << 8) |
> + (AES_GFMUL(x, 0xe) << 0);
> + }
> + return u;
> +}
> +
> +#define XLEN (8 * sizeof(target_ulong))
I don't think this is used, but please don't hard coded xlen's.
Everything should be dynamic based on the CPU xlen.
It would also be great if you could split this patch up more. There is
a lot being added here.
Alistair
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
@ 2022-01-18 4:21 ` Alistair Francis
0 siblings, 0 replies; 40+ messages in thread
From: Alistair Francis @ 2022-01-18 4:21 UTC (permalink / raw)
To: Weiwei Li
Cc: Richard Henderson, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
lazyparser, luruibo2000, lustrew
On Tue, Jan 11, 2022 at 2:01 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Co-authored-by: Ruibo Lu <luruibo2000@163.com>
> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/crypto_helper.c | 446 ++++++++++++++++++++++
> target/riscv/helper.h | 37 ++
> target/riscv/insn32.decode | 42 +++
> target/riscv/insn_trans/trans_rvk.c.inc | 467 ++++++++++++++++++++++++
> target/riscv/meson.build | 3 +-
> target/riscv/translate.c | 1 +
> 6 files changed, 995 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/crypto_helper.c
> create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>
> diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
> new file mode 100644
> index 0000000000..344eea4287
> --- /dev/null
> +++ b/target/riscv/crypto_helper.c
> @@ -0,0 +1,446 @@
> +/*
> + * RISC-V Crypto Emulation Helpers for QEMU.
> + *
> + * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
> + * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +#include "exec/exec-all.h"
> +#include "exec/helper-proto.h"
> +#include "crypto/aes.h"
> +#include "crypto/sm4.h"
> +
> +#define AES_XTIME(a) \
> + ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
> +
> +#define AES_GFMUL(a, b) (( \
> + (((b) & 0x1) ? (a) : 0) ^ \
> + (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
> + (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
> + (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
> +
> +#define BY(X, I) ((X >> (8 * I)) & 0xFF)
> +
> +#define AES_SHIFROWS_LO(RS1, RS2) ( \
> + (((RS1 >> 24) & 0xFF) << 56) | \
> + (((RS2 >> 48) & 0xFF) << 48) | \
> + (((RS2 >> 8) & 0xFF) << 40) | \
> + (((RS1 >> 32) & 0xFF) << 32) | \
> + (((RS2 >> 56) & 0xFF) << 24) | \
> + (((RS2 >> 16) & 0xFF) << 16) | \
> + (((RS1 >> 40) & 0xFF) << 8) | \
> + (((RS1 >> 0) & 0xFF) << 0))
> +
> +#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
> + (((RS2 >> 24) & 0xFF) << 56) | \
> + (((RS2 >> 48) & 0xFF) << 48) | \
> + (((RS1 >> 8) & 0xFF) << 40) | \
> + (((RS1 >> 32) & 0xFF) << 32) | \
> + (((RS1 >> 56) & 0xFF) << 24) | \
> + (((RS2 >> 16) & 0xFF) << 16) | \
> + (((RS2 >> 40) & 0xFF) << 8) | \
> + (((RS1 >> 0) & 0xFF) << 0))
> +
> +#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
> + BY(COL, B3) ^ \
> + BY(COL, B2) ^ \
> + AES_GFMUL(BY(COL, B1), 3) ^ \
> + AES_GFMUL(BY(COL, B0), 2) \
> +)
> +
> +#define AES_MIXCOLUMN(COL) ( \
> + AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
> + AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
> + AES_MIXBYTE(COL, 1, 2, 3, 0) << 8 | \
> + AES_MIXBYTE(COL, 0, 1, 2, 3) << 0 \
> +)
> +
> +#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
> + AES_GFMUL(BY(COL, B3), 0x9) ^ \
> + AES_GFMUL(BY(COL, B2), 0xd) ^ \
> + AES_GFMUL(BY(COL, B1), 0xb) ^ \
> + AES_GFMUL(BY(COL, B0), 0xe) \
> +)
> +
> +#define AES_INVMIXCOLUMN(COL) ( \
> + AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
> + AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
> + AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
> + AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0 \
> +)
> +
> +static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
> +{
> + uint32_t u;
> + if (fwd) {
> + u = (AES_GFMUL(x, 3) << 24) |
> + (x << 16) |
> + (x << 8) |
> + (AES_GFMUL(x, 2) << 0);
> + } else {
> + u = (AES_GFMUL(x, 0xb) << 24) |
> + (AES_GFMUL(x, 0xd) << 16) |
> + (AES_GFMUL(x, 0x9) << 8) |
> + (AES_GFMUL(x, 0xe) << 0);
> + }
> + return u;
> +}
> +
> +#define XLEN (8 * sizeof(target_ulong))
I don't think this is used, but please don't hard coded xlen's.
Everything should be dynamic based on the CPU xlen.
It would also be great if you could split this patch up more. There is
a lot being added here.
Alistair
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-18 4:23 ` Alistair Francis
-1 siblings, 0 replies; 40+ messages in thread
From: Alistair Francis @ 2022-01-18 4:23 UTC (permalink / raw)
To: Weiwei Li
Cc: lazyparser, open list:RISC-V, lustrew, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, luruibo2000, Alistair Francis
On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/cpu.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b487a8282c..628a782ba9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -694,9 +694,23 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> + DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
> + DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
> + DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> + DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
> + DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
> + DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
> + DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
> + DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
> + DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
> + DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
> + DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
> + DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
> + DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
>
> /* These are experimental so mark with 'x-' */
> + DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
Looks like a rebase error
Alistair
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
@ 2022-01-18 4:23 ` Alistair Francis
0 siblings, 0 replies; 40+ messages in thread
From: Alistair Francis @ 2022-01-18 4:23 UTC (permalink / raw)
To: Weiwei Li
Cc: Richard Henderson, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
lazyparser, luruibo2000, lustrew
On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/cpu.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b487a8282c..628a782ba9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -694,9 +694,23 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> + DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
> + DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
> + DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> + DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
> + DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
> + DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
> + DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
> + DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
> + DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
> + DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
> + DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
> + DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
> + DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
>
> /* These are experimental so mark with 'x-' */
> + DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
Looks like a rebase error
Alistair
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-18 4:36 ` Alistair Francis
-1 siblings, 0 replies; 40+ messages in thread
From: Alistair Francis @ 2022-01-18 4:36 UTC (permalink / raw)
To: Weiwei Li
Cc: lazyparser, open list:RISC-V, lustrew, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, luruibo2000, Alistair Francis
On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - add SEED CSR
> - add USEED, SSEED fields for MSECCFG CSR
>
> Co-authored-by: Ruibo Lu <luruibo2000@163.com>
> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/cpu_bits.h | 9 +++++
> target/riscv/csr.c | 74 +++++++++++++++++++++++++++++++++++++++++
> target/riscv/pmp.h | 8 +++--
> 3 files changed, 88 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 5a6d49aa64..65c708622b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -374,6 +374,9 @@
> #define CSR_VSPMMASK 0x2c1
> #define CSR_VSPMBASE 0x2c2
>
> +/* Crypto Extension */
> +#define CSR_SEED 0x015
> +
> /* mstatus CSR bits */
> #define MSTATUS_UIE 0x00000001
> #define MSTATUS_SIE 0x00000002
> @@ -628,4 +631,10 @@ typedef enum RISCVException {
> #define UMTE_U_PM_INSN U_PM_INSN
> #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
>
> +/* seed CSR bits */
> +#define SEED_OPST (0b11 << 30)
> +#define SEED_OPST_BIST (0b00 << 30)
> +#define SEED_OPST_WAIT (0b01 << 30)
> +#define SEED_OPST_ES16 (0b10 << 30)
> +#define SEED_OPST_DEAD (0b11 << 30)
> #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index adb3d4381d..9d93e72f68 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -22,6 +22,8 @@
> #include "cpu.h"
> #include "qemu/main-loop.h"
> #include "exec/exec-all.h"
> +#include "qemu/guest-random.h"
> +#include "qapi/error.h"
>
> /* CSR function table public API */
> void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
> @@ -222,6 +224,38 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
> }
> #endif
>
> +/* Predicates */
> +static RISCVException seed(CPURISCVState *env, int csrno)
> +{
> + RISCVCPU *cpu = env_archcpu(env);
New line between declarations and code please
> + if (!cpu->cfg.ext_zkr) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +#if !defined(CONFIG_USER_ONLY)
> + if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) {
> + /* Hypervisor extension is supported */
> + if (riscv_cpu_virt_enabled(env) && (env->priv != PRV_M)) {
> + if (env->mseccfg & MSECCFG_SSEED) {
> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> + } else {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + }
> + }
> + if (env->priv == PRV_M) {
> + return RISCV_EXCP_NONE;
> + } else if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
> + return RISCV_EXCP_NONE;
> + } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
> + return RISCV_EXCP_NONE;
> + } else {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +#else
> + return RISCV_EXCP_NONE;
> +#endif
> +}
> +
> /* User Floating-Point CSRs */
> static RISCVException read_fflags(CPURISCVState *env, int csrno,
> target_ulong *val)
> @@ -1785,6 +1819,39 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
>
> #endif
>
> +/* Crypto Extension */
> +static int read_seed(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = 0;
> + uint32_t return_status = SEED_OPST_ES16;
Keep variable declarations first please
> + *val = (*val) | return_status;
> + if (return_status == SEED_OPST_ES16) {
> + uint16_t random_number;
> + Error *err = NULL;
> + if (qemu_guest_getrandom(&random_number, sizeof(random_number),
> + &err) < 0) {
You can use qemu_guest_getrandom_nofail() instead and then not worry
about this error handling.
> + qemu_log_mask(LOG_UNIMP, "Seed: Crypto failure: %s",
> + error_get_pretty(err));
> + error_free(err);
> + return -1;
> + }
> + *val = (*val) | random_number;
> + } else if (return_status == SEED_OPST_BIST) {
> + /* Do nothing */
> + } else if (return_status == SEED_OPST_WAIT) {
> + /* Do nothing */
> + } else if (return_status == SEED_OPST_DEAD) {
> + /* Do nothing */
> + }
> + return 0;
RISCV_EXCP_NONE instead of 0
> +}
> +
> +static RISCVException write_seed(CPURISCVState *env, int csrno,
> + target_ulong val)
> +{
> + return RISCV_EXCP_NONE;
> +}
> +
> /*
> * riscv_csrrw - read and/or update control and status register
> *
> @@ -1823,6 +1890,10 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + if (!write_mask && (csrno == CSR_SEED)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
I think it would be better to remove this and use a rmw_*() function
instead. Then the read/write check can happen in the CSR access
function
Look at rmw_mip() for an example of implementing a rmw_*() function.
> +
> /* ensure the CSR extension is enabled. */
> if (!cpu->cfg.ext_icsr) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -2011,6 +2082,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_TIME] = { "time", ctr, read_time },
> [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
>
> + /* Crypto Extension */
> + [CSR_SEED] = { "seed", seed, read_seed, write_seed},
> +
> #if !defined(CONFIG_USER_ONLY)
> /* Machine Timers and Counters */
> [CSR_MCYCLE] = { "mcycle", any, read_instret },
> diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
> index a9a0b363a7..83135849bb 100644
> --- a/target/riscv/pmp.h
> +++ b/target/riscv/pmp.h
> @@ -37,9 +37,11 @@ typedef enum {
> } pmp_am_t;
>
> typedef enum {
> - MSECCFG_MML = 1 << 0,
> - MSECCFG_MMWP = 1 << 1,
> - MSECCFG_RLB = 1 << 2
> + MSECCFG_MML = 1 << 0,
> + MSECCFG_MMWP = 1 << 1,
> + MSECCFG_RLB = 1 << 2,
> + MSECCFG_USEED = 1 << 8,
> + MSECCFG_SSEED = 1 << 9
Why are these all being changed?
Alistair
> } mseccfg_field_t;
>
> typedef struct {
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
@ 2022-01-18 4:36 ` Alistair Francis
0 siblings, 0 replies; 40+ messages in thread
From: Alistair Francis @ 2022-01-18 4:36 UTC (permalink / raw)
To: Weiwei Li
Cc: Richard Henderson, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
lazyparser, luruibo2000, lustrew
On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - add SEED CSR
> - add USEED, SSEED fields for MSECCFG CSR
>
> Co-authored-by: Ruibo Lu <luruibo2000@163.com>
> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/cpu_bits.h | 9 +++++
> target/riscv/csr.c | 74 +++++++++++++++++++++++++++++++++++++++++
> target/riscv/pmp.h | 8 +++--
> 3 files changed, 88 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 5a6d49aa64..65c708622b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -374,6 +374,9 @@
> #define CSR_VSPMMASK 0x2c1
> #define CSR_VSPMBASE 0x2c2
>
> +/* Crypto Extension */
> +#define CSR_SEED 0x015
> +
> /* mstatus CSR bits */
> #define MSTATUS_UIE 0x00000001
> #define MSTATUS_SIE 0x00000002
> @@ -628,4 +631,10 @@ typedef enum RISCVException {
> #define UMTE_U_PM_INSN U_PM_INSN
> #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
>
> +/* seed CSR bits */
> +#define SEED_OPST (0b11 << 30)
> +#define SEED_OPST_BIST (0b00 << 30)
> +#define SEED_OPST_WAIT (0b01 << 30)
> +#define SEED_OPST_ES16 (0b10 << 30)
> +#define SEED_OPST_DEAD (0b11 << 30)
> #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index adb3d4381d..9d93e72f68 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -22,6 +22,8 @@
> #include "cpu.h"
> #include "qemu/main-loop.h"
> #include "exec/exec-all.h"
> +#include "qemu/guest-random.h"
> +#include "qapi/error.h"
>
> /* CSR function table public API */
> void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
> @@ -222,6 +224,38 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
> }
> #endif
>
> +/* Predicates */
> +static RISCVException seed(CPURISCVState *env, int csrno)
> +{
> + RISCVCPU *cpu = env_archcpu(env);
New line between declarations and code please
> + if (!cpu->cfg.ext_zkr) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +#if !defined(CONFIG_USER_ONLY)
> + if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) {
> + /* Hypervisor extension is supported */
> + if (riscv_cpu_virt_enabled(env) && (env->priv != PRV_M)) {
> + if (env->mseccfg & MSECCFG_SSEED) {
> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> + } else {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + }
> + }
> + if (env->priv == PRV_M) {
> + return RISCV_EXCP_NONE;
> + } else if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
> + return RISCV_EXCP_NONE;
> + } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
> + return RISCV_EXCP_NONE;
> + } else {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +#else
> + return RISCV_EXCP_NONE;
> +#endif
> +}
> +
> /* User Floating-Point CSRs */
> static RISCVException read_fflags(CPURISCVState *env, int csrno,
> target_ulong *val)
> @@ -1785,6 +1819,39 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
>
> #endif
>
> +/* Crypto Extension */
> +static int read_seed(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = 0;
> + uint32_t return_status = SEED_OPST_ES16;
Keep variable declarations first please
> + *val = (*val) | return_status;
> + if (return_status == SEED_OPST_ES16) {
> + uint16_t random_number;
> + Error *err = NULL;
> + if (qemu_guest_getrandom(&random_number, sizeof(random_number),
> + &err) < 0) {
You can use qemu_guest_getrandom_nofail() instead and then not worry
about this error handling.
> + qemu_log_mask(LOG_UNIMP, "Seed: Crypto failure: %s",
> + error_get_pretty(err));
> + error_free(err);
> + return -1;
> + }
> + *val = (*val) | random_number;
> + } else if (return_status == SEED_OPST_BIST) {
> + /* Do nothing */
> + } else if (return_status == SEED_OPST_WAIT) {
> + /* Do nothing */
> + } else if (return_status == SEED_OPST_DEAD) {
> + /* Do nothing */
> + }
> + return 0;
RISCV_EXCP_NONE instead of 0
> +}
> +
> +static RISCVException write_seed(CPURISCVState *env, int csrno,
> + target_ulong val)
> +{
> + return RISCV_EXCP_NONE;
> +}
> +
> /*
> * riscv_csrrw - read and/or update control and status register
> *
> @@ -1823,6 +1890,10 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + if (!write_mask && (csrno == CSR_SEED)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
I think it would be better to remove this and use a rmw_*() function
instead. Then the read/write check can happen in the CSR access
function
Look at rmw_mip() for an example of implementing a rmw_*() function.
> +
> /* ensure the CSR extension is enabled. */
> if (!cpu->cfg.ext_icsr) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -2011,6 +2082,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_TIME] = { "time", ctr, read_time },
> [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
>
> + /* Crypto Extension */
> + [CSR_SEED] = { "seed", seed, read_seed, write_seed},
> +
> #if !defined(CONFIG_USER_ONLY)
> /* Machine Timers and Counters */
> [CSR_MCYCLE] = { "mcycle", any, read_instret },
> diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
> index a9a0b363a7..83135849bb 100644
> --- a/target/riscv/pmp.h
> +++ b/target/riscv/pmp.h
> @@ -37,9 +37,11 @@ typedef enum {
> } pmp_am_t;
>
> typedef enum {
> - MSECCFG_MML = 1 << 0,
> - MSECCFG_MMWP = 1 << 1,
> - MSECCFG_RLB = 1 << 2
> + MSECCFG_MML = 1 << 0,
> + MSECCFG_MMWP = 1 << 1,
> + MSECCFG_RLB = 1 << 2,
> + MSECCFG_USEED = 1 << 8,
> + MSECCFG_SSEED = 1 << 9
Why are these all being changed?
Alistair
> } mseccfg_field_t;
>
> typedef struct {
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-18 4:40 ` Alistair Francis
-1 siblings, 0 replies; 40+ messages in thread
From: Alistair Francis @ 2022-01-18 4:40 UTC (permalink / raw)
To: Weiwei Li
Cc: lazyparser, open list:RISC-V, lustrew, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, luruibo2000, Alistair Francis
On Tue, Jan 11, 2022 at 1:56 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - reuse partial instructions of Zbb/Zbc extensions
> - add brev8, packh, unzip, zip, etc.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/bitmanip_helper.c | 74 ++++++++++++++
> target/riscv/helper.h | 5 +
> target/riscv/insn32.decode | 52 ++++++----
> target/riscv/insn_trans/trans_rvb.c.inc | 127 +++++++++++++++++++++---
> target/riscv/translate.c | 7 ++
> 5 files changed, 234 insertions(+), 31 deletions(-)
>
> diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
> index f1b5e5549f..dc3dcf685a 100644
> --- a/target/riscv/bitmanip_helper.c
> +++ b/target/riscv/bitmanip_helper.c
> @@ -49,3 +49,77 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
>
> return result;
> }
> +
> +static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
> +{
> + return ((x & mask) << shift) | ((x & ~mask) >> shift);
> +}
> +
> +target_ulong HELPER(brev8)(target_ulong rs1)
> +{
> + target_ulong x = rs1;
> + x = do_swap(x, 0x5555555555555555ull, 1);
> + x = do_swap(x, 0x3333333333333333ull, 2);
> + x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
> + return x;
> +}
> +
> +static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
> + uint32_t sz_log2)
> +{
> + target_ulong r = 0;
> + target_ulong sz = 1LL << sz_log2;
> + target_ulong mask = (1LL << sz) - 1;
> + for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
> + target_ulong pos = ((rs2 >> i) & mask) << sz_log2;
> + if (pos < sizeof(target_ulong) * 8) {
> + r |= ((rs1 >> pos) & mask) << i;
> + }
> + }
> + return r;
> +}
> +
> +target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
> +{
> + return do_xperm(rs1, rs2, 2);
> +}
> +
> +target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
> +{
> + return do_xperm(rs1, rs2, 3);
> +}
> +
> +static const uint64_t shuf_masks[] = {
> + dup_const(MO_8, 0x44),
> + dup_const(MO_8, 0x30),
> + dup_const(MO_16, 0x0f00),
> + dup_const(MO_32, 0xff0000)
> +};
> +
> +static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
> + uint64_t maskR, int shift)
> +{
> + target_ulong x = src & ~(maskL | maskR);
> + x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
> + return x;
> +}
> +
> +target_ulong HELPER(unzip)(target_ulong rs1)
> +{
> + target_ulong x = rs1;
> + x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
> + x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
> + x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
> + x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
> + return x;
> +}
> +
> +target_ulong HELPER(zip)(target_ulong rs1)
> +{
> + target_ulong x = rs1;
> + x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
> + x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
> + x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
> + x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
> + return x;
> +}
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 6cf6d6ce98..2bd6ac8280 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -66,6 +66,11 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
> /* Bitmanip */
> DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> +DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> +DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> +DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
> +DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
> +DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
>
> /* Floating Point - Half Precision */
> DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 5bbedc254c..7491b2d562 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -717,8 +717,22 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r
> sh3add_uw 0010000 .......... 110 ..... 0111011 @r
> slli_uw 00001 ............ 001 ..... 0011011 @sh
>
> -# *** RV32 Zbb Standard Extension ***
> +# *** RV32 Zbb/Zbkb Standard Extension ***
> andn 0100000 .......... 111 ..... 0110011 @r
> +rol 0110000 .......... 001 ..... 0110011 @r
> +ror 0110000 .......... 101 ..... 0110011 @r
> +rori 01100 ............ 101 ..... 0010011 @sh
> +# The encoding for rev8 differs between RV32 and RV64.
> +# rev8_32 denotes the RV32 variant.
> +rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
Why move these?
Alistair
> +# The encoding for zext.h differs between RV32 and RV64.
> +# zext_h_32 denotes the RV32 variant.
> +{
> + zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
> + pack 0000100 ..... ..... 100 ..... 0110011 @r
> +}
> +xnor 0100000 .......... 100 ..... 0110011 @r
> +# *** RV32 extra Zbb Standard Extension ***
> clz 011000 000000 ..... 001 ..... 0010011 @r2
> cpop 011000 000010 ..... 001 ..... 0010011 @r2
> ctz 011000 000001 ..... 001 ..... 0010011 @r2
> @@ -728,23 +742,15 @@ min 0000101 .......... 100 ..... 0110011 @r
> minu 0000101 .......... 101 ..... 0110011 @r
> orc_b 001010 000111 ..... 101 ..... 0010011 @r2
> orn 0100000 .......... 110 ..... 0110011 @r
> -# The encoding for rev8 differs between RV32 and RV64.
> -# rev8_32 denotes the RV32 variant.
> -rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
> -rol 0110000 .......... 001 ..... 0110011 @r
> -ror 0110000 .......... 101 ..... 0110011 @r
> -rori 01100 ............ 101 ..... 0010011 @sh
> sext_b 011000 000100 ..... 001 ..... 0010011 @r2
> sext_h 011000 000101 ..... 001 ..... 0010011 @r2
> -xnor 0100000 .......... 100 ..... 0110011 @r
> -# The encoding for zext.h differs between RV32 and RV64.
> -# zext_h_32 denotes the RV32 variant.
> -zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
> +# *** RV32 extra Zbkb Standard Extension ***
> +brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
> +packh 0000100 .......... 111 ..... 0110011 @r
> +unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
> +zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
>
> -# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
> -clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> -ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
> -cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
> +# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
> # The encoding for rev8 differs between RV32 and RV64.
> # When executing on RV64, the encoding used in RV32 is an illegal
> # instruction, so we use different handler functions to differentiate.
> @@ -755,13 +761,25 @@ rorw 0110000 .......... 101 ..... 0111011 @r
> # The encoding for zext.h differs between RV32 and RV64.
> # When executing on RV64, the encoding used in RV32 is an illegal
> # instruction, so we use different handler functions to differentiate.
> -zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
> +{
> + zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
> + packw 0000100 ..... ..... 100 ..... 0111011 @r
> +}
> +# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
> +clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
> +cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
>
> -# *** RV32 Zbc Standard Extension ***
> +# *** RV32 Zbc/Zbkc Standard Extension ***
> clmul 0000101 .......... 001 ..... 0110011 @r
> clmulh 0000101 .......... 011 ..... 0110011 @r
> +# *** RV32 extra Zbc Standard Extension ***
> clmulr 0000101 .......... 010 ..... 0110011 @r
>
> +# *** RV32 Zbkx Standard Extension ***
> +xperm4 0010100 .......... 010 ..... 0110011 @r
> +xperm8 0010100 .......... 100 ..... 0110011 @r
> +
> # *** RV32 Zbs Standard Extension ***
> bclr 0100100 .......... 001 ..... 0110011 @r
> bclri 01001. ........... 001 ..... 0010011 @sh
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 810431a1d6..a7fb34fb65 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -1,5 +1,5 @@
> /*
> - * RISC-V translation routines for the Zb[abcs] Standard Extension.
> + * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
> *
> * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
> * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
> @@ -42,6 +42,18 @@
> } \
> } while (0)
>
> +#define REQUIRE_ZBKB(ctx) do { \
> + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbkb) { \
> + return false; \
> + } \
> +} while (0)
> +
> +#define REQUIRE_ZBKX(ctx) do { \
> + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbkx) { \
> + return false; \
> + } \
> +} while (0)
> +
> static void gen_clz(TCGv ret, TCGv arg1)
> {
> tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
> @@ -85,19 +97,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
>
> static bool trans_andn(DisasContext *ctx, arg_andn *a)
> {
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_logic(ctx, a, tcg_gen_andc_tl);
> }
>
> static bool trans_orn(DisasContext *ctx, arg_orn *a)
> {
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_logic(ctx, a, tcg_gen_orc_tl);
> }
>
> static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
> {
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_logic(ctx, a, tcg_gen_eqv_tl);
> }
>
> @@ -247,7 +259,7 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
>
> static bool trans_ror(DisasContext *ctx, arg_ror *a)
> {
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
> }
>
> @@ -264,7 +276,7 @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
>
> static bool trans_rori(DisasContext *ctx, arg_rori *a)
> {
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
> tcg_gen_rotri_tl, gen_roriw, NULL);
> }
> @@ -289,7 +301,7 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
>
> static bool trans_rol(DisasContext *ctx, arg_rol *a)
> {
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
> }
>
> @@ -301,14 +313,14 @@ static void gen_rev8_32(TCGv ret, TCGv src1)
> static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
> {
> REQUIRE_32BIT(ctx);
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
> }
>
> static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
> }
>
> @@ -403,7 +415,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
> static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
> }
> @@ -411,7 +423,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
> static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> ctx->ol = MXL_RV32;
> return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
> }
> @@ -419,7 +431,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
> static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
> }
> @@ -483,7 +495,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
>
> static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
> {
> - REQUIRE_ZBC(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
> return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
> }
>
> @@ -495,7 +507,7 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
>
> static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
> {
> - REQUIRE_ZBC(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
> return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
> }
>
> @@ -504,3 +516,90 @@ static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
> REQUIRE_ZBC(ctx);
> return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
> }
> +
> +static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
> +{
> + tcg_gen_deposit_tl(ret, src1, src2,
> + TARGET_LONG_BITS / 2,
> + TARGET_LONG_BITS / 2);
> +}
> +
> +static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_ext8u_tl(t, src2);
> + tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
> + tcg_temp_free(t);
> +}
> +
> +static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_ext16s_tl(t, src2);
> + tcg_gen_deposit_tl(ret, src1, t, 16, 48);
> + tcg_temp_free(t);
> +}
> +
> +static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
> +{
> + REQUIRE_ZBKB(ctx);
> + TCGv dest = dest_gpr(ctx, a->rd);
> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> + gen_helper_brev8(dest, src1);
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> +static bool trans_pack(DisasContext *ctx, arg_pack *a)
> +{
> + REQUIRE_ZBKB(ctx);
> + return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
> +}
> +
> +static bool trans_packh(DisasContext *ctx, arg_packh *a)
> +{
> + REQUIRE_ZBKB(ctx);
> + return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
> +}
> +
> +static bool trans_packw(DisasContext *ctx, arg_packw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_ZBKB(ctx);
> + return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
> +}
> +
> +static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
> +{
> + REQUIRE_ZBKB(ctx);
> + REQUIRE_32BIT(ctx);
> +
> + TCGv dest = dest_gpr(ctx, a->rd);
> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> + gen_helper_unzip(dest, src1);
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> +static bool trans_zip(DisasContext *ctx, arg_zip *a)
> +{
> + REQUIRE_ZBKB(ctx);
> + REQUIRE_32BIT(ctx);
> + TCGv dest = dest_gpr(ctx, a->rd);
> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> + gen_helper_zip(dest, src1);
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> +static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
> +{
> + REQUIRE_ZBKX(ctx);
> + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
> +}
> +
> +static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
> +{
> + REQUIRE_ZBKX(ctx);
> + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 615048ec87..f3e37ddcd2 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -525,6 +525,13 @@ EX_SH(12)
> } \
> } while (0)
>
> +#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
> + if (!RISCV_CPU(ctx->cs)->cfg.ext_##A && \
> + !RISCV_CPU(ctx->cs)->cfg.ext_##B) { \
> + return false; \
> + } \
> +} while (0)
> +
> static int ex_rvc_register(DisasContext *ctx, int reg)
> {
> return 8 + reg;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
@ 2022-01-18 4:40 ` Alistair Francis
0 siblings, 0 replies; 40+ messages in thread
From: Alistair Francis @ 2022-01-18 4:40 UTC (permalink / raw)
To: Weiwei Li
Cc: Richard Henderson, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
lazyparser, luruibo2000, lustrew
On Tue, Jan 11, 2022 at 1:56 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - reuse partial instructions of Zbb/Zbc extensions
> - add brev8, packh, unzip, zip, etc.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/bitmanip_helper.c | 74 ++++++++++++++
> target/riscv/helper.h | 5 +
> target/riscv/insn32.decode | 52 ++++++----
> target/riscv/insn_trans/trans_rvb.c.inc | 127 +++++++++++++++++++++---
> target/riscv/translate.c | 7 ++
> 5 files changed, 234 insertions(+), 31 deletions(-)
>
> diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
> index f1b5e5549f..dc3dcf685a 100644
> --- a/target/riscv/bitmanip_helper.c
> +++ b/target/riscv/bitmanip_helper.c
> @@ -49,3 +49,77 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
>
> return result;
> }
> +
> +static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
> +{
> + return ((x & mask) << shift) | ((x & ~mask) >> shift);
> +}
> +
> +target_ulong HELPER(brev8)(target_ulong rs1)
> +{
> + target_ulong x = rs1;
> + x = do_swap(x, 0x5555555555555555ull, 1);
> + x = do_swap(x, 0x3333333333333333ull, 2);
> + x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
> + return x;
> +}
> +
> +static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
> + uint32_t sz_log2)
> +{
> + target_ulong r = 0;
> + target_ulong sz = 1LL << sz_log2;
> + target_ulong mask = (1LL << sz) - 1;
> + for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
> + target_ulong pos = ((rs2 >> i) & mask) << sz_log2;
> + if (pos < sizeof(target_ulong) * 8) {
> + r |= ((rs1 >> pos) & mask) << i;
> + }
> + }
> + return r;
> +}
> +
> +target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
> +{
> + return do_xperm(rs1, rs2, 2);
> +}
> +
> +target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
> +{
> + return do_xperm(rs1, rs2, 3);
> +}
> +
> +static const uint64_t shuf_masks[] = {
> + dup_const(MO_8, 0x44),
> + dup_const(MO_8, 0x30),
> + dup_const(MO_16, 0x0f00),
> + dup_const(MO_32, 0xff0000)
> +};
> +
> +static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
> + uint64_t maskR, int shift)
> +{
> + target_ulong x = src & ~(maskL | maskR);
> + x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
> + return x;
> +}
> +
> +target_ulong HELPER(unzip)(target_ulong rs1)
> +{
> + target_ulong x = rs1;
> + x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
> + x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
> + x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
> + x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
> + return x;
> +}
> +
> +target_ulong HELPER(zip)(target_ulong rs1)
> +{
> + target_ulong x = rs1;
> + x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
> + x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
> + x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
> + x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
> + return x;
> +}
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 6cf6d6ce98..2bd6ac8280 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -66,6 +66,11 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
> /* Bitmanip */
> DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> +DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> +DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> +DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
> +DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
> +DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
>
> /* Floating Point - Half Precision */
> DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 5bbedc254c..7491b2d562 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -717,8 +717,22 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r
> sh3add_uw 0010000 .......... 110 ..... 0111011 @r
> slli_uw 00001 ............ 001 ..... 0011011 @sh
>
> -# *** RV32 Zbb Standard Extension ***
> +# *** RV32 Zbb/Zbkb Standard Extension ***
> andn 0100000 .......... 111 ..... 0110011 @r
> +rol 0110000 .......... 001 ..... 0110011 @r
> +ror 0110000 .......... 101 ..... 0110011 @r
> +rori 01100 ............ 101 ..... 0010011 @sh
> +# The encoding for rev8 differs between RV32 and RV64.
> +# rev8_32 denotes the RV32 variant.
> +rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
Why move these?
Alistair
> +# The encoding for zext.h differs between RV32 and RV64.
> +# zext_h_32 denotes the RV32 variant.
> +{
> + zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
> + pack 0000100 ..... ..... 100 ..... 0110011 @r
> +}
> +xnor 0100000 .......... 100 ..... 0110011 @r
> +# *** RV32 extra Zbb Standard Extension ***
> clz 011000 000000 ..... 001 ..... 0010011 @r2
> cpop 011000 000010 ..... 001 ..... 0010011 @r2
> ctz 011000 000001 ..... 001 ..... 0010011 @r2
> @@ -728,23 +742,15 @@ min 0000101 .......... 100 ..... 0110011 @r
> minu 0000101 .......... 101 ..... 0110011 @r
> orc_b 001010 000111 ..... 101 ..... 0010011 @r2
> orn 0100000 .......... 110 ..... 0110011 @r
> -# The encoding for rev8 differs between RV32 and RV64.
> -# rev8_32 denotes the RV32 variant.
> -rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
> -rol 0110000 .......... 001 ..... 0110011 @r
> -ror 0110000 .......... 101 ..... 0110011 @r
> -rori 01100 ............ 101 ..... 0010011 @sh
> sext_b 011000 000100 ..... 001 ..... 0010011 @r2
> sext_h 011000 000101 ..... 001 ..... 0010011 @r2
> -xnor 0100000 .......... 100 ..... 0110011 @r
> -# The encoding for zext.h differs between RV32 and RV64.
> -# zext_h_32 denotes the RV32 variant.
> -zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
> +# *** RV32 extra Zbkb Standard Extension ***
> +brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
> +packh 0000100 .......... 111 ..... 0110011 @r
> +unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
> +zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
>
> -# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
> -clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> -ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
> -cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
> +# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
> # The encoding for rev8 differs between RV32 and RV64.
> # When executing on RV64, the encoding used in RV32 is an illegal
> # instruction, so we use different handler functions to differentiate.
> @@ -755,13 +761,25 @@ rorw 0110000 .......... 101 ..... 0111011 @r
> # The encoding for zext.h differs between RV32 and RV64.
> # When executing on RV64, the encoding used in RV32 is an illegal
> # instruction, so we use different handler functions to differentiate.
> -zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
> +{
> + zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
> + packw 0000100 ..... ..... 100 ..... 0111011 @r
> +}
> +# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
> +clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
> +cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
>
> -# *** RV32 Zbc Standard Extension ***
> +# *** RV32 Zbc/Zbkc Standard Extension ***
> clmul 0000101 .......... 001 ..... 0110011 @r
> clmulh 0000101 .......... 011 ..... 0110011 @r
> +# *** RV32 extra Zbc Standard Extension ***
> clmulr 0000101 .......... 010 ..... 0110011 @r
>
> +# *** RV32 Zbkx Standard Extension ***
> +xperm4 0010100 .......... 010 ..... 0110011 @r
> +xperm8 0010100 .......... 100 ..... 0110011 @r
> +
> # *** RV32 Zbs Standard Extension ***
> bclr 0100100 .......... 001 ..... 0110011 @r
> bclri 01001. ........... 001 ..... 0010011 @sh
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 810431a1d6..a7fb34fb65 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -1,5 +1,5 @@
> /*
> - * RISC-V translation routines for the Zb[abcs] Standard Extension.
> + * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
> *
> * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
> * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
> @@ -42,6 +42,18 @@
> } \
> } while (0)
>
> +#define REQUIRE_ZBKB(ctx) do { \
> + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbkb) { \
> + return false; \
> + } \
> +} while (0)
> +
> +#define REQUIRE_ZBKX(ctx) do { \
> + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbkx) { \
> + return false; \
> + } \
> +} while (0)
> +
> static void gen_clz(TCGv ret, TCGv arg1)
> {
> tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
> @@ -85,19 +97,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
>
> static bool trans_andn(DisasContext *ctx, arg_andn *a)
> {
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_logic(ctx, a, tcg_gen_andc_tl);
> }
>
> static bool trans_orn(DisasContext *ctx, arg_orn *a)
> {
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_logic(ctx, a, tcg_gen_orc_tl);
> }
>
> static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
> {
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_logic(ctx, a, tcg_gen_eqv_tl);
> }
>
> @@ -247,7 +259,7 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
>
> static bool trans_ror(DisasContext *ctx, arg_ror *a)
> {
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
> }
>
> @@ -264,7 +276,7 @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
>
> static bool trans_rori(DisasContext *ctx, arg_rori *a)
> {
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
> tcg_gen_rotri_tl, gen_roriw, NULL);
> }
> @@ -289,7 +301,7 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
>
> static bool trans_rol(DisasContext *ctx, arg_rol *a)
> {
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
> }
>
> @@ -301,14 +313,14 @@ static void gen_rev8_32(TCGv ret, TCGv src1)
> static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
> {
> REQUIRE_32BIT(ctx);
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
> }
>
> static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
> }
>
> @@ -403,7 +415,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
> static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
> }
> @@ -411,7 +423,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
> static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> ctx->ol = MXL_RV32;
> return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
> }
> @@ -419,7 +431,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
> static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
> {
> REQUIRE_64BIT(ctx);
> - REQUIRE_ZBB(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
> ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
> }
> @@ -483,7 +495,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
>
> static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
> {
> - REQUIRE_ZBC(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
> return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
> }
>
> @@ -495,7 +507,7 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
>
> static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
> {
> - REQUIRE_ZBC(ctx);
> + REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
> return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
> }
>
> @@ -504,3 +516,90 @@ static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
> REQUIRE_ZBC(ctx);
> return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
> }
> +
> +static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
> +{
> + tcg_gen_deposit_tl(ret, src1, src2,
> + TARGET_LONG_BITS / 2,
> + TARGET_LONG_BITS / 2);
> +}
> +
> +static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_ext8u_tl(t, src2);
> + tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
> + tcg_temp_free(t);
> +}
> +
> +static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_ext16s_tl(t, src2);
> + tcg_gen_deposit_tl(ret, src1, t, 16, 48);
> + tcg_temp_free(t);
> +}
> +
> +static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
> +{
> + REQUIRE_ZBKB(ctx);
> + TCGv dest = dest_gpr(ctx, a->rd);
> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> + gen_helper_brev8(dest, src1);
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> +static bool trans_pack(DisasContext *ctx, arg_pack *a)
> +{
> + REQUIRE_ZBKB(ctx);
> + return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
> +}
> +
> +static bool trans_packh(DisasContext *ctx, arg_packh *a)
> +{
> + REQUIRE_ZBKB(ctx);
> + return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
> +}
> +
> +static bool trans_packw(DisasContext *ctx, arg_packw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_ZBKB(ctx);
> + return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
> +}
> +
> +static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
> +{
> + REQUIRE_ZBKB(ctx);
> + REQUIRE_32BIT(ctx);
> +
> + TCGv dest = dest_gpr(ctx, a->rd);
> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> + gen_helper_unzip(dest, src1);
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> +static bool trans_zip(DisasContext *ctx, arg_zip *a)
> +{
> + REQUIRE_ZBKB(ctx);
> + REQUIRE_32BIT(ctx);
> + TCGv dest = dest_gpr(ctx, a->rd);
> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> + gen_helper_zip(dest, src1);
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> +static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
> +{
> + REQUIRE_ZBKX(ctx);
> + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
> +}
> +
> +static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
> +{
> + REQUIRE_ZBKX(ctx);
> + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 615048ec87..f3e37ddcd2 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -525,6 +525,13 @@ EX_SH(12)
> } \
> } while (0)
>
> +#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
> + if (!RISCV_CPU(ctx->cs)->cfg.ext_##A && \
> + !RISCV_CPU(ctx->cs)->cfg.ext_##B) { \
> + return false; \
> + } \
> +} while (0)
> +
> static int ex_rvc_register(DisasContext *ctx, int reg)
> {
> return 8 + reg;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 0/7] support subsets of scalar crypto extension
2022-01-11 3:51 ` Weiwei Li
@ 2022-01-18 4:41 ` Alistair Francis
-1 siblings, 0 replies; 40+ messages in thread
From: Alistair Francis @ 2022-01-18 4:41 UTC (permalink / raw)
To: Weiwei Li
Cc: lazyparser, open list:RISC-V, lustrew, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, luruibo2000, Alistair Francis
On Tue, Jan 11, 2022 at 1:54 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> This patchset implements RISC-V scalar crypto extension v1.0.0 version instructions.
> Partial instructions are reused from B-extension.
>
> Specification:
> https://github.com/riscv/riscv-crypto
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4
>
> To test rvk implementation, specify cpu argument with 'zks=true,zkn=true'
> or
> "zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true"
> to enable K-extension support. This implementation can pass the ACT tests
> for K with our extended act support for qemu (available at
> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4-with-act)
>
> v4:
> * drop "x-" in exposed properties
> * delete unrelated changes
>
> v3:
> * add extension check for SEED csr access
>
> v2:
> * optimize implementation for brev8, xperm, zip, unzip
> * use aes related sbox array from crypto/aes.h
> * move sm4_sbox to crypto/sm4.c, and share it with target/arm
>
> Weiwei Li (7):
> target/riscv: rvk: add cfg properties for zbk* and zk*
> target/riscv: rvk: add implementation of instructions for Zbk*
> crypto include/crypto target/arm: move sm4_sbox to crypto
> target/riscv: rvk: add implementation of instructions for Zk*
> target/riscv: rvk: add CSR support for Zkr
> disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
> target/riscv: rvk: expose zbk* and zk* properties
Thanks for the patches!
Overall this looks good, just some small comments on the individual patches.
For the next version do you mind splitting the patches up a little bit
more? That will make it easier and faster to review
Alistair
>
> crypto/meson.build | 1 +
> crypto/sm4.c | 49 +++
> disas/riscv.c | 170 +++++++++
> include/crypto/sm4.h | 6 +
> target/arm/crypto_helper.c | 36 +-
> target/riscv/bitmanip_helper.c | 74 ++++
> target/riscv/cpu.c | 37 ++
> target/riscv/cpu.h | 13 +
> target/riscv/cpu_bits.h | 9 +
> target/riscv/crypto_helper.c | 446 ++++++++++++++++++++++
> target/riscv/csr.c | 74 ++++
> target/riscv/helper.h | 42 +++
> target/riscv/insn32.decode | 94 ++++-
> target/riscv/insn_trans/trans_rvb.c.inc | 127 ++++++-
> target/riscv/insn_trans/trans_rvk.c.inc | 467 ++++++++++++++++++++++++
> target/riscv/meson.build | 3 +-
> target/riscv/pmp.h | 8 +-
> target/riscv/translate.c | 8 +
> 18 files changed, 1594 insertions(+), 70 deletions(-)
> create mode 100644 crypto/sm4.c
> create mode 100644 include/crypto/sm4.h
> create mode 100644 target/riscv/crypto_helper.c
> create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 0/7] support subsets of scalar crypto extension
@ 2022-01-18 4:41 ` Alistair Francis
0 siblings, 0 replies; 40+ messages in thread
From: Alistair Francis @ 2022-01-18 4:41 UTC (permalink / raw)
To: Weiwei Li
Cc: Richard Henderson, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
lazyparser, luruibo2000, lustrew
On Tue, Jan 11, 2022 at 1:54 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> This patchset implements RISC-V scalar crypto extension v1.0.0 version instructions.
> Partial instructions are reused from B-extension.
>
> Specification:
> https://github.com/riscv/riscv-crypto
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4
>
> To test rvk implementation, specify cpu argument with 'zks=true,zkn=true'
> or
> "zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true"
> to enable K-extension support. This implementation can pass the ACT tests
> for K with our extended act support for qemu (available at
> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4-with-act)
>
> v4:
> * drop "x-" in exposed properties
> * delete unrelated changes
>
> v3:
> * add extension check for SEED csr access
>
> v2:
> * optimize implementation for brev8, xperm, zip, unzip
> * use aes related sbox array from crypto/aes.h
> * move sm4_sbox to crypto/sm4.c, and share it with target/arm
>
> Weiwei Li (7):
> target/riscv: rvk: add cfg properties for zbk* and zk*
> target/riscv: rvk: add implementation of instructions for Zbk*
> crypto include/crypto target/arm: move sm4_sbox to crypto
> target/riscv: rvk: add implementation of instructions for Zk*
> target/riscv: rvk: add CSR support for Zkr
> disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
> target/riscv: rvk: expose zbk* and zk* properties
Thanks for the patches!
Overall this looks good, just some small comments on the individual patches.
For the next version do you mind splitting the patches up a little bit
more? That will make it easier and faster to review
Alistair
>
> crypto/meson.build | 1 +
> crypto/sm4.c | 49 +++
> disas/riscv.c | 170 +++++++++
> include/crypto/sm4.h | 6 +
> target/arm/crypto_helper.c | 36 +-
> target/riscv/bitmanip_helper.c | 74 ++++
> target/riscv/cpu.c | 37 ++
> target/riscv/cpu.h | 13 +
> target/riscv/cpu_bits.h | 9 +
> target/riscv/crypto_helper.c | 446 ++++++++++++++++++++++
> target/riscv/csr.c | 74 ++++
> target/riscv/helper.h | 42 +++
> target/riscv/insn32.decode | 94 ++++-
> target/riscv/insn_trans/trans_rvb.c.inc | 127 ++++++-
> target/riscv/insn_trans/trans_rvk.c.inc | 467 ++++++++++++++++++++++++
> target/riscv/meson.build | 3 +-
> target/riscv/pmp.h | 8 +-
> target/riscv/translate.c | 8 +
> 18 files changed, 1594 insertions(+), 70 deletions(-)
> create mode 100644 crypto/sm4.c
> create mode 100644 include/crypto/sm4.h
> create mode 100644 target/riscv/crypto_helper.c
> create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
2022-01-18 4:21 ` Alistair Francis
@ 2022-01-18 8:08 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-18 8:08 UTC (permalink / raw)
To: Alistair Francis
Cc: lazyparser, open list:RISC-V, lustrew, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, luruibo2000, Alistair Francis
在 2022/1/18 下午12:21, Alistair Francis 写道:
> On Tue, Jan 11, 2022 at 2:01 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> Co-authored-by: Ruibo Lu <luruibo2000@163.com>
>> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>> target/riscv/crypto_helper.c | 446 ++++++++++++++++++++++
>> target/riscv/helper.h | 37 ++
>> target/riscv/insn32.decode | 42 +++
>> target/riscv/insn_trans/trans_rvk.c.inc | 467 ++++++++++++++++++++++++
>> target/riscv/meson.build | 3 +-
>> target/riscv/translate.c | 1 +
>> 6 files changed, 995 insertions(+), 1 deletion(-)
>> create mode 100644 target/riscv/crypto_helper.c
>> create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>>
>> diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
>> new file mode 100644
>> index 0000000000..344eea4287
>> --- /dev/null
>> +++ b/target/riscv/crypto_helper.c
>> @@ -0,0 +1,446 @@
>> +/*
>> + * RISC-V Crypto Emulation Helpers for QEMU.
>> + *
>> + * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
>> + * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2 or later, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "cpu.h"
>> +#include "exec/exec-all.h"
>> +#include "exec/helper-proto.h"
>> +#include "crypto/aes.h"
>> +#include "crypto/sm4.h"
>> +
>> +#define AES_XTIME(a) \
>> + ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
>> +
>> +#define AES_GFMUL(a, b) (( \
>> + (((b) & 0x1) ? (a) : 0) ^ \
>> + (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
>> + (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
>> + (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
>> +
>> +#define BY(X, I) ((X >> (8 * I)) & 0xFF)
>> +
>> +#define AES_SHIFROWS_LO(RS1, RS2) ( \
>> + (((RS1 >> 24) & 0xFF) << 56) | \
>> + (((RS2 >> 48) & 0xFF) << 48) | \
>> + (((RS2 >> 8) & 0xFF) << 40) | \
>> + (((RS1 >> 32) & 0xFF) << 32) | \
>> + (((RS2 >> 56) & 0xFF) << 24) | \
>> + (((RS2 >> 16) & 0xFF) << 16) | \
>> + (((RS1 >> 40) & 0xFF) << 8) | \
>> + (((RS1 >> 0) & 0xFF) << 0))
>> +
>> +#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
>> + (((RS2 >> 24) & 0xFF) << 56) | \
>> + (((RS2 >> 48) & 0xFF) << 48) | \
>> + (((RS1 >> 8) & 0xFF) << 40) | \
>> + (((RS1 >> 32) & 0xFF) << 32) | \
>> + (((RS1 >> 56) & 0xFF) << 24) | \
>> + (((RS2 >> 16) & 0xFF) << 16) | \
>> + (((RS2 >> 40) & 0xFF) << 8) | \
>> + (((RS1 >> 0) & 0xFF) << 0))
>> +
>> +#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
>> + BY(COL, B3) ^ \
>> + BY(COL, B2) ^ \
>> + AES_GFMUL(BY(COL, B1), 3) ^ \
>> + AES_GFMUL(BY(COL, B0), 2) \
>> +)
>> +
>> +#define AES_MIXCOLUMN(COL) ( \
>> + AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
>> + AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
>> + AES_MIXBYTE(COL, 1, 2, 3, 0) << 8 | \
>> + AES_MIXBYTE(COL, 0, 1, 2, 3) << 0 \
>> +)
>> +
>> +#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
>> + AES_GFMUL(BY(COL, B3), 0x9) ^ \
>> + AES_GFMUL(BY(COL, B2), 0xd) ^ \
>> + AES_GFMUL(BY(COL, B1), 0xb) ^ \
>> + AES_GFMUL(BY(COL, B0), 0xe) \
>> +)
>> +
>> +#define AES_INVMIXCOLUMN(COL) ( \
>> + AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
>> + AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
>> + AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
>> + AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0 \
>> +)
>> +
>> +static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
>> +{
>> + uint32_t u;
>> + if (fwd) {
>> + u = (AES_GFMUL(x, 3) << 24) |
>> + (x << 16) |
>> + (x << 8) |
>> + (AES_GFMUL(x, 2) << 0);
>> + } else {
>> + u = (AES_GFMUL(x, 0xb) << 24) |
>> + (AES_GFMUL(x, 0xd) << 16) |
>> + (AES_GFMUL(x, 0x9) << 8) |
>> + (AES_GFMUL(x, 0xe) << 0);
>> + }
>> + return u;
>> +}
>> +
>> +#define XLEN (8 * sizeof(target_ulong))
> I don't think this is used, but please don't hard coded xlen's.
> Everything should be dynamic based on the CPU xlen.
>
> It would also be great if you could split this patch up more. There is
> a lot being added here.
>
> Alistair
OK. Thanks for your comments. I'll delete XLEN and split this patch.
Regards,
Weiwei Li
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
@ 2022-01-18 8:08 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-18 8:08 UTC (permalink / raw)
To: Alistair Francis
Cc: Richard Henderson, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
lazyparser, luruibo2000, lustrew
在 2022/1/18 下午12:21, Alistair Francis 写道:
> On Tue, Jan 11, 2022 at 2:01 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> Co-authored-by: Ruibo Lu <luruibo2000@163.com>
>> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>> target/riscv/crypto_helper.c | 446 ++++++++++++++++++++++
>> target/riscv/helper.h | 37 ++
>> target/riscv/insn32.decode | 42 +++
>> target/riscv/insn_trans/trans_rvk.c.inc | 467 ++++++++++++++++++++++++
>> target/riscv/meson.build | 3 +-
>> target/riscv/translate.c | 1 +
>> 6 files changed, 995 insertions(+), 1 deletion(-)
>> create mode 100644 target/riscv/crypto_helper.c
>> create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>>
>> diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
>> new file mode 100644
>> index 0000000000..344eea4287
>> --- /dev/null
>> +++ b/target/riscv/crypto_helper.c
>> @@ -0,0 +1,446 @@
>> +/*
>> + * RISC-V Crypto Emulation Helpers for QEMU.
>> + *
>> + * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
>> + * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2 or later, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "cpu.h"
>> +#include "exec/exec-all.h"
>> +#include "exec/helper-proto.h"
>> +#include "crypto/aes.h"
>> +#include "crypto/sm4.h"
>> +
>> +#define AES_XTIME(a) \
>> + ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
>> +
>> +#define AES_GFMUL(a, b) (( \
>> + (((b) & 0x1) ? (a) : 0) ^ \
>> + (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
>> + (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
>> + (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
>> +
>> +#define BY(X, I) ((X >> (8 * I)) & 0xFF)
>> +
>> +#define AES_SHIFROWS_LO(RS1, RS2) ( \
>> + (((RS1 >> 24) & 0xFF) << 56) | \
>> + (((RS2 >> 48) & 0xFF) << 48) | \
>> + (((RS2 >> 8) & 0xFF) << 40) | \
>> + (((RS1 >> 32) & 0xFF) << 32) | \
>> + (((RS2 >> 56) & 0xFF) << 24) | \
>> + (((RS2 >> 16) & 0xFF) << 16) | \
>> + (((RS1 >> 40) & 0xFF) << 8) | \
>> + (((RS1 >> 0) & 0xFF) << 0))
>> +
>> +#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
>> + (((RS2 >> 24) & 0xFF) << 56) | \
>> + (((RS2 >> 48) & 0xFF) << 48) | \
>> + (((RS1 >> 8) & 0xFF) << 40) | \
>> + (((RS1 >> 32) & 0xFF) << 32) | \
>> + (((RS1 >> 56) & 0xFF) << 24) | \
>> + (((RS2 >> 16) & 0xFF) << 16) | \
>> + (((RS2 >> 40) & 0xFF) << 8) | \
>> + (((RS1 >> 0) & 0xFF) << 0))
>> +
>> +#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
>> + BY(COL, B3) ^ \
>> + BY(COL, B2) ^ \
>> + AES_GFMUL(BY(COL, B1), 3) ^ \
>> + AES_GFMUL(BY(COL, B0), 2) \
>> +)
>> +
>> +#define AES_MIXCOLUMN(COL) ( \
>> + AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
>> + AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
>> + AES_MIXBYTE(COL, 1, 2, 3, 0) << 8 | \
>> + AES_MIXBYTE(COL, 0, 1, 2, 3) << 0 \
>> +)
>> +
>> +#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
>> + AES_GFMUL(BY(COL, B3), 0x9) ^ \
>> + AES_GFMUL(BY(COL, B2), 0xd) ^ \
>> + AES_GFMUL(BY(COL, B1), 0xb) ^ \
>> + AES_GFMUL(BY(COL, B0), 0xe) \
>> +)
>> +
>> +#define AES_INVMIXCOLUMN(COL) ( \
>> + AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
>> + AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
>> + AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
>> + AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0 \
>> +)
>> +
>> +static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
>> +{
>> + uint32_t u;
>> + if (fwd) {
>> + u = (AES_GFMUL(x, 3) << 24) |
>> + (x << 16) |
>> + (x << 8) |
>> + (AES_GFMUL(x, 2) << 0);
>> + } else {
>> + u = (AES_GFMUL(x, 0xb) << 24) |
>> + (AES_GFMUL(x, 0xd) << 16) |
>> + (AES_GFMUL(x, 0x9) << 8) |
>> + (AES_GFMUL(x, 0xe) << 0);
>> + }
>> + return u;
>> +}
>> +
>> +#define XLEN (8 * sizeof(target_ulong))
> I don't think this is used, but please don't hard coded xlen's.
> Everything should be dynamic based on the CPU xlen.
>
> It would also be great if you could split this patch up more. There is
> a lot being added here.
>
> Alistair
OK. Thanks for your comments. I'll delete XLEN and split this patch.
Regards,
Weiwei Li
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
2022-01-18 4:23 ` Alistair Francis
@ 2022-01-18 8:09 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-18 8:09 UTC (permalink / raw)
To: Alistair Francis
Cc: lazyparser, open list:RISC-V, lustrew, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, luruibo2000, Alistair Francis
在 2022/1/18 下午12:23, Alistair Francis 写道:
> On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>> target/riscv/cpu.c | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index b487a8282c..628a782ba9 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -694,9 +694,23 @@ static Property riscv_cpu_properties[] = {
>> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
>> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>> DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
>> + DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
>> + DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
>> + DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
>> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
>> + DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
>> + DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
>> + DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
>> + DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
>> + DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
>> + DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
>> + DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
>> + DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
>> + DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
>> + DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
>>
>> /* These are experimental so mark with 'x-' */
>> + DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> Looks like a rebase error
>
> Alistair
Yeah. I'll fix this.
Regards,
Weiwei Li
>> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
>> /* ePMP 0.9.3 */
>> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
@ 2022-01-18 8:09 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-18 8:09 UTC (permalink / raw)
To: Alistair Francis
Cc: Richard Henderson, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
lazyparser, luruibo2000, lustrew
在 2022/1/18 下午12:23, Alistair Francis 写道:
> On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>> target/riscv/cpu.c | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index b487a8282c..628a782ba9 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -694,9 +694,23 @@ static Property riscv_cpu_properties[] = {
>> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
>> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>> DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
>> + DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
>> + DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
>> + DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
>> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
>> + DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
>> + DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
>> + DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
>> + DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
>> + DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
>> + DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
>> + DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
>> + DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
>> + DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
>> + DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
>>
>> /* These are experimental so mark with 'x-' */
>> + DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> Looks like a rebase error
>
> Alistair
Yeah. I'll fix this.
Regards,
Weiwei Li
>> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
>> /* ePMP 0.9.3 */
>> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
2022-01-18 4:36 ` Alistair Francis
@ 2022-01-18 8:14 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-18 8:14 UTC (permalink / raw)
To: Alistair Francis
Cc: lazyparser, open list:RISC-V, lustrew, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, luruibo2000, Alistair Francis
在 2022/1/18 下午12:36, Alistair Francis 写道:
> On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> - add SEED CSR
>> - add USEED, SSEED fields for MSECCFG CSR
>>
>> Co-authored-by: Ruibo Lu <luruibo2000@163.com>
>> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>> target/riscv/cpu_bits.h | 9 +++++
>> target/riscv/csr.c | 74 +++++++++++++++++++++++++++++++++++++++++
>> target/riscv/pmp.h | 8 +++--
>> 3 files changed, 88 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>> index 5a6d49aa64..65c708622b 100644
>> --- a/target/riscv/cpu_bits.h
>> +++ b/target/riscv/cpu_bits.h
>> @@ -374,6 +374,9 @@
>> #define CSR_VSPMMASK 0x2c1
>> #define CSR_VSPMBASE 0x2c2
>>
>> +/* Crypto Extension */
>> +#define CSR_SEED 0x015
>> +
>> /* mstatus CSR bits */
>> #define MSTATUS_UIE 0x00000001
>> #define MSTATUS_SIE 0x00000002
>> @@ -628,4 +631,10 @@ typedef enum RISCVException {
>> #define UMTE_U_PM_INSN U_PM_INSN
>> #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
>>
>> +/* seed CSR bits */
>> +#define SEED_OPST (0b11 << 30)
>> +#define SEED_OPST_BIST (0b00 << 30)
>> +#define SEED_OPST_WAIT (0b01 << 30)
>> +#define SEED_OPST_ES16 (0b10 << 30)
>> +#define SEED_OPST_DEAD (0b11 << 30)
>> #endif
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index adb3d4381d..9d93e72f68 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -22,6 +22,8 @@
>> #include "cpu.h"
>> #include "qemu/main-loop.h"
>> #include "exec/exec-all.h"
>> +#include "qemu/guest-random.h"
>> +#include "qapi/error.h"
>>
>> /* CSR function table public API */
>> void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
>> @@ -222,6 +224,38 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
>> }
>> #endif
>>
>> +/* Predicates */
>> +static RISCVException seed(CPURISCVState *env, int csrno)
>> +{
>> + RISCVCPU *cpu = env_archcpu(env);
> New line between declarations and code please
OK.
>> + if (!cpu->cfg.ext_zkr) {
>> + return RISCV_EXCP_ILLEGAL_INST;
>> + }
>> +#if !defined(CONFIG_USER_ONLY)
>> + if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) {
>> + /* Hypervisor extension is supported */
>> + if (riscv_cpu_virt_enabled(env) && (env->priv != PRV_M)) {
>> + if (env->mseccfg & MSECCFG_SSEED) {
>> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
>> + } else {
>> + return RISCV_EXCP_ILLEGAL_INST;
>> + }
>> + }
>> + }
>> + if (env->priv == PRV_M) {
>> + return RISCV_EXCP_NONE;
>> + } else if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
>> + return RISCV_EXCP_NONE;
>> + } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
>> + return RISCV_EXCP_NONE;
>> + } else {
>> + return RISCV_EXCP_ILLEGAL_INST;
>> + }
>> +#else
>> + return RISCV_EXCP_NONE;
>> +#endif
>> +}
>> +
>> /* User Floating-Point CSRs */
>> static RISCVException read_fflags(CPURISCVState *env, int csrno,
>> target_ulong *val)
>> @@ -1785,6 +1819,39 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
>>
>> #endif
>>
>> +/* Crypto Extension */
>> +static int read_seed(CPURISCVState *env, int csrno, target_ulong *val)
>> +{
>> + *val = 0;
>> + uint32_t return_status = SEED_OPST_ES16;
> Keep variable declarations first please
>
OK.
>> + *val = (*val) | return_status;
>> + if (return_status == SEED_OPST_ES16) {
>> + uint16_t random_number;
>> + Error *err = NULL;
>> + if (qemu_guest_getrandom(&random_number, sizeof(random_number),
>> + &err) < 0) {
> You can use qemu_guest_getrandom_nofail() instead and then not worry
> about this error handling.
>
>
OK. I'll update this.
>> + qemu_log_mask(LOG_UNIMP, "Seed: Crypto failure: %s",
>> + error_get_pretty(err));
>> + error_free(err);
>> + return -1;
>> + }
>> + *val = (*val) | random_number;
>> + } else if (return_status == SEED_OPST_BIST) {
>> + /* Do nothing */
>> + } else if (return_status == SEED_OPST_WAIT) {
>> + /* Do nothing */
>> + } else if (return_status == SEED_OPST_DEAD) {
>> + /* Do nothing */
>> + }
>> + return 0;
> RISCV_EXCP_NONE instead of 0
OK.
>> +}
>> +
>> +static RISCVException write_seed(CPURISCVState *env, int csrno,
>> + target_ulong val)
>> +{
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> /*
>> * riscv_csrrw - read and/or update control and status register
>> *
>> @@ -1823,6 +1890,10 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
>> return RISCV_EXCP_ILLEGAL_INST;
>> }
>>
>> + if (!write_mask && (csrno == CSR_SEED)) {
>> + return RISCV_EXCP_ILLEGAL_INST;
>> + }
> I think it would be better to remove this and use a rmw_*() function
> instead. Then the read/write check can happen in the CSR access
> function
>
> Look at rmw_mip() for an example of implementing a rmw_*() function.
OK. I'll update this.
>> +
>> /* ensure the CSR extension is enabled. */
>> if (!cpu->cfg.ext_icsr) {
>> return RISCV_EXCP_ILLEGAL_INST;
>> @@ -2011,6 +2082,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>> [CSR_TIME] = { "time", ctr, read_time },
>> [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
>>
>> + /* Crypto Extension */
>> + [CSR_SEED] = { "seed", seed, read_seed, write_seed},
>> +
>> #if !defined(CONFIG_USER_ONLY)
>> /* Machine Timers and Counters */
>> [CSR_MCYCLE] = { "mcycle", any, read_instret },
>> diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
>> index a9a0b363a7..83135849bb 100644
>> --- a/target/riscv/pmp.h
>> +++ b/target/riscv/pmp.h
>> @@ -37,9 +37,11 @@ typedef enum {
>> } pmp_am_t;
>>
>> typedef enum {
>> - MSECCFG_MML = 1 << 0,
>> - MSECCFG_MMWP = 1 << 1,
>> - MSECCFG_RLB = 1 << 2
>> + MSECCFG_MML = 1 << 0,
>> + MSECCFG_MMWP = 1 << 1,
>> + MSECCFG_RLB = 1 << 2,
>> + MSECCFG_USEED = 1 << 8,
>> + MSECCFG_SSEED = 1 << 9
> Why are these all being changed?
>
> Alistair
>
USEED and SEED fields are added for the check of seed csr. the other
changes are to align with the new code for MSECCFG_SSEED and
MSECCFG_SSEED.
Regards,
Weiwei Li
>> } mseccfg_field_t;
>>
>> typedef struct {
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
@ 2022-01-18 8:14 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-18 8:14 UTC (permalink / raw)
To: Alistair Francis
Cc: Richard Henderson, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
lazyparser, luruibo2000, lustrew
在 2022/1/18 下午12:36, Alistair Francis 写道:
> On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> - add SEED CSR
>> - add USEED, SSEED fields for MSECCFG CSR
>>
>> Co-authored-by: Ruibo Lu <luruibo2000@163.com>
>> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>> target/riscv/cpu_bits.h | 9 +++++
>> target/riscv/csr.c | 74 +++++++++++++++++++++++++++++++++++++++++
>> target/riscv/pmp.h | 8 +++--
>> 3 files changed, 88 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>> index 5a6d49aa64..65c708622b 100644
>> --- a/target/riscv/cpu_bits.h
>> +++ b/target/riscv/cpu_bits.h
>> @@ -374,6 +374,9 @@
>> #define CSR_VSPMMASK 0x2c1
>> #define CSR_VSPMBASE 0x2c2
>>
>> +/* Crypto Extension */
>> +#define CSR_SEED 0x015
>> +
>> /* mstatus CSR bits */
>> #define MSTATUS_UIE 0x00000001
>> #define MSTATUS_SIE 0x00000002
>> @@ -628,4 +631,10 @@ typedef enum RISCVException {
>> #define UMTE_U_PM_INSN U_PM_INSN
>> #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
>>
>> +/* seed CSR bits */
>> +#define SEED_OPST (0b11 << 30)
>> +#define SEED_OPST_BIST (0b00 << 30)
>> +#define SEED_OPST_WAIT (0b01 << 30)
>> +#define SEED_OPST_ES16 (0b10 << 30)
>> +#define SEED_OPST_DEAD (0b11 << 30)
>> #endif
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index adb3d4381d..9d93e72f68 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -22,6 +22,8 @@
>> #include "cpu.h"
>> #include "qemu/main-loop.h"
>> #include "exec/exec-all.h"
>> +#include "qemu/guest-random.h"
>> +#include "qapi/error.h"
>>
>> /* CSR function table public API */
>> void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
>> @@ -222,6 +224,38 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
>> }
>> #endif
>>
>> +/* Predicates */
>> +static RISCVException seed(CPURISCVState *env, int csrno)
>> +{
>> + RISCVCPU *cpu = env_archcpu(env);
> New line between declarations and code please
OK.
>> + if (!cpu->cfg.ext_zkr) {
>> + return RISCV_EXCP_ILLEGAL_INST;
>> + }
>> +#if !defined(CONFIG_USER_ONLY)
>> + if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) {
>> + /* Hypervisor extension is supported */
>> + if (riscv_cpu_virt_enabled(env) && (env->priv != PRV_M)) {
>> + if (env->mseccfg & MSECCFG_SSEED) {
>> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
>> + } else {
>> + return RISCV_EXCP_ILLEGAL_INST;
>> + }
>> + }
>> + }
>> + if (env->priv == PRV_M) {
>> + return RISCV_EXCP_NONE;
>> + } else if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
>> + return RISCV_EXCP_NONE;
>> + } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
>> + return RISCV_EXCP_NONE;
>> + } else {
>> + return RISCV_EXCP_ILLEGAL_INST;
>> + }
>> +#else
>> + return RISCV_EXCP_NONE;
>> +#endif
>> +}
>> +
>> /* User Floating-Point CSRs */
>> static RISCVException read_fflags(CPURISCVState *env, int csrno,
>> target_ulong *val)
>> @@ -1785,6 +1819,39 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
>>
>> #endif
>>
>> +/* Crypto Extension */
>> +static int read_seed(CPURISCVState *env, int csrno, target_ulong *val)
>> +{
>> + *val = 0;
>> + uint32_t return_status = SEED_OPST_ES16;
> Keep variable declarations first please
>
OK.
>> + *val = (*val) | return_status;
>> + if (return_status == SEED_OPST_ES16) {
>> + uint16_t random_number;
>> + Error *err = NULL;
>> + if (qemu_guest_getrandom(&random_number, sizeof(random_number),
>> + &err) < 0) {
> You can use qemu_guest_getrandom_nofail() instead and then not worry
> about this error handling.
>
>
OK. I'll update this.
>> + qemu_log_mask(LOG_UNIMP, "Seed: Crypto failure: %s",
>> + error_get_pretty(err));
>> + error_free(err);
>> + return -1;
>> + }
>> + *val = (*val) | random_number;
>> + } else if (return_status == SEED_OPST_BIST) {
>> + /* Do nothing */
>> + } else if (return_status == SEED_OPST_WAIT) {
>> + /* Do nothing */
>> + } else if (return_status == SEED_OPST_DEAD) {
>> + /* Do nothing */
>> + }
>> + return 0;
> RISCV_EXCP_NONE instead of 0
OK.
>> +}
>> +
>> +static RISCVException write_seed(CPURISCVState *env, int csrno,
>> + target_ulong val)
>> +{
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> /*
>> * riscv_csrrw - read and/or update control and status register
>> *
>> @@ -1823,6 +1890,10 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
>> return RISCV_EXCP_ILLEGAL_INST;
>> }
>>
>> + if (!write_mask && (csrno == CSR_SEED)) {
>> + return RISCV_EXCP_ILLEGAL_INST;
>> + }
> I think it would be better to remove this and use a rmw_*() function
> instead. Then the read/write check can happen in the CSR access
> function
>
> Look at rmw_mip() for an example of implementing a rmw_*() function.
OK. I'll update this.
>> +
>> /* ensure the CSR extension is enabled. */
>> if (!cpu->cfg.ext_icsr) {
>> return RISCV_EXCP_ILLEGAL_INST;
>> @@ -2011,6 +2082,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>> [CSR_TIME] = { "time", ctr, read_time },
>> [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
>>
>> + /* Crypto Extension */
>> + [CSR_SEED] = { "seed", seed, read_seed, write_seed},
>> +
>> #if !defined(CONFIG_USER_ONLY)
>> /* Machine Timers and Counters */
>> [CSR_MCYCLE] = { "mcycle", any, read_instret },
>> diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
>> index a9a0b363a7..83135849bb 100644
>> --- a/target/riscv/pmp.h
>> +++ b/target/riscv/pmp.h
>> @@ -37,9 +37,11 @@ typedef enum {
>> } pmp_am_t;
>>
>> typedef enum {
>> - MSECCFG_MML = 1 << 0,
>> - MSECCFG_MMWP = 1 << 1,
>> - MSECCFG_RLB = 1 << 2
>> + MSECCFG_MML = 1 << 0,
>> + MSECCFG_MMWP = 1 << 1,
>> + MSECCFG_RLB = 1 << 2,
>> + MSECCFG_USEED = 1 << 8,
>> + MSECCFG_SSEED = 1 << 9
> Why are these all being changed?
>
> Alistair
>
USEED and SEED fields are added for the check of seed csr. the other
changes are to align with the new code for MSECCFG_SSEED and
MSECCFG_SSEED.
Regards,
Weiwei Li
>> } mseccfg_field_t;
>>
>> typedef struct {
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
2022-01-18 4:40 ` Alistair Francis
@ 2022-01-18 8:21 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-18 8:21 UTC (permalink / raw)
To: Alistair Francis
Cc: lazyparser, open list:RISC-V, lustrew, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, luruibo2000, Alistair Francis
在 2022/1/18 下午12:40, Alistair Francis 写道:
> On Tue, Jan 11, 2022 at 1:56 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> - reuse partial instructions of Zbb/Zbc extensions
>> - add brev8, packh, unzip, zip, etc.
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>> target/riscv/bitmanip_helper.c | 74 ++++++++++++++
>> target/riscv/helper.h | 5 +
>> target/riscv/insn32.decode | 52 ++++++----
>> target/riscv/insn_trans/trans_rvb.c.inc | 127 +++++++++++++++++++++---
>> target/riscv/translate.c | 7 ++
>> 5 files changed, 234 insertions(+), 31 deletions(-)
>>
>> diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
>> index f1b5e5549f..dc3dcf685a 100644
>> --- a/target/riscv/bitmanip_helper.c
>> +++ b/target/riscv/bitmanip_helper.c
>> @@ -49,3 +49,77 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
>>
>> return result;
>> }
>> +
>> +static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
>> +{
>> + return ((x & mask) << shift) | ((x & ~mask) >> shift);
>> +}
>> +
>> +target_ulong HELPER(brev8)(target_ulong rs1)
>> +{
>> + target_ulong x = rs1;
>> + x = do_swap(x, 0x5555555555555555ull, 1);
>> + x = do_swap(x, 0x3333333333333333ull, 2);
>> + x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
>> + return x;
>> +}
>> +
>> +static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
>> + uint32_t sz_log2)
>> +{
>> + target_ulong r = 0;
>> + target_ulong sz = 1LL << sz_log2;
>> + target_ulong mask = (1LL << sz) - 1;
>> + for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
>> + target_ulong pos = ((rs2 >> i) & mask) << sz_log2;
>> + if (pos < sizeof(target_ulong) * 8) {
>> + r |= ((rs1 >> pos) & mask) << i;
>> + }
>> + }
>> + return r;
>> +}
>> +
>> +target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
>> +{
>> + return do_xperm(rs1, rs2, 2);
>> +}
>> +
>> +target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
>> +{
>> + return do_xperm(rs1, rs2, 3);
>> +}
>> +
>> +static const uint64_t shuf_masks[] = {
>> + dup_const(MO_8, 0x44),
>> + dup_const(MO_8, 0x30),
>> + dup_const(MO_16, 0x0f00),
>> + dup_const(MO_32, 0xff0000)
>> +};
>> +
>> +static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
>> + uint64_t maskR, int shift)
>> +{
>> + target_ulong x = src & ~(maskL | maskR);
>> + x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
>> + return x;
>> +}
>> +
>> +target_ulong HELPER(unzip)(target_ulong rs1)
>> +{
>> + target_ulong x = rs1;
>> + x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
>> + x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
>> + x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
>> + x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
>> + return x;
>> +}
>> +
>> +target_ulong HELPER(zip)(target_ulong rs1)
>> +{
>> + target_ulong x = rs1;
>> + x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
>> + x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
>> + x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
>> + x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
>> + return x;
>> +}
>> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
>> index 6cf6d6ce98..2bd6ac8280 100644
>> --- a/target/riscv/helper.h
>> +++ b/target/riscv/helper.h
>> @@ -66,6 +66,11 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
>> /* Bitmanip */
>> DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
>> DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
>> +DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
>> +DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
>>
>> /* Floating Point - Half Precision */
>> DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
>> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
>> index 5bbedc254c..7491b2d562 100644
>> --- a/target/riscv/insn32.decode
>> +++ b/target/riscv/insn32.decode
>> @@ -717,8 +717,22 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r
>> sh3add_uw 0010000 .......... 110 ..... 0111011 @r
>> slli_uw 00001 ............ 001 ..... 0011011 @sh
>>
>> -# *** RV32 Zbb Standard Extension ***
>> +# *** RV32 Zbb/Zbkb Standard Extension ***
>> andn 0100000 .......... 111 ..... 0110011 @r
>> +rol 0110000 .......... 001 ..... 0110011 @r
>> +ror 0110000 .......... 101 ..... 0110011 @r
>> +rori 01100 ............ 101 ..... 0010011 @sh
>> +# The encoding for rev8 differs between RV32 and RV64.
>> +# rev8_32 denotes the RV32 variant.
>> +rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
> Why move these?
>
> Alistair
>
I mov these to divide instructions for only zbb (as RV32 extra Zbb
Standard Extension) and the instructions for both zbb and zbkb( as RV32
Zbb/Zbkb Standard Extension) .
Regards,
Weiwei Li
>> +# The encoding for zext.h differs between RV32 and RV64.
>> +# zext_h_32 denotes the RV32 variant.
>> +{
>> + zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
>> + pack 0000100 ..... ..... 100 ..... 0110011 @r
>> +}
>> +xnor 0100000 .......... 100 ..... 0110011 @r
>> +# *** RV32 extra Zbb Standard Extension ***
>> clz 011000 000000 ..... 001 ..... 0010011 @r2
>> cpop 011000 000010 ..... 001 ..... 0010011 @r2
>> ctz 011000 000001 ..... 001 ..... 0010011 @r2
>> @@ -728,23 +742,15 @@ min 0000101 .......... 100 ..... 0110011 @r
>> minu 0000101 .......... 101 ..... 0110011 @r
>> orc_b 001010 000111 ..... 101 ..... 0010011 @r2
>> orn 0100000 .......... 110 ..... 0110011 @r
>> -# The encoding for rev8 differs between RV32 and RV64.
>> -# rev8_32 denotes the RV32 variant.
>> -rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
>> -rol 0110000 .......... 001 ..... 0110011 @r
>> -ror 0110000 .......... 101 ..... 0110011 @r
>> -rori 01100 ............ 101 ..... 0010011 @sh
>> sext_b 011000 000100 ..... 001 ..... 0010011 @r2
>> sext_h 011000 000101 ..... 001 ..... 0010011 @r2
>> -xnor 0100000 .......... 100 ..... 0110011 @r
>> -# The encoding for zext.h differs between RV32 and RV64.
>> -# zext_h_32 denotes the RV32 variant.
>> -zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
>> +# *** RV32 extra Zbkb Standard Extension ***
>> +brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
>> +packh 0000100 .......... 111 ..... 0110011 @r
>> +unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
>> +zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
>>
>> -# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
>> -clzw 0110000 00000 ..... 001 ..... 0011011 @r2
>> -ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
>> -cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
>> +# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
>> # The encoding for rev8 differs between RV32 and RV64.
>> # When executing on RV64, the encoding used in RV32 is an illegal
>> # instruction, so we use different handler functions to differentiate.
>> @@ -755,13 +761,25 @@ rorw 0110000 .......... 101 ..... 0111011 @r
>> # The encoding for zext.h differs between RV32 and RV64.
>> # When executing on RV64, the encoding used in RV32 is an illegal
>> # instruction, so we use different handler functions to differentiate.
>> -zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
>> +{
>> + zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
>> + packw 0000100 ..... ..... 100 ..... 0111011 @r
>> +}
>> +# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
>> +clzw 0110000 00000 ..... 001 ..... 0011011 @r2
>> +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
>> +cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
>>
>> -# *** RV32 Zbc Standard Extension ***
>> +# *** RV32 Zbc/Zbkc Standard Extension ***
>> clmul 0000101 .......... 001 ..... 0110011 @r
>> clmulh 0000101 .......... 011 ..... 0110011 @r
>> +# *** RV32 extra Zbc Standard Extension ***
>> clmulr 0000101 .......... 010 ..... 0110011 @r
>>
>> +# *** RV32 Zbkx Standard Extension ***
>> +xperm4 0010100 .......... 010 ..... 0110011 @r
>> +xperm8 0010100 .......... 100 ..... 0110011 @r
>> +
>> # *** RV32 Zbs Standard Extension ***
>> bclr 0100100 .......... 001 ..... 0110011 @r
>> bclri 01001. ........... 001 ..... 0010011 @sh
>> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
>> index 810431a1d6..a7fb34fb65 100644
>> --- a/target/riscv/insn_trans/trans_rvb.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
>> @@ -1,5 +1,5 @@
>> /*
>> - * RISC-V translation routines for the Zb[abcs] Standard Extension.
>> + * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
>> *
>> * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
>> * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
>> @@ -42,6 +42,18 @@
>> } \
>> } while (0)
>>
>> +#define REQUIRE_ZBKB(ctx) do { \
>> + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbkb) { \
>> + return false; \
>> + } \
>> +} while (0)
>> +
>> +#define REQUIRE_ZBKX(ctx) do { \
>> + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbkx) { \
>> + return false; \
>> + } \
>> +} while (0)
>> +
>> static void gen_clz(TCGv ret, TCGv arg1)
>> {
>> tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
>> @@ -85,19 +97,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
>>
>> static bool trans_andn(DisasContext *ctx, arg_andn *a)
>> {
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_logic(ctx, a, tcg_gen_andc_tl);
>> }
>>
>> static bool trans_orn(DisasContext *ctx, arg_orn *a)
>> {
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_logic(ctx, a, tcg_gen_orc_tl);
>> }
>>
>> static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
>> {
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_logic(ctx, a, tcg_gen_eqv_tl);
>> }
>>
>> @@ -247,7 +259,7 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
>>
>> static bool trans_ror(DisasContext *ctx, arg_ror *a)
>> {
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
>> }
>>
>> @@ -264,7 +276,7 @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
>>
>> static bool trans_rori(DisasContext *ctx, arg_rori *a)
>> {
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
>> tcg_gen_rotri_tl, gen_roriw, NULL);
>> }
>> @@ -289,7 +301,7 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
>>
>> static bool trans_rol(DisasContext *ctx, arg_rol *a)
>> {
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
>> }
>>
>> @@ -301,14 +313,14 @@ static void gen_rev8_32(TCGv ret, TCGv src1)
>> static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
>> {
>> REQUIRE_32BIT(ctx);
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
>> }
>>
>> static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
>> }
>>
>> @@ -403,7 +415,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
>> static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> ctx->ol = MXL_RV32;
>> return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
>> }
>> @@ -411,7 +423,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
>> static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> ctx->ol = MXL_RV32;
>> return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
>> }
>> @@ -419,7 +431,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
>> static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> ctx->ol = MXL_RV32;
>> return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
>> }
>> @@ -483,7 +495,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
>>
>> static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
>> {
>> - REQUIRE_ZBC(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
>> return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
>> }
>>
>> @@ -495,7 +507,7 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
>>
>> static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
>> {
>> - REQUIRE_ZBC(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
>> return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
>> }
>>
>> @@ -504,3 +516,90 @@ static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
>> REQUIRE_ZBC(ctx);
>> return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
>> }
>> +
>> +static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
>> +{
>> + tcg_gen_deposit_tl(ret, src1, src2,
>> + TARGET_LONG_BITS / 2,
>> + TARGET_LONG_BITS / 2);
>> +}
>> +
>> +static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
>> +{
>> + TCGv t = tcg_temp_new();
>> + tcg_gen_ext8u_tl(t, src2);
>> + tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
>> + tcg_temp_free(t);
>> +}
>> +
>> +static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
>> +{
>> + TCGv t = tcg_temp_new();
>> + tcg_gen_ext16s_tl(t, src2);
>> + tcg_gen_deposit_tl(ret, src1, t, 16, 48);
>> + tcg_temp_free(t);
>> +}
>> +
>> +static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
>> +{
>> + REQUIRE_ZBKB(ctx);
>> + TCGv dest = dest_gpr(ctx, a->rd);
>> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> + gen_helper_brev8(dest, src1);
>> + gen_set_gpr(ctx, a->rd, dest);
>> + return true;
>> +}
>> +
>> +static bool trans_pack(DisasContext *ctx, arg_pack *a)
>> +{
>> + REQUIRE_ZBKB(ctx);
>> + return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
>> +}
>> +
>> +static bool trans_packh(DisasContext *ctx, arg_packh *a)
>> +{
>> + REQUIRE_ZBKB(ctx);
>> + return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
>> +}
>> +
>> +static bool trans_packw(DisasContext *ctx, arg_packw *a)
>> +{
>> + REQUIRE_64BIT(ctx);
>> + REQUIRE_ZBKB(ctx);
>> + return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
>> +}
>> +
>> +static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
>> +{
>> + REQUIRE_ZBKB(ctx);
>> + REQUIRE_32BIT(ctx);
>> +
>> + TCGv dest = dest_gpr(ctx, a->rd);
>> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> + gen_helper_unzip(dest, src1);
>> + gen_set_gpr(ctx, a->rd, dest);
>> + return true;
>> +}
>> +
>> +static bool trans_zip(DisasContext *ctx, arg_zip *a)
>> +{
>> + REQUIRE_ZBKB(ctx);
>> + REQUIRE_32BIT(ctx);
>> + TCGv dest = dest_gpr(ctx, a->rd);
>> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> + gen_helper_zip(dest, src1);
>> + gen_set_gpr(ctx, a->rd, dest);
>> + return true;
>> +}
>> +
>> +static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
>> +{
>> + REQUIRE_ZBKX(ctx);
>> + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
>> +}
>> +
>> +static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
>> +{
>> + REQUIRE_ZBKX(ctx);
>> + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
>> +}
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index 615048ec87..f3e37ddcd2 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -525,6 +525,13 @@ EX_SH(12)
>> } \
>> } while (0)
>>
>> +#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
>> + if (!RISCV_CPU(ctx->cs)->cfg.ext_##A && \
>> + !RISCV_CPU(ctx->cs)->cfg.ext_##B) { \
>> + return false; \
>> + } \
>> +} while (0)
>> +
>> static int ex_rvc_register(DisasContext *ctx, int reg)
>> {
>> return 8 + reg;
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
@ 2022-01-18 8:21 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-18 8:21 UTC (permalink / raw)
To: Alistair Francis
Cc: Richard Henderson, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
lazyparser, luruibo2000, lustrew
在 2022/1/18 下午12:40, Alistair Francis 写道:
> On Tue, Jan 11, 2022 at 1:56 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> - reuse partial instructions of Zbb/Zbc extensions
>> - add brev8, packh, unzip, zip, etc.
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>> target/riscv/bitmanip_helper.c | 74 ++++++++++++++
>> target/riscv/helper.h | 5 +
>> target/riscv/insn32.decode | 52 ++++++----
>> target/riscv/insn_trans/trans_rvb.c.inc | 127 +++++++++++++++++++++---
>> target/riscv/translate.c | 7 ++
>> 5 files changed, 234 insertions(+), 31 deletions(-)
>>
>> diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
>> index f1b5e5549f..dc3dcf685a 100644
>> --- a/target/riscv/bitmanip_helper.c
>> +++ b/target/riscv/bitmanip_helper.c
>> @@ -49,3 +49,77 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
>>
>> return result;
>> }
>> +
>> +static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
>> +{
>> + return ((x & mask) << shift) | ((x & ~mask) >> shift);
>> +}
>> +
>> +target_ulong HELPER(brev8)(target_ulong rs1)
>> +{
>> + target_ulong x = rs1;
>> + x = do_swap(x, 0x5555555555555555ull, 1);
>> + x = do_swap(x, 0x3333333333333333ull, 2);
>> + x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
>> + return x;
>> +}
>> +
>> +static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
>> + uint32_t sz_log2)
>> +{
>> + target_ulong r = 0;
>> + target_ulong sz = 1LL << sz_log2;
>> + target_ulong mask = (1LL << sz) - 1;
>> + for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
>> + target_ulong pos = ((rs2 >> i) & mask) << sz_log2;
>> + if (pos < sizeof(target_ulong) * 8) {
>> + r |= ((rs1 >> pos) & mask) << i;
>> + }
>> + }
>> + return r;
>> +}
>> +
>> +target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
>> +{
>> + return do_xperm(rs1, rs2, 2);
>> +}
>> +
>> +target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
>> +{
>> + return do_xperm(rs1, rs2, 3);
>> +}
>> +
>> +static const uint64_t shuf_masks[] = {
>> + dup_const(MO_8, 0x44),
>> + dup_const(MO_8, 0x30),
>> + dup_const(MO_16, 0x0f00),
>> + dup_const(MO_32, 0xff0000)
>> +};
>> +
>> +static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
>> + uint64_t maskR, int shift)
>> +{
>> + target_ulong x = src & ~(maskL | maskR);
>> + x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
>> + return x;
>> +}
>> +
>> +target_ulong HELPER(unzip)(target_ulong rs1)
>> +{
>> + target_ulong x = rs1;
>> + x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
>> + x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
>> + x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
>> + x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
>> + return x;
>> +}
>> +
>> +target_ulong HELPER(zip)(target_ulong rs1)
>> +{
>> + target_ulong x = rs1;
>> + x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
>> + x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
>> + x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
>> + x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
>> + return x;
>> +}
>> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
>> index 6cf6d6ce98..2bd6ac8280 100644
>> --- a/target/riscv/helper.h
>> +++ b/target/riscv/helper.h
>> @@ -66,6 +66,11 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
>> /* Bitmanip */
>> DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
>> DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
>> +DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
>> +DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
>>
>> /* Floating Point - Half Precision */
>> DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
>> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
>> index 5bbedc254c..7491b2d562 100644
>> --- a/target/riscv/insn32.decode
>> +++ b/target/riscv/insn32.decode
>> @@ -717,8 +717,22 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r
>> sh3add_uw 0010000 .......... 110 ..... 0111011 @r
>> slli_uw 00001 ............ 001 ..... 0011011 @sh
>>
>> -# *** RV32 Zbb Standard Extension ***
>> +# *** RV32 Zbb/Zbkb Standard Extension ***
>> andn 0100000 .......... 111 ..... 0110011 @r
>> +rol 0110000 .......... 001 ..... 0110011 @r
>> +ror 0110000 .......... 101 ..... 0110011 @r
>> +rori 01100 ............ 101 ..... 0010011 @sh
>> +# The encoding for rev8 differs between RV32 and RV64.
>> +# rev8_32 denotes the RV32 variant.
>> +rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
> Why move these?
>
> Alistair
>
I mov these to divide instructions for only zbb (as RV32 extra Zbb
Standard Extension) and the instructions for both zbb and zbkb( as RV32
Zbb/Zbkb Standard Extension) .
Regards,
Weiwei Li
>> +# The encoding for zext.h differs between RV32 and RV64.
>> +# zext_h_32 denotes the RV32 variant.
>> +{
>> + zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
>> + pack 0000100 ..... ..... 100 ..... 0110011 @r
>> +}
>> +xnor 0100000 .......... 100 ..... 0110011 @r
>> +# *** RV32 extra Zbb Standard Extension ***
>> clz 011000 000000 ..... 001 ..... 0010011 @r2
>> cpop 011000 000010 ..... 001 ..... 0010011 @r2
>> ctz 011000 000001 ..... 001 ..... 0010011 @r2
>> @@ -728,23 +742,15 @@ min 0000101 .......... 100 ..... 0110011 @r
>> minu 0000101 .......... 101 ..... 0110011 @r
>> orc_b 001010 000111 ..... 101 ..... 0010011 @r2
>> orn 0100000 .......... 110 ..... 0110011 @r
>> -# The encoding for rev8 differs between RV32 and RV64.
>> -# rev8_32 denotes the RV32 variant.
>> -rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
>> -rol 0110000 .......... 001 ..... 0110011 @r
>> -ror 0110000 .......... 101 ..... 0110011 @r
>> -rori 01100 ............ 101 ..... 0010011 @sh
>> sext_b 011000 000100 ..... 001 ..... 0010011 @r2
>> sext_h 011000 000101 ..... 001 ..... 0010011 @r2
>> -xnor 0100000 .......... 100 ..... 0110011 @r
>> -# The encoding for zext.h differs between RV32 and RV64.
>> -# zext_h_32 denotes the RV32 variant.
>> -zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
>> +# *** RV32 extra Zbkb Standard Extension ***
>> +brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
>> +packh 0000100 .......... 111 ..... 0110011 @r
>> +unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
>> +zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
>>
>> -# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
>> -clzw 0110000 00000 ..... 001 ..... 0011011 @r2
>> -ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
>> -cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
>> +# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
>> # The encoding for rev8 differs between RV32 and RV64.
>> # When executing on RV64, the encoding used in RV32 is an illegal
>> # instruction, so we use different handler functions to differentiate.
>> @@ -755,13 +761,25 @@ rorw 0110000 .......... 101 ..... 0111011 @r
>> # The encoding for zext.h differs between RV32 and RV64.
>> # When executing on RV64, the encoding used in RV32 is an illegal
>> # instruction, so we use different handler functions to differentiate.
>> -zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
>> +{
>> + zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
>> + packw 0000100 ..... ..... 100 ..... 0111011 @r
>> +}
>> +# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
>> +clzw 0110000 00000 ..... 001 ..... 0011011 @r2
>> +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
>> +cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
>>
>> -# *** RV32 Zbc Standard Extension ***
>> +# *** RV32 Zbc/Zbkc Standard Extension ***
>> clmul 0000101 .......... 001 ..... 0110011 @r
>> clmulh 0000101 .......... 011 ..... 0110011 @r
>> +# *** RV32 extra Zbc Standard Extension ***
>> clmulr 0000101 .......... 010 ..... 0110011 @r
>>
>> +# *** RV32 Zbkx Standard Extension ***
>> +xperm4 0010100 .......... 010 ..... 0110011 @r
>> +xperm8 0010100 .......... 100 ..... 0110011 @r
>> +
>> # *** RV32 Zbs Standard Extension ***
>> bclr 0100100 .......... 001 ..... 0110011 @r
>> bclri 01001. ........... 001 ..... 0010011 @sh
>> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
>> index 810431a1d6..a7fb34fb65 100644
>> --- a/target/riscv/insn_trans/trans_rvb.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
>> @@ -1,5 +1,5 @@
>> /*
>> - * RISC-V translation routines for the Zb[abcs] Standard Extension.
>> + * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
>> *
>> * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
>> * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
>> @@ -42,6 +42,18 @@
>> } \
>> } while (0)
>>
>> +#define REQUIRE_ZBKB(ctx) do { \
>> + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbkb) { \
>> + return false; \
>> + } \
>> +} while (0)
>> +
>> +#define REQUIRE_ZBKX(ctx) do { \
>> + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbkx) { \
>> + return false; \
>> + } \
>> +} while (0)
>> +
>> static void gen_clz(TCGv ret, TCGv arg1)
>> {
>> tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
>> @@ -85,19 +97,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
>>
>> static bool trans_andn(DisasContext *ctx, arg_andn *a)
>> {
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_logic(ctx, a, tcg_gen_andc_tl);
>> }
>>
>> static bool trans_orn(DisasContext *ctx, arg_orn *a)
>> {
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_logic(ctx, a, tcg_gen_orc_tl);
>> }
>>
>> static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
>> {
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_logic(ctx, a, tcg_gen_eqv_tl);
>> }
>>
>> @@ -247,7 +259,7 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
>>
>> static bool trans_ror(DisasContext *ctx, arg_ror *a)
>> {
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
>> }
>>
>> @@ -264,7 +276,7 @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
>>
>> static bool trans_rori(DisasContext *ctx, arg_rori *a)
>> {
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
>> tcg_gen_rotri_tl, gen_roriw, NULL);
>> }
>> @@ -289,7 +301,7 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
>>
>> static bool trans_rol(DisasContext *ctx, arg_rol *a)
>> {
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
>> }
>>
>> @@ -301,14 +313,14 @@ static void gen_rev8_32(TCGv ret, TCGv src1)
>> static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
>> {
>> REQUIRE_32BIT(ctx);
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
>> }
>>
>> static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
>> }
>>
>> @@ -403,7 +415,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
>> static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> ctx->ol = MXL_RV32;
>> return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
>> }
>> @@ -411,7 +423,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
>> static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> ctx->ol = MXL_RV32;
>> return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
>> }
>> @@ -419,7 +431,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
>> static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - REQUIRE_ZBB(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
>> ctx->ol = MXL_RV32;
>> return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
>> }
>> @@ -483,7 +495,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
>>
>> static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
>> {
>> - REQUIRE_ZBC(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
>> return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
>> }
>>
>> @@ -495,7 +507,7 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
>>
>> static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
>> {
>> - REQUIRE_ZBC(ctx);
>> + REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
>> return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
>> }
>>
>> @@ -504,3 +516,90 @@ static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
>> REQUIRE_ZBC(ctx);
>> return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
>> }
>> +
>> +static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
>> +{
>> + tcg_gen_deposit_tl(ret, src1, src2,
>> + TARGET_LONG_BITS / 2,
>> + TARGET_LONG_BITS / 2);
>> +}
>> +
>> +static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
>> +{
>> + TCGv t = tcg_temp_new();
>> + tcg_gen_ext8u_tl(t, src2);
>> + tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
>> + tcg_temp_free(t);
>> +}
>> +
>> +static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
>> +{
>> + TCGv t = tcg_temp_new();
>> + tcg_gen_ext16s_tl(t, src2);
>> + tcg_gen_deposit_tl(ret, src1, t, 16, 48);
>> + tcg_temp_free(t);
>> +}
>> +
>> +static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
>> +{
>> + REQUIRE_ZBKB(ctx);
>> + TCGv dest = dest_gpr(ctx, a->rd);
>> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> + gen_helper_brev8(dest, src1);
>> + gen_set_gpr(ctx, a->rd, dest);
>> + return true;
>> +}
>> +
>> +static bool trans_pack(DisasContext *ctx, arg_pack *a)
>> +{
>> + REQUIRE_ZBKB(ctx);
>> + return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
>> +}
>> +
>> +static bool trans_packh(DisasContext *ctx, arg_packh *a)
>> +{
>> + REQUIRE_ZBKB(ctx);
>> + return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
>> +}
>> +
>> +static bool trans_packw(DisasContext *ctx, arg_packw *a)
>> +{
>> + REQUIRE_64BIT(ctx);
>> + REQUIRE_ZBKB(ctx);
>> + return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
>> +}
>> +
>> +static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
>> +{
>> + REQUIRE_ZBKB(ctx);
>> + REQUIRE_32BIT(ctx);
>> +
>> + TCGv dest = dest_gpr(ctx, a->rd);
>> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> + gen_helper_unzip(dest, src1);
>> + gen_set_gpr(ctx, a->rd, dest);
>> + return true;
>> +}
>> +
>> +static bool trans_zip(DisasContext *ctx, arg_zip *a)
>> +{
>> + REQUIRE_ZBKB(ctx);
>> + REQUIRE_32BIT(ctx);
>> + TCGv dest = dest_gpr(ctx, a->rd);
>> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> + gen_helper_zip(dest, src1);
>> + gen_set_gpr(ctx, a->rd, dest);
>> + return true;
>> +}
>> +
>> +static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
>> +{
>> + REQUIRE_ZBKX(ctx);
>> + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
>> +}
>> +
>> +static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
>> +{
>> + REQUIRE_ZBKX(ctx);
>> + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
>> +}
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index 615048ec87..f3e37ddcd2 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -525,6 +525,13 @@ EX_SH(12)
>> } \
>> } while (0)
>>
>> +#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
>> + if (!RISCV_CPU(ctx->cs)->cfg.ext_##A && \
>> + !RISCV_CPU(ctx->cs)->cfg.ext_##B) { \
>> + return false; \
>> + } \
>> +} while (0)
>> +
>> static int ex_rvc_register(DisasContext *ctx, int reg)
>> {
>> return 8 + reg;
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 0/7] support subsets of scalar crypto extension
2022-01-18 4:41 ` Alistair Francis
@ 2022-01-18 8:24 ` Weiwei Li
-1 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-18 8:24 UTC (permalink / raw)
To: Alistair Francis
Cc: lazyparser, open list:RISC-V, lustrew, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, luruibo2000, Alistair Francis
在 2022/1/18 下午12:41, Alistair Francis 写道:
> On Tue, Jan 11, 2022 at 1:54 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> This patchset implements RISC-V scalar crypto extension v1.0.0 version instructions.
>> Partial instructions are reused from B-extension.
>>
>> Specification:
>> https://github.com/riscv/riscv-crypto
>>
>> The port is available here:
>> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4
>>
>> To test rvk implementation, specify cpu argument with 'zks=true,zkn=true'
>> or
>> "zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true"
>> to enable K-extension support. This implementation can pass the ACT tests
>> for K with our extended act support for qemu (available at
>> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4-with-act)
>>
>> v4:
>> * drop "x-" in exposed properties
>> * delete unrelated changes
>>
>> v3:
>> * add extension check for SEED csr access
>>
>> v2:
>> * optimize implementation for brev8, xperm, zip, unzip
>> * use aes related sbox array from crypto/aes.h
>> * move sm4_sbox to crypto/sm4.c, and share it with target/arm
>>
>> Weiwei Li (7):
>> target/riscv: rvk: add cfg properties for zbk* and zk*
>> target/riscv: rvk: add implementation of instructions for Zbk*
>> crypto include/crypto target/arm: move sm4_sbox to crypto
>> target/riscv: rvk: add implementation of instructions for Zk*
>> target/riscv: rvk: add CSR support for Zkr
>> disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
>> target/riscv: rvk: expose zbk* and zk* properties
> Thanks for the patches!
>
> Overall this looks good, just some small comments on the individual patches.
>
> For the next version do you mind splitting the patches up a little bit
> more? That will make it easier and faster to review
>
> Alistair
>
Thanks for your comments. Sorry for the big patches. I'll divide them.
Regards,
Weiwei Li
>> crypto/meson.build | 1 +
>> crypto/sm4.c | 49 +++
>> disas/riscv.c | 170 +++++++++
>> include/crypto/sm4.h | 6 +
>> target/arm/crypto_helper.c | 36 +-
>> target/riscv/bitmanip_helper.c | 74 ++++
>> target/riscv/cpu.c | 37 ++
>> target/riscv/cpu.h | 13 +
>> target/riscv/cpu_bits.h | 9 +
>> target/riscv/crypto_helper.c | 446 ++++++++++++++++++++++
>> target/riscv/csr.c | 74 ++++
>> target/riscv/helper.h | 42 +++
>> target/riscv/insn32.decode | 94 ++++-
>> target/riscv/insn_trans/trans_rvb.c.inc | 127 ++++++-
>> target/riscv/insn_trans/trans_rvk.c.inc | 467 ++++++++++++++++++++++++
>> target/riscv/meson.build | 3 +-
>> target/riscv/pmp.h | 8 +-
>> target/riscv/translate.c | 8 +
>> 18 files changed, 1594 insertions(+), 70 deletions(-)
>> create mode 100644 crypto/sm4.c
>> create mode 100644 include/crypto/sm4.h
>> create mode 100644 target/riscv/crypto_helper.c
>> create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>>
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v4 0/7] support subsets of scalar crypto extension
@ 2022-01-18 8:24 ` Weiwei Li
0 siblings, 0 replies; 40+ messages in thread
From: Weiwei Li @ 2022-01-18 8:24 UTC (permalink / raw)
To: Alistair Francis
Cc: Richard Henderson, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
lazyparser, luruibo2000, lustrew
在 2022/1/18 下午12:41, Alistair Francis 写道:
> On Tue, Jan 11, 2022 at 1:54 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> This patchset implements RISC-V scalar crypto extension v1.0.0 version instructions.
>> Partial instructions are reused from B-extension.
>>
>> Specification:
>> https://github.com/riscv/riscv-crypto
>>
>> The port is available here:
>> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4
>>
>> To test rvk implementation, specify cpu argument with 'zks=true,zkn=true'
>> or
>> "zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true"
>> to enable K-extension support. This implementation can pass the ACT tests
>> for K with our extended act support for qemu (available at
>> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v4-with-act)
>>
>> v4:
>> * drop "x-" in exposed properties
>> * delete unrelated changes
>>
>> v3:
>> * add extension check for SEED csr access
>>
>> v2:
>> * optimize implementation for brev8, xperm, zip, unzip
>> * use aes related sbox array from crypto/aes.h
>> * move sm4_sbox to crypto/sm4.c, and share it with target/arm
>>
>> Weiwei Li (7):
>> target/riscv: rvk: add cfg properties for zbk* and zk*
>> target/riscv: rvk: add implementation of instructions for Zbk*
>> crypto include/crypto target/arm: move sm4_sbox to crypto
>> target/riscv: rvk: add implementation of instructions for Zk*
>> target/riscv: rvk: add CSR support for Zkr
>> disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
>> target/riscv: rvk: expose zbk* and zk* properties
> Thanks for the patches!
>
> Overall this looks good, just some small comments on the individual patches.
>
> For the next version do you mind splitting the patches up a little bit
> more? That will make it easier and faster to review
>
> Alistair
>
Thanks for your comments. Sorry for the big patches. I'll divide them.
Regards,
Weiwei Li
>> crypto/meson.build | 1 +
>> crypto/sm4.c | 49 +++
>> disas/riscv.c | 170 +++++++++
>> include/crypto/sm4.h | 6 +
>> target/arm/crypto_helper.c | 36 +-
>> target/riscv/bitmanip_helper.c | 74 ++++
>> target/riscv/cpu.c | 37 ++
>> target/riscv/cpu.h | 13 +
>> target/riscv/cpu_bits.h | 9 +
>> target/riscv/crypto_helper.c | 446 ++++++++++++++++++++++
>> target/riscv/csr.c | 74 ++++
>> target/riscv/helper.h | 42 +++
>> target/riscv/insn32.decode | 94 ++++-
>> target/riscv/insn_trans/trans_rvb.c.inc | 127 ++++++-
>> target/riscv/insn_trans/trans_rvk.c.inc | 467 ++++++++++++++++++++++++
>> target/riscv/meson.build | 3 +-
>> target/riscv/pmp.h | 8 +-
>> target/riscv/translate.c | 8 +
>> 18 files changed, 1594 insertions(+), 70 deletions(-)
>> create mode 100644 crypto/sm4.c
>> create mode 100644 include/crypto/sm4.h
>> create mode 100644 target/riscv/crypto_helper.c
>> create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>>
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 40+ messages in thread
end of thread, other threads:[~2022-01-18 8:30 UTC | newest]
Thread overview: 40+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-11 3:51 [PATCH v4 0/7] support subsets of scalar crypto extension Weiwei Li
2022-01-11 3:51 ` Weiwei Li
2022-01-11 3:51 ` [PATCH v4 1/7] target/riscv: rvk: add cfg properties for zbk* and zk* Weiwei Li
2022-01-11 3:51 ` Weiwei Li
2022-01-11 3:51 ` [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk* Weiwei Li
2022-01-11 3:51 ` Weiwei Li
2022-01-18 4:40 ` Alistair Francis
2022-01-18 4:40 ` Alistair Francis
2022-01-18 8:21 ` Weiwei Li
2022-01-18 8:21 ` Weiwei Li
2022-01-11 3:51 ` [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto Weiwei Li
2022-01-11 3:51 ` Weiwei Li
2022-01-17 23:28 ` Alistair Francis
2022-01-17 23:28 ` Alistair Francis
2022-01-18 1:09 ` Weiwei Li
2022-01-18 1:09 ` Weiwei Li
2022-01-11 3:51 ` [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk* Weiwei Li
2022-01-11 3:51 ` Weiwei Li
2022-01-18 4:21 ` Alistair Francis
2022-01-18 4:21 ` Alistair Francis
2022-01-18 8:08 ` Weiwei Li
2022-01-18 8:08 ` Weiwei Li
2022-01-11 3:51 ` [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr Weiwei Li
2022-01-11 3:51 ` Weiwei Li
2022-01-18 4:36 ` Alistair Francis
2022-01-18 4:36 ` Alistair Francis
2022-01-18 8:14 ` Weiwei Li
2022-01-18 8:14 ` Weiwei Li
2022-01-11 3:51 ` [PATCH v4 6/7] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions Weiwei Li
2022-01-11 3:51 ` Weiwei Li
2022-01-11 3:51 ` [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties Weiwei Li
2022-01-11 3:51 ` Weiwei Li
2022-01-18 4:23 ` Alistair Francis
2022-01-18 4:23 ` Alistair Francis
2022-01-18 8:09 ` Weiwei Li
2022-01-18 8:09 ` Weiwei Li
2022-01-18 4:41 ` [PATCH v4 0/7] support subsets of scalar crypto extension Alistair Francis
2022-01-18 4:41 ` Alistair Francis
2022-01-18 8:24 ` Weiwei Li
2022-01-18 8:24 ` Weiwei Li
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