Re: [PATCH] mips/loongson64: using __fast_iob implement __wbflush() instead of sync

["Jiaxun Yang" <jiaxun.yang@flygoat.com>]

Hi Jingfeng,
I'd suggest you not to mess with barriers on Loongson.
It's a hell.

Also Loongson had changed semantics of sync/synci many times.
They got redefined and swapped. So the present way is just the safest way.

Thanks.

- Jiaxun

在2021年12月4日十二月 下午12:00，suijingfeng写道：
> 1) loongson's cpu(ls3a3000, ls3a4000, ls3a5000) have uncache store buffers
>     which is for uncache accleration.
>
>     Uncached Accelerated is the name under which the R10000 introduced
>     a cache mode that uses the CPU's write buffer to combine writes
>     but that otherwise is uncached.
>
>     wbflush is mean to empty data gathered in the uncache store buffers
>     within the CPU.
>
>  2) The SYNC instruction in R10000
>
>     A SYNC instruction is not prevented from graduating if the uncached
>     buffer contains any uncached accelerated stores[1].
>
>  3) wbflush() implementation of IDT CPU.
>
>     IDT CPUs enforce strict write priority (all pending writes retired
>     to memory before main memory is read). Thus, implementing wbflush()
>     is as simple as implementing an uncached load.
>
>     for loongson's cpu, __wbflush should also be implemented with
>     __fast_iob not sync.
>
> [1] 
> https://www.ele.uva.es/~jesman/BigSeti/ftp/Microprocesadores/MIPS/t5.ver.2.0.book.pdf
>
> Signed-off-by: suijingfeng <suijingfeng@loongson.cn>
> ---
>  arch/mips/loongson64/Makefile  |  1 +
>  arch/mips/loongson64/setup.c   | 17 -----------------
>  arch/mips/loongson64/smp.c     |  6 +++---
>  arch/mips/loongson64/wbflush.c | 28 ++++++++++++++++++++++++++++
>  4 files changed, 32 insertions(+), 20 deletions(-)
>  create mode 100644 arch/mips/loongson64/wbflush.c
>
> diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
> index e806280bbb85..ad00d92c2871 100644
> --- a/arch/mips/loongson64/Makefile
> +++ b/arch/mips/loongson64/Makefile
> @@ -12,3 +12,4 @@ obj-$(CONFIG_SUSPEND) += pm.o
>  obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o
>  obj-$(CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION) += cpucfg-emul.o
>  obj-$(CONFIG_SYSFS) += boardinfo.o
> +obj-$(CONFIG_CPU_HAS_WB) += wbflush.o
> diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c
> index 6fe3ffffcaa6..cb10d14da433 100644
> --- a/arch/mips/loongson64/setup.c
> +++ b/arch/mips/loongson64/setup.c
> @@ -3,10 +3,7 @@
>   * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
>   * Author: Fuxin Zhang, zhangfx@lemote.com
>   */
> -#include <linux/export.h>
>  #include <linux/init.h>
> -
> -#include <asm/wbflush.h>
>  #include <asm/bootinfo.h>
>  #include <linux/libfdt.h>
>  #include <linux/of_fdt.h>
> @@ -17,20 +14,6 @@
> 
>  void *loongson_fdt_blob;
> 
> -static void wbflush_loongson(void)
> -{
> -	asm(".set\tpush\n\t"
> -	    ".set\tnoreorder\n\t"
> -	    ".set mips3\n\t"
> -	    "sync\n\t"
> -	    "nop\n\t"
> -	    ".set\tpop\n\t"
> -	    ".set mips0\n\t");
> -}
> -
> -void (*__wbflush)(void) = wbflush_loongson;
> -EXPORT_SYMBOL(__wbflush);
> -
>  void __init plat_mem_setup(void)
>  {
>  	if (loongson_fdt_blob)
> diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
> index 660e1de4412a..0d9f249c95f9 100644
> --- a/arch/mips/loongson64/smp.c
> +++ b/arch/mips/loongson64/smp.c
> @@ -42,13 +42,13 @@ static uint32_t core0_c0count[NR_CPUS];
>  #define loongson3_ipi_write32(action, addr)	\
>  	do {					\
>  		writel(action, addr);		\
> -		__wbflush();			\
> +		wbflush();			\
>  	} while (0)
>  /* write a 64bit value to ipi register */
>  #define loongson3_ipi_write64(action, addr)	\
>  	do {					\
>  		writeq(action, addr);		\
> -		__wbflush();			\
> +		wbflush();			\
>  	} while (0)
> 
>  static u32 (*ipi_read_clear)(int cpu);
> @@ -418,7 +418,7 @@ static irqreturn_t loongson3_ipi_interrupt(int irq, 
> void *dev_id)
>  		c0count = c0count ? c0count : 1;
>  		for (i = 1; i < nr_cpu_ids; i++)
>  			core0_c0count[i] = c0count;
> -		__wbflush(); /* Let others see the result ASAP */
> +		wbflush(); /* Let others see the result ASAP */
>  	}
> 
>  	return IRQ_HANDLED;
> diff --git a/arch/mips/loongson64/wbflush.c b/arch/mips/loongson64/wbflush.c
> new file mode 100644
> index 000000000000..49f0e4c53196
> --- /dev/null
> +++ b/arch/mips/loongson64/wbflush.c
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License.  See the file "COPYING" in the main directory of this archive
> + * for more details.
> + *
> + * Copyright (C) 2021 suijingfeng@loongson.cn
> + */
> +#include <linux/export.h>
> +#include <linux/init.h>
> +#include <asm/wbflush.h>
> +#include <asm/barrier.h>
> +
> +#ifdef CONFIG_CPU_HAS_WB
> +
> +/*
> + * I/O ASIC systems use a standard writeback buffer that gets flushed
> + * upon an uncached read.
> + */
> +static void wbflush_mips(void)
> +{
> +	__fast_iob();
> +}
> +
> +void (*__wbflush)(void) = wbflush_mips;
> +EXPORT_SYMBOL(__wbflush);
> +
> +#endif
> -- 
> 2.25.1

-- 
- Jiaxun