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(p200300ea8f08450058dae5ebc8671a2c.dip0.t-ipconnect.de. [2003:ea:8f08:4500:58da:e5eb:c867:1a2c]) by smtp.googlemail.com with ESMTPSA id x18sm306969wrw.19.2021.09.01.12.07.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Sep 2021 12:07:49 -0700 (PDT) To: Johannes Berg , =?UTF-8?Q?Pali_Roh=c3=a1r?= , =?UTF-8?Q?Jonas_Dre=c3=9fler?= Cc: Andy Shevchenko , Amitkumar Karwar , Ganapathi Bhat , Xinming Hu , Kalle Valo , "David S. Miller" , Jakub Kicinski , Tsuchiya Yuto , "open list:TI WILINK WIRELES..." , netdev , Linux Kernel Mailing List , linux-pci , Maximilian Luz , Andy Shevchenko , Bjorn Helgaas References: <20210830123704.221494-1-verdre@v0yd.nl> <20210830123704.221494-2-verdre@v0yd.nl> <7e38931e-2f1c-066e-088e-b27b56c1245c@v0yd.nl> <20210901155110.xgje2qrtq65loawh@pali> <985049b8-bad7-6f18-c94f-368059dd6f95@gmail.com> From: Heiner Kallweit Subject: Re: [PATCH 1/2] mwifiex: Use non-posted PCI register writes Message-ID: Date: Wed, 1 Sep 2021 21:07:41 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org On 01.09.2021 19:07, Johannes Berg wrote: > On Wed, 2021-09-01 at 18:51 +0200, Heiner Kallweit wrote: >> On 01.09.2021 17:51, Pali Rohár wrote: >>> On Wednesday 01 September 2021 16:01:54 Jonas Dreßler wrote: >>>> On 8/30/21 2:49 PM, Andy Shevchenko wrote: >>>>> On Mon, Aug 30, 2021 at 3:38 PM Jonas Dreßler wrote: >>>>>> >>>>>> On the 88W8897 card it's very important the TX ring write pointer is >>>>>> updated correctly to its new value before setting the TX ready >>>>>> interrupt, otherwise the firmware appears to crash (probably because >>>>>> it's trying to DMA-read from the wrong place). >>>>>> >> >> This sounds somehow like the typical case where you write DMA descriptors >> and then ring the doorbell. This normally requires a dma_wmb(). >> Maybe something like that is missing here? > > But it looks like this "TX ring write pointer" is actually the register? > > However, I would agree that doing it in mwifiex_write_reg() is possibly > too big a hammer - could be done only for reg->tx_wrptr, not all the > registers? > > Actually, can two writes actually cross on PCI? > > johannes > In case we're talking about the following piece of code both register writes are IOMEM writes that are ordered. Maybe the writes arrive properly ordered but some chip-internal delays cause the issue? Then the read-back would be something like an ordinary udelay()? Instead of always reading back register writes, is it sufficient to read an arbitrary register after mwifiex_write_reg(adapter, reg->tx_wrptr ? /* Write the TX ring write pointer in to reg->tx_wrptr */ if (mwifiex_write_reg(adapter, reg->tx_wrptr, card->txbd_wrptr | rx_val)) { mwifiex_dbg(adapter, ERROR, "SEND DATA: failed to write reg->tx_wrptr\n"); ret = -1; goto done_unmap; } if ((mwifiex_pcie_txbd_not_full(card)) && tx_param->next_pkt_len) { /* have more packets and TxBD still can hold more */ mwifiex_dbg(adapter, DATA, "SEND DATA: delay dnld-rdy interrupt.\n"); adapter->data_sent = false; } else { /* Send the TX ready interrupt */ if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, CPU_INTR_DNLD_RDY)) {