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* [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-07-16 23:28 ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:28 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Hi all,

over the last few days I've taken on the job to give the blk-ctrl driver
initially worked on by Peng Fan another spin. What I've come up with now
looks quite a bit different, as the power sequencing shared between the
blk-ctrls and the GPC is not really feasible to model with a strict
hierarchy of power domains. In my design the blk-ctrl driver is the
instance driving the sequence for those power domains where a blk-ctrl
is part of the picture.

For those that aren't familiar with the power domain architecture on the
i.MX8M*, here's a short overview, to hopefully make it easier to review
this series. The i.MX8M* reuses the GPCv2 (General Power Controller)IP
block, already known from the i.MX7. On the i.MX7 all power domains
were independent and all the reset and bus isolation sequencing was handled
in hardware by the GPC. Software only needed to request power up/down for
the domain and things mostly happened behind the scenes. On i.MX8M* things
got more complex, as there are now nested power domains and coupling of
the data busses is handled by AMBA domain bridges (ADB), which aren't
sequenced by the GPC hardware, but have handshake requests/acks wired
up to a register in the GPC that needs to be handled by software. Due to
hardware issues some of the reset sequencing also needs to be handled by
software, as the GPC isn't always able to properly trigger the SRC reset
for the peripherals inside the power domains.

Generally with all those nested domains there exists a outer *MIX
(e.g. VPUMIX, DISPMIX) domain that contains the ADB and the BLK_CTRL.
Handshake with the ADB can only happen after the *MIX domain is powered
up and some domain specific initialization in the BLK_CTRL is done. The
ADB is connected to a bus clock from CCM that needs to be enabled for
the ADB to work. Also there might be additional resets and clock gates
for the ADB in the BLK_CTRL MMIO region, which is also only accessible
after the *MIX domain is powered up.
Some peripherals are directly located in the *MIX domain, but others
are placed in inner domains located in the *MIX domain. In order to
power up those nested domains the *MIX domain must already be powered up
and the ADB handshake must be finished. Reset is handled via the BLK_CTRL,
instead of the SRC, which contains resets and clock gates for the
peripherals.
The general flow for those inner domains is:
1. Assert reset and ungate clocks in BLK_CTRL to allow reset to propagate
2. Request power up at the GPC
3. Deassert reset

Failing to meet the ADB handshake and/or reset sequencing requirements
will generally lead to system hangs (not necessarily at the point where
the sequence is violated). The blk-ctrl driver as implemented hides this
behind virtual power domains. Peripherals don't need to care whether they
are located directly inside the *MIX domain or in a nested domain, they
all just use the power domains exposed by the BLK_CTRL driver, which
handles the sequencing requiments internally.

Currently this series implements both the VPU and DISP blk-ctrls for the
i.MX8MM SoC, but I'm quite confident that the design is sound and can be
trivially extended for the other i.MX8M* SoCs. On my personal TODO list
is the conversion of the i.MX8MQ VPU blk-ctrl to the new model, which
should finally allow us to drive the G1 and G2 VPUs independently. After
that I'm going to look at the i.MX8MP, as this is a current focus of my
work and has even more blk-ctrl instances. But before moving on to those,
I would like to gather some feedback and testing on this series.

I will also provide a branch with those patches and the WIP VPU and
display patches I used to test this. But that will have to wait for next
week, as it's getting pretty late here.

Regards,
Lucas

Frieder Schrempf (1):
  arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core

Lucas Stach (14):
  Revert "soc: imx: gpcv2: move reset assert after requesting domain
    power up"
  soc: imx: gpcv2: add lockdep annotation
  soc: imx: gpcv2: add domain option to keep domain clocks enabled
  soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
  dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
  dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains
  soc: imx: add i.MX8M blk-ctrl driver
  dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
  dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains
  soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
  arm64: dts: imx8mm: add GPC node
  arm64: dts: imx8mm: put USB controllers into power-domains
  arm64: dts: imx8mm: add VPU blk-ctrl
  arm64: dts: imx8mm: add DISP blk-ctrl

Marek Vasut (2):
  soc: imx: gpcv2: Turn domain->pgc into bitfield
  soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU
    domain

 .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     |  97 ++++
 .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      |  79 +++
 arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 180 +++++++
 drivers/soc/imx/Makefile                      |   1 +
 drivers/soc/imx/gpcv2.c                       |  99 ++--
 drivers/soc/imx/imx8m-blk-ctrl.c              | 464 ++++++++++++++++++
 include/dt-bindings/power/imx8mm-power.h      |   9 +
 7 files changed, 888 insertions(+), 41 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
 create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c

-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-07-16 23:28 ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:28 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Hi all,

over the last few days I've taken on the job to give the blk-ctrl driver
initially worked on by Peng Fan another spin. What I've come up with now
looks quite a bit different, as the power sequencing shared between the
blk-ctrls and the GPC is not really feasible to model with a strict
hierarchy of power domains. In my design the blk-ctrl driver is the
instance driving the sequence for those power domains where a blk-ctrl
is part of the picture.

For those that aren't familiar with the power domain architecture on the
i.MX8M*, here's a short overview, to hopefully make it easier to review
this series. The i.MX8M* reuses the GPCv2 (General Power Controller)IP
block, already known from the i.MX7. On the i.MX7 all power domains
were independent and all the reset and bus isolation sequencing was handled
in hardware by the GPC. Software only needed to request power up/down for
the domain and things mostly happened behind the scenes. On i.MX8M* things
got more complex, as there are now nested power domains and coupling of
the data busses is handled by AMBA domain bridges (ADB), which aren't
sequenced by the GPC hardware, but have handshake requests/acks wired
up to a register in the GPC that needs to be handled by software. Due to
hardware issues some of the reset sequencing also needs to be handled by
software, as the GPC isn't always able to properly trigger the SRC reset
for the peripherals inside the power domains.

Generally with all those nested domains there exists a outer *MIX
(e.g. VPUMIX, DISPMIX) domain that contains the ADB and the BLK_CTRL.
Handshake with the ADB can only happen after the *MIX domain is powered
up and some domain specific initialization in the BLK_CTRL is done. The
ADB is connected to a bus clock from CCM that needs to be enabled for
the ADB to work. Also there might be additional resets and clock gates
for the ADB in the BLK_CTRL MMIO region, which is also only accessible
after the *MIX domain is powered up.
Some peripherals are directly located in the *MIX domain, but others
are placed in inner domains located in the *MIX domain. In order to
power up those nested domains the *MIX domain must already be powered up
and the ADB handshake must be finished. Reset is handled via the BLK_CTRL,
instead of the SRC, which contains resets and clock gates for the
peripherals.
The general flow for those inner domains is:
1. Assert reset and ungate clocks in BLK_CTRL to allow reset to propagate
2. Request power up at the GPC
3. Deassert reset

Failing to meet the ADB handshake and/or reset sequencing requirements
will generally lead to system hangs (not necessarily at the point where
the sequence is violated). The blk-ctrl driver as implemented hides this
behind virtual power domains. Peripherals don't need to care whether they
are located directly inside the *MIX domain or in a nested domain, they
all just use the power domains exposed by the BLK_CTRL driver, which
handles the sequencing requiments internally.

Currently this series implements both the VPU and DISP blk-ctrls for the
i.MX8MM SoC, but I'm quite confident that the design is sound and can be
trivially extended for the other i.MX8M* SoCs. On my personal TODO list
is the conversion of the i.MX8MQ VPU blk-ctrl to the new model, which
should finally allow us to drive the G1 and G2 VPUs independently. After
that I'm going to look at the i.MX8MP, as this is a current focus of my
work and has even more blk-ctrl instances. But before moving on to those,
I would like to gather some feedback and testing on this series.

I will also provide a branch with those patches and the WIP VPU and
display patches I used to test this. But that will have to wait for next
week, as it's getting pretty late here.

Regards,
Lucas

Frieder Schrempf (1):
  arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core

Lucas Stach (14):
  Revert "soc: imx: gpcv2: move reset assert after requesting domain
    power up"
  soc: imx: gpcv2: add lockdep annotation
  soc: imx: gpcv2: add domain option to keep domain clocks enabled
  soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
  dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
  dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains
  soc: imx: add i.MX8M blk-ctrl driver
  dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
  dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains
  soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
  arm64: dts: imx8mm: add GPC node
  arm64: dts: imx8mm: put USB controllers into power-domains
  arm64: dts: imx8mm: add VPU blk-ctrl
  arm64: dts: imx8mm: add DISP blk-ctrl

Marek Vasut (2):
  soc: imx: gpcv2: Turn domain->pgc into bitfield
  soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU
    domain

 .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     |  97 ++++
 .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      |  79 +++
 arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 180 +++++++
 drivers/soc/imx/Makefile                      |   1 +
 drivers/soc/imx/gpcv2.c                       |  99 ++--
 drivers/soc/imx/imx8m-blk-ctrl.c              | 464 ++++++++++++++++++
 include/dt-bindings/power/imx8mm-power.h      |   9 +
 7 files changed, 888 insertions(+), 41 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
 create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c

-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 01/17] Revert "soc: imx: gpcv2: move reset assert after requesting domain power up"
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This reverts commit a77ebdd9f553. It turns out that the VPU domain has no
different requirements, even though the downstream ATF implementation seems
to suggest otherwise. Powering on the domain with the reset asserted works
fine. As the changed sequence has caused sporadic issues with the GPU
domains, just revert the change to go back to the working sequence.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 34a9ac1f2b9b..8b7a01773aec 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -244,6 +244,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 		goto out_regulator_disable;
 	}
 
+	reset_control_assert(domain->reset);
+
 	if (domain->bits.pxx) {
 		/* request the domain to power up */
 		regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
@@ -266,8 +268,6 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 				  GPC_PGC_CTRL_PCR);
 	}
 
-	reset_control_assert(domain->reset);
-
 	/* delay for reset to propagate */
 	udelay(5);
 
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 01/17] Revert "soc: imx: gpcv2: move reset assert after requesting domain power up"
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This reverts commit a77ebdd9f553. It turns out that the VPU domain has no
different requirements, even though the downstream ATF implementation seems
to suggest otherwise. Powering on the domain with the reset asserted works
fine. As the changed sequence has caused sporadic issues with the GPU
domains, just revert the change to go back to the working sequence.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 34a9ac1f2b9b..8b7a01773aec 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -244,6 +244,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 		goto out_regulator_disable;
 	}
 
+	reset_control_assert(domain->reset);
+
 	if (domain->bits.pxx) {
 		/* request the domain to power up */
 		regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
@@ -266,8 +268,6 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 				  GPC_PGC_CTRL_PCR);
 	}
 
-	reset_control_assert(domain->reset);
-
 	/* delay for reset to propagate */
 	udelay(5);
 
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 02/17] soc: imx: gpcv2: Turn domain->pgc into bitfield
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

From: Marek Vasut <marex@denx.de>

There is currently the MX8MM GPU domain, which is in fact a composite domain
for both GPU2D and GPU3D. To correctly configure this domain, it is necessary
to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same
time. This is currently not possible.

Turn the domain->pgc from value into bitfield and use for_each_set_bit() to
iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL
register array. This way it is possible to configure all GPC_PGC_nCTRL
registers required in a particular domain.

This is a preparatory patch, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
v2 (Lucas Stach):
- rebase on top of reverted reset sequence change
- also convert i.MX8MN domains
---
 drivers/soc/imx/gpcv2.c | 72 ++++++++++++++++++++++-------------------
 1 file changed, 38 insertions(+), 34 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 8b7a01773aec..c7826ce92f0d 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -192,7 +192,7 @@ struct imx_pgc_domain {
 	struct clk_bulk_data *clks;
 	int num_clks;
 
-	unsigned int pgc;
+	unsigned long pgc;
 
 	const struct {
 		u32 pxx;
@@ -220,7 +220,7 @@ to_imx_pgc_domain(struct generic_pm_domain *genpd)
 static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 {
 	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
-	u32 reg_val;
+	u32 reg_val, pgc;
 	int ret;
 
 	ret = pm_runtime_get_sync(domain->dev);
@@ -264,8 +264,10 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 		}
 
 		/* disable power control */
-		regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
-				  GPC_PGC_CTRL_PCR);
+		for_each_set_bit(pgc, &domain->pgc, 32) {
+			regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
+					  GPC_PGC_CTRL_PCR);
+		}
 	}
 
 	/* delay for reset to propagate */
@@ -311,7 +313,7 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 {
 	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
-	u32 reg_val;
+	u32 reg_val, pgc;
 	int ret;
 
 	/* Enable reset clocks for all devices in the domain */
@@ -338,8 +340,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 
 	if (domain->bits.pxx) {
 		/* enable power control */
-		regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
-				   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+		for_each_set_bit(pgc, &domain->pgc, 32) {
+			regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
+					   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+		}
 
 		/* request the domain to power down */
 		regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
@@ -389,7 +393,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1000000,
-		.pgc	   = IMX7_PGC_MIPI,
+		.pgc	   = BIT(IMX7_PGC_MIPI),
 	},
 
 	[IMX7_POWER_DOMAIN_PCIE_PHY] = {
@@ -401,7 +405,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1000000,
-		.pgc	   = IMX7_PGC_PCIE,
+		.pgc	   = BIT(IMX7_PGC_PCIE),
 	},
 
 	[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
@@ -413,7 +417,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1200000,
-		.pgc	   = IMX7_PGC_USB_HSIC,
+		.pgc	   = BIT(IMX7_PGC_USB_HSIC),
 	},
 };
 
@@ -448,7 +452,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_MIPI_SW_Pxx_REQ,
 			.map = IMX8M_MIPI_A53_DOMAIN,
 		},
-		.pgc	   = IMX8M_PGC_MIPI,
+		.pgc	   = BIT(IMX8M_PGC_MIPI),
 	},
 
 	[IMX8M_POWER_DOMAIN_PCIE1] = {
@@ -459,7 +463,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_PCIE1_SW_Pxx_REQ,
 			.map = IMX8M_PCIE1_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_PCIE1,
+		.pgc   = BIT(IMX8M_PGC_PCIE1),
 	},
 
 	[IMX8M_POWER_DOMAIN_USB_OTG1] = {
@@ -470,7 +474,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_OTG1_SW_Pxx_REQ,
 			.map = IMX8M_OTG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_OTG1,
+		.pgc   = BIT(IMX8M_PGC_OTG1),
 	},
 
 	[IMX8M_POWER_DOMAIN_USB_OTG2] = {
@@ -481,7 +485,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_OTG2_SW_Pxx_REQ,
 			.map = IMX8M_OTG2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_OTG2,
+		.pgc   = BIT(IMX8M_PGC_OTG2),
 	},
 
 	[IMX8M_POWER_DOMAIN_DDR1] = {
@@ -492,7 +496,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_DDR1_SW_Pxx_REQ,
 			.map = IMX8M_DDR2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_DDR1,
+		.pgc   = BIT(IMX8M_PGC_DDR1),
 	},
 
 	[IMX8M_POWER_DOMAIN_GPU] = {
@@ -505,7 +509,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.hskreq = IMX8M_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8M_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8M_PGC_GPU,
+		.pgc   = BIT(IMX8M_PGC_GPU),
 	},
 
 	[IMX8M_POWER_DOMAIN_VPU] = {
@@ -518,7 +522,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.hskreq = IMX8M_VPU_HSK_PWRDNREQN,
 			.hskack = IMX8M_VPU_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8M_PGC_VPU,
+		.pgc   = BIT(IMX8M_PGC_VPU),
 	},
 
 	[IMX8M_POWER_DOMAIN_DISP] = {
@@ -531,7 +535,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.hskreq = IMX8M_DISP_HSK_PWRDNREQN,
 			.hskack = IMX8M_DISP_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8M_PGC_DISP,
+		.pgc   = BIT(IMX8M_PGC_DISP),
 	},
 
 	[IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
@@ -542,7 +546,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
 			.map = IMX8M_MIPI_CSI1_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_MIPI_CSI1,
+		.pgc   = BIT(IMX8M_PGC_MIPI_CSI1),
 	},
 
 	[IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
@@ -553,7 +557,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
 			.map = IMX8M_MIPI_CSI2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_MIPI_CSI2,
+		.pgc   = BIT(IMX8M_PGC_MIPI_CSI2),
 	},
 
 	[IMX8M_POWER_DOMAIN_PCIE2] = {
@@ -564,7 +568,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_PCIE2_SW_Pxx_REQ,
 			.map = IMX8M_PCIE2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_PCIE2,
+		.pgc   = BIT(IMX8M_PGC_PCIE2),
 	},
 };
 
@@ -627,7 +631,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_PCIE_SW_Pxx_REQ,
 			.map = IMX8MM_PCIE_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_PCIE,
+		.pgc   = BIT(IMX8MM_PGC_PCIE),
 	},
 
 	[IMX8MM_POWER_DOMAIN_OTG1] = {
@@ -638,7 +642,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_OTG1_SW_Pxx_REQ,
 			.map = IMX8MM_OTG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_OTG1,
+		.pgc   = BIT(IMX8MM_PGC_OTG1),
 	},
 
 	[IMX8MM_POWER_DOMAIN_OTG2] = {
@@ -649,7 +653,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_OTG2_SW_Pxx_REQ,
 			.map = IMX8MM_OTG2_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_OTG2,
+		.pgc   = BIT(IMX8MM_PGC_OTG2),
 	},
 
 	[IMX8MM_POWER_DOMAIN_GPUMIX] = {
@@ -662,7 +666,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_GPUMIX,
+		.pgc   = BIT(IMX8MM_PGC_GPUMIX),
 	},
 
 	[IMX8MM_POWER_DOMAIN_GPU] = {
@@ -675,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_GPU2D,
+		.pgc   = BIT(IMX8MM_PGC_GPU2D),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
@@ -688,7 +692,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_VPUMIX,
+		.pgc   = BIT(IMX8MM_PGC_VPUMIX),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUG1] = {
@@ -699,7 +703,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
 			.map = IMX8MM_VPUG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_VPUG1,
+		.pgc   = BIT(IMX8MM_PGC_VPUG1),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUG2] = {
@@ -710,7 +714,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
 			.map = IMX8MM_VPUG2_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_VPUG2,
+		.pgc   = BIT(IMX8MM_PGC_VPUG2),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUH1] = {
@@ -721,7 +725,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
 			.map = IMX8MM_VPUH1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_VPUH1,
+		.pgc   = BIT(IMX8MM_PGC_VPUH1),
 	},
 
 	[IMX8MM_POWER_DOMAIN_DISPMIX] = {
@@ -734,7 +738,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_DISPMIX,
+		.pgc   = BIT(IMX8MM_PGC_DISPMIX),
 	},
 
 	[IMX8MM_POWER_DOMAIN_MIPI] = {
@@ -745,7 +749,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_MIPI_SW_Pxx_REQ,
 			.map = IMX8MM_MIPI_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_MIPI,
+		.pgc   = BIT(IMX8MM_PGC_MIPI),
 	},
 };
 
@@ -812,7 +816,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 			.pxx = IMX8MN_OTG1_SW_Pxx_REQ,
 			.map = IMX8MN_OTG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MN_PGC_OTG1,
+		.pgc   = BIT(IMX8MN_PGC_OTG1),
 	},
 
 	[IMX8MN_POWER_DOMAIN_GPUMIX] = {
@@ -825,7 +829,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 			.hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MN_PGC_GPUMIX,
+		.pgc   = BIT(IMX8MN_PGC_GPUMIX),
 	},
 };
 
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 02/17] soc: imx: gpcv2: Turn domain->pgc into bitfield
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

From: Marek Vasut <marex@denx.de>

There is currently the MX8MM GPU domain, which is in fact a composite domain
for both GPU2D and GPU3D. To correctly configure this domain, it is necessary
to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same
time. This is currently not possible.

Turn the domain->pgc from value into bitfield and use for_each_set_bit() to
iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL
register array. This way it is possible to configure all GPC_PGC_nCTRL
registers required in a particular domain.

This is a preparatory patch, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
v2 (Lucas Stach):
- rebase on top of reverted reset sequence change
- also convert i.MX8MN domains
---
 drivers/soc/imx/gpcv2.c | 72 ++++++++++++++++++++++-------------------
 1 file changed, 38 insertions(+), 34 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 8b7a01773aec..c7826ce92f0d 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -192,7 +192,7 @@ struct imx_pgc_domain {
 	struct clk_bulk_data *clks;
 	int num_clks;
 
-	unsigned int pgc;
+	unsigned long pgc;
 
 	const struct {
 		u32 pxx;
@@ -220,7 +220,7 @@ to_imx_pgc_domain(struct generic_pm_domain *genpd)
 static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 {
 	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
-	u32 reg_val;
+	u32 reg_val, pgc;
 	int ret;
 
 	ret = pm_runtime_get_sync(domain->dev);
@@ -264,8 +264,10 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 		}
 
 		/* disable power control */
-		regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
-				  GPC_PGC_CTRL_PCR);
+		for_each_set_bit(pgc, &domain->pgc, 32) {
+			regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
+					  GPC_PGC_CTRL_PCR);
+		}
 	}
 
 	/* delay for reset to propagate */
@@ -311,7 +313,7 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 {
 	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
-	u32 reg_val;
+	u32 reg_val, pgc;
 	int ret;
 
 	/* Enable reset clocks for all devices in the domain */
@@ -338,8 +340,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 
 	if (domain->bits.pxx) {
 		/* enable power control */
-		regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
-				   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+		for_each_set_bit(pgc, &domain->pgc, 32) {
+			regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
+					   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+		}
 
 		/* request the domain to power down */
 		regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
@@ -389,7 +393,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1000000,
-		.pgc	   = IMX7_PGC_MIPI,
+		.pgc	   = BIT(IMX7_PGC_MIPI),
 	},
 
 	[IMX7_POWER_DOMAIN_PCIE_PHY] = {
@@ -401,7 +405,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1000000,
-		.pgc	   = IMX7_PGC_PCIE,
+		.pgc	   = BIT(IMX7_PGC_PCIE),
 	},
 
 	[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
@@ -413,7 +417,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1200000,
-		.pgc	   = IMX7_PGC_USB_HSIC,
+		.pgc	   = BIT(IMX7_PGC_USB_HSIC),
 	},
 };
 
@@ -448,7 +452,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_MIPI_SW_Pxx_REQ,
 			.map = IMX8M_MIPI_A53_DOMAIN,
 		},
-		.pgc	   = IMX8M_PGC_MIPI,
+		.pgc	   = BIT(IMX8M_PGC_MIPI),
 	},
 
 	[IMX8M_POWER_DOMAIN_PCIE1] = {
@@ -459,7 +463,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_PCIE1_SW_Pxx_REQ,
 			.map = IMX8M_PCIE1_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_PCIE1,
+		.pgc   = BIT(IMX8M_PGC_PCIE1),
 	},
 
 	[IMX8M_POWER_DOMAIN_USB_OTG1] = {
@@ -470,7 +474,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_OTG1_SW_Pxx_REQ,
 			.map = IMX8M_OTG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_OTG1,
+		.pgc   = BIT(IMX8M_PGC_OTG1),
 	},
 
 	[IMX8M_POWER_DOMAIN_USB_OTG2] = {
@@ -481,7 +485,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_OTG2_SW_Pxx_REQ,
 			.map = IMX8M_OTG2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_OTG2,
+		.pgc   = BIT(IMX8M_PGC_OTG2),
 	},
 
 	[IMX8M_POWER_DOMAIN_DDR1] = {
@@ -492,7 +496,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_DDR1_SW_Pxx_REQ,
 			.map = IMX8M_DDR2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_DDR1,
+		.pgc   = BIT(IMX8M_PGC_DDR1),
 	},
 
 	[IMX8M_POWER_DOMAIN_GPU] = {
@@ -505,7 +509,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.hskreq = IMX8M_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8M_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8M_PGC_GPU,
+		.pgc   = BIT(IMX8M_PGC_GPU),
 	},
 
 	[IMX8M_POWER_DOMAIN_VPU] = {
@@ -518,7 +522,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.hskreq = IMX8M_VPU_HSK_PWRDNREQN,
 			.hskack = IMX8M_VPU_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8M_PGC_VPU,
+		.pgc   = BIT(IMX8M_PGC_VPU),
 	},
 
 	[IMX8M_POWER_DOMAIN_DISP] = {
@@ -531,7 +535,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.hskreq = IMX8M_DISP_HSK_PWRDNREQN,
 			.hskack = IMX8M_DISP_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8M_PGC_DISP,
+		.pgc   = BIT(IMX8M_PGC_DISP),
 	},
 
 	[IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
@@ -542,7 +546,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
 			.map = IMX8M_MIPI_CSI1_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_MIPI_CSI1,
+		.pgc   = BIT(IMX8M_PGC_MIPI_CSI1),
 	},
 
 	[IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
@@ -553,7 +557,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
 			.map = IMX8M_MIPI_CSI2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_MIPI_CSI2,
+		.pgc   = BIT(IMX8M_PGC_MIPI_CSI2),
 	},
 
 	[IMX8M_POWER_DOMAIN_PCIE2] = {
@@ -564,7 +568,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_PCIE2_SW_Pxx_REQ,
 			.map = IMX8M_PCIE2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_PCIE2,
+		.pgc   = BIT(IMX8M_PGC_PCIE2),
 	},
 };
 
@@ -627,7 +631,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_PCIE_SW_Pxx_REQ,
 			.map = IMX8MM_PCIE_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_PCIE,
+		.pgc   = BIT(IMX8MM_PGC_PCIE),
 	},
 
 	[IMX8MM_POWER_DOMAIN_OTG1] = {
@@ -638,7 +642,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_OTG1_SW_Pxx_REQ,
 			.map = IMX8MM_OTG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_OTG1,
+		.pgc   = BIT(IMX8MM_PGC_OTG1),
 	},
 
 	[IMX8MM_POWER_DOMAIN_OTG2] = {
@@ -649,7 +653,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_OTG2_SW_Pxx_REQ,
 			.map = IMX8MM_OTG2_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_OTG2,
+		.pgc   = BIT(IMX8MM_PGC_OTG2),
 	},
 
 	[IMX8MM_POWER_DOMAIN_GPUMIX] = {
@@ -662,7 +666,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_GPUMIX,
+		.pgc   = BIT(IMX8MM_PGC_GPUMIX),
 	},
 
 	[IMX8MM_POWER_DOMAIN_GPU] = {
@@ -675,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_GPU2D,
+		.pgc   = BIT(IMX8MM_PGC_GPU2D),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
@@ -688,7 +692,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_VPUMIX,
+		.pgc   = BIT(IMX8MM_PGC_VPUMIX),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUG1] = {
@@ -699,7 +703,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
 			.map = IMX8MM_VPUG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_VPUG1,
+		.pgc   = BIT(IMX8MM_PGC_VPUG1),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUG2] = {
@@ -710,7 +714,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
 			.map = IMX8MM_VPUG2_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_VPUG2,
+		.pgc   = BIT(IMX8MM_PGC_VPUG2),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUH1] = {
@@ -721,7 +725,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
 			.map = IMX8MM_VPUH1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_VPUH1,
+		.pgc   = BIT(IMX8MM_PGC_VPUH1),
 	},
 
 	[IMX8MM_POWER_DOMAIN_DISPMIX] = {
@@ -734,7 +738,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_DISPMIX,
+		.pgc   = BIT(IMX8MM_PGC_DISPMIX),
 	},
 
 	[IMX8MM_POWER_DOMAIN_MIPI] = {
@@ -745,7 +749,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_MIPI_SW_Pxx_REQ,
 			.map = IMX8MM_MIPI_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_MIPI,
+		.pgc   = BIT(IMX8MM_PGC_MIPI),
 	},
 };
 
@@ -812,7 +816,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 			.pxx = IMX8MN_OTG1_SW_Pxx_REQ,
 			.map = IMX8MN_OTG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MN_PGC_OTG1,
+		.pgc   = BIT(IMX8MN_PGC_OTG1),
 	},
 
 	[IMX8MN_POWER_DOMAIN_GPUMIX] = {
@@ -825,7 +829,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 			.hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MN_PGC_GPUMIX,
+		.pgc   = BIT(IMX8MN_PGC_GPUMIX),
 	},
 };
 
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 03/17] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

From: Marek Vasut <marex@denx.de>

To bring up the MX8MM GPU domain, it is necessary to configure both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
this configuration, the system might hang on boot when bringing up
the GPU power domain. This is sporadically observed on multiple
disparate systems.

Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
configured when bringing up the GPU domain. This fixes the sporadic
hang.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index c7826ce92f0d..2c43e74db0be 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -679,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = BIT(IMX8MM_PGC_GPU2D),
+		.pgc   = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 03/17] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

From: Marek Vasut <marex@denx.de>

To bring up the MX8MM GPU domain, it is necessary to configure both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
this configuration, the system might hang on boot when bringing up
the GPU power domain. This is sporadically observed on multiple
disparate systems.

Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
configured when bringing up the GPU domain. This fixes the sporadic
hang.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index c7826ce92f0d..2c43e74db0be 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -679,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = BIT(IMX8MM_PGC_GPU2D),
+		.pgc   = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 04/17] soc: imx: gpcv2: add lockdep annotation
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Some of the GPCv2 power domains are nested inside each other without
visibility to lockdep at the genpd level, as they are in separate
driver instances and don't have a parent/child power-domain relationship.

Add a subclass annotation to the nested domains to let lockdep know that
it is okay to take the genpd lock in a nested fashion.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 2c43e74db0be..35f26f57d1ac 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -898,6 +898,10 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
 		goto out_domain_unmap;
 	}
 
+	if (IS_ENABLED(CONFIG_LOCKDEP) &&
+	    of_property_read_bool(domain->dev->of_node, "power-domains"))
+		lockdep_set_subclass(&domain->genpd.mlock, 1);
+
 	ret = of_genpd_add_provider_simple(domain->dev->of_node,
 					   &domain->genpd);
 	if (ret) {
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 04/17] soc: imx: gpcv2: add lockdep annotation
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Some of the GPCv2 power domains are nested inside each other without
visibility to lockdep at the genpd level, as they are in separate
driver instances and don't have a parent/child power-domain relationship.

Add a subclass annotation to the nested domains to let lockdep know that
it is okay to take the genpd lock in a nested fashion.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 2c43e74db0be..35f26f57d1ac 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -898,6 +898,10 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
 		goto out_domain_unmap;
 	}
 
+	if (IS_ENABLED(CONFIG_LOCKDEP) &&
+	    of_property_read_bool(domain->dev->of_node, "power-domains"))
+		lockdep_set_subclass(&domain->genpd.mlock, 1);
+
 	ret = of_genpd_add_provider_simple(domain->dev->of_node,
 					   &domain->genpd);
 	if (ret) {
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 05/17] soc: imx: gpcv2: add domain option to keep domain clocks enabled
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Some of the MIX domains are using clocks to drive the bus bridges. Those
must be enabled at all times, as long as the domain is powered up and
they don't have any other consumer than the power domain. Add an option
to keep the clocks attached to a domain enabled as long as the domain
is power up and only disable them after the domain is powered down.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 35f26f57d1ac..c3b1d2580963 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -202,6 +202,7 @@ struct imx_pgc_domain {
 	} bits;
 
 	const int voltage;
+	const bool keep_clocks;
 	struct device *dev;
 };
 
@@ -295,7 +296,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 	}
 
 	/* Disable reset clocks for all devices in the domain */
-	clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
+	if (!domain->keep_clocks)
+		clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 
 	return 0;
 
@@ -317,10 +319,12 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 	int ret;
 
 	/* Enable reset clocks for all devices in the domain */
-	ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
-	if (ret) {
-		dev_err(domain->dev, "failed to enable reset clocks\n");
-		return ret;
+	if (!domain->keep_clocks) {
+		ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
+		if (ret) {
+			dev_err(domain->dev, "failed to enable reset clocks\n");
+			return ret;
+		}
 	}
 
 	/* request the ADB400 to power down */
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 05/17] soc: imx: gpcv2: add domain option to keep domain clocks enabled
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Some of the MIX domains are using clocks to drive the bus bridges. Those
must be enabled at all times, as long as the domain is powered up and
they don't have any other consumer than the power domain. Add an option
to keep the clocks attached to a domain enabled as long as the domain
is power up and only disable them after the domain is powered down.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 35f26f57d1ac..c3b1d2580963 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -202,6 +202,7 @@ struct imx_pgc_domain {
 	} bits;
 
 	const int voltage;
+	const bool keep_clocks;
 	struct device *dev;
 };
 
@@ -295,7 +296,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 	}
 
 	/* Disable reset clocks for all devices in the domain */
-	clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
+	if (!domain->keep_clocks)
+		clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 
 	return 0;
 
@@ -317,10 +319,12 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 	int ret;
 
 	/* Enable reset clocks for all devices in the domain */
-	ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
-	if (ret) {
-		dev_err(domain->dev, "failed to enable reset clocks\n");
-		return ret;
+	if (!domain->keep_clocks) {
+		ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
+		if (ret) {
+			dev_err(domain->dev, "failed to enable reset clocks\n");
+			return ret;
+		}
 	}
 
 	/* request the ADB400 to power down */
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 06/17] soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Annotate the domains with bus clocks to keep those clocks enabled
as long as the domain is active.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index c3b1d2580963..66697d4e8035 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -625,6 +625,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
 			.hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
 		},
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_PCIE] = {
@@ -684,6 +685,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 		},
 		.pgc   = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
@@ -697,6 +699,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
 		},
 		.pgc   = BIT(IMX8MM_PGC_VPUMIX),
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUG1] = {
@@ -743,6 +746,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
 		},
 		.pgc   = BIT(IMX8MM_PGC_DISPMIX),
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_MIPI] = {
@@ -810,6 +814,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 			.hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
 			.hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
 		},
+		.keep_clocks = true,
 	},
 
 	[IMX8MN_POWER_DOMAIN_OTG1] = {
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 06/17] soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Annotate the domains with bus clocks to keep those clocks enabled
as long as the domain is active.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index c3b1d2580963..66697d4e8035 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -625,6 +625,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
 			.hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
 		},
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_PCIE] = {
@@ -684,6 +685,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 		},
 		.pgc   = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
@@ -697,6 +699,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
 		},
 		.pgc   = BIT(IMX8MM_PGC_VPUMIX),
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUG1] = {
@@ -743,6 +746,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
 		},
 		.pgc   = BIT(IMX8MM_PGC_DISPMIX),
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_MIPI] = {
@@ -810,6 +814,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 			.hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
 			.hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
 		},
+		.keep_clocks = true,
 	},
 
 	[IMX8MN_POWER_DOMAIN_OTG1] = {
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 07/17] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the DT binding for the i.MX8MM VPU blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
new file mode 100644
index 000000000000..eea52eba2fa5
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MM VPU blk-ctrl
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+  The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
+  the NoC and ensuring proper power sequencing of the VPU peripherals
+  located in the VPU domain of the SoC.
+
+properties:
+  compatible:
+    - const: fsl,imx8mm-vpu-blk-ctrl
+    - const: syscon
+
+  reg:
+    maxItems: 1
+
+  "#power-domains-cells":
+    const: 1
+
+  power-domains:
+    minItems: 4
+    maxItems: 4
+
+  power-domain-names:
+    minItems: 4
+    maxItems: 4
+    items:
+      - bus
+      - g1
+      - g1
+      - h1
+
+  clocks:
+    minItems: 3
+    maxItems: 3
+
+  clock-names:
+    minItems: 3
+    maxItems: 3
+    items:
+      - g1
+      - g2
+      - h1
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mm-clock.h>
+    #include <dt-bindings/power/imx8mm-power.h
+
+    vpu_blk_ctrl: blk-ctrl@38330000 {
+      compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
+      reg = <0x38330000 0x100>;
+      power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
+                      <&pgc_vpu_g2>, <&pgc_vpu_h1>;
+      power-domain-names = "bus", "g1", "g2", "h1";
+      clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
+               <&clk IMX8MM_CLK_VPU_G2_ROOT>,
+               <&clk IMX8MM_CLK_VPU_H1_ROOT>;
+      clock-names = "g1", "g2", "h1";
+      #power-domain-cells = <1>;
+    };
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 07/17] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the DT binding for the i.MX8MM VPU blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
new file mode 100644
index 000000000000..eea52eba2fa5
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MM VPU blk-ctrl
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+  The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
+  the NoC and ensuring proper power sequencing of the VPU peripherals
+  located in the VPU domain of the SoC.
+
+properties:
+  compatible:
+    - const: fsl,imx8mm-vpu-blk-ctrl
+    - const: syscon
+
+  reg:
+    maxItems: 1
+
+  "#power-domains-cells":
+    const: 1
+
+  power-domains:
+    minItems: 4
+    maxItems: 4
+
+  power-domain-names:
+    minItems: 4
+    maxItems: 4
+    items:
+      - bus
+      - g1
+      - g1
+      - h1
+
+  clocks:
+    minItems: 3
+    maxItems: 3
+
+  clock-names:
+    minItems: 3
+    maxItems: 3
+    items:
+      - g1
+      - g2
+      - h1
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mm-clock.h>
+    #include <dt-bindings/power/imx8mm-power.h
+
+    vpu_blk_ctrl: blk-ctrl@38330000 {
+      compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
+      reg = <0x38330000 0x100>;
+      power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
+                      <&pgc_vpu_g2>, <&pgc_vpu_h1>;
+      power-domain-names = "bus", "g1", "g2", "h1";
+      clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
+               <&clk IMX8MM_CLK_VPU_G2_ROOT>,
+               <&clk IMX8MM_CLK_VPU_H1_ROOT>;
+      clock-names = "g1", "g2", "h1";
+      #power-domain-cells = <1>;
+    };
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 08/17] dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the defines for the power domains provided by the VPU
blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 include/dt-bindings/power/imx8mm-power.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
index fc9c2e16aadc..38b0a56fd7d0 100644
--- a/include/dt-bindings/power/imx8mm-power.h
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -19,4 +19,8 @@
 #define IMX8MM_POWER_DOMAIN_DISPMIX	10
 #define IMX8MM_POWER_DOMAIN_MIPI	11
 
+#define IMX8MM_VPUBLK_PD_G1		0
+#define IMX8MM_VPUBLK_PD_G2		1
+#define IMX8MM_VPUBLK_PD_H1		2
+
 #endif
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 08/17] dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the defines for the power domains provided by the VPU
blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 include/dt-bindings/power/imx8mm-power.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
index fc9c2e16aadc..38b0a56fd7d0 100644
--- a/include/dt-bindings/power/imx8mm-power.h
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -19,4 +19,8 @@
 #define IMX8MM_POWER_DOMAIN_DISPMIX	10
 #define IMX8MM_POWER_DOMAIN_MIPI	11
 
+#define IMX8MM_VPUBLK_PD_G1		0
+#define IMX8MM_VPUBLK_PD_G2		1
+#define IMX8MM_VPUBLK_PD_H1		2
+
 #endif
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 09/17] soc: imx: add i.MX8M blk-ctrl driver
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds a driver for the blk-ctrl blocks found in the i.MX8M* line of
SoCs. The blk-ctrl is a top-level peripheral located in the various *MIX
power domains and interacts with the GPC power controller to provide the
peripherals in the power domain access to the NoC and ensures that those
peripherals are properly reset when their respective power domain is
brought back to life.

Software needs to do different things to make the bus handshake happen
after the the GPC *MIX domain is power up and before it is powered down.
As the requirements are quite different between the various blk-ctrls
there is a callback function provided to hook in the proper sequence.

The peripheral domains are quite uniform, they handle the soft clock
enables and resets in the blk-ctrl address space and sequencing with the
upstream GPC power domains.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
This commit includes the full code to drive the VPUMIX domain on the
i.MX8MM, as the skeleton driver would probably be harder to review
without the context provided by one blk-ctrl implementation. Other
blk-ctrl implementations will follow, based on this overall structure.
---
 drivers/soc/imx/Makefile         |   1 +
 drivers/soc/imx/imx8m-blk-ctrl.c | 394 +++++++++++++++++++++++++++++++
 2 files changed, 395 insertions(+)
 create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c

diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index 078dc918f4f3..8a707077914c 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -5,3 +5,4 @@ endif
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
 obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
+obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
new file mode 100644
index 000000000000..90ff845b2643
--- /dev/null
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -0,0 +1,394 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2021 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/clk.h>
+
+#include <dt-bindings/power/imx8mm-power.h>
+
+#define BLK_SFT_RSTN	0x0
+#define BLK_CLK_EN	0x4
+
+struct imx8m_blk_ctrl_domain;
+
+struct imx8m_blk_ctrl {
+	struct device *dev;
+	struct notifier_block power_nb;
+	struct device *bus_power_dev;
+	struct regmap *regmap;
+	struct imx8m_blk_ctrl_domain *domains;
+	struct genpd_onecell_data onecell_data;
+};
+
+struct imx8m_blk_ctrl_domain_data {
+	const char *name;
+	const char **clk_names;
+	int num_clks;
+	const char *gpc_name;
+	u32 rst_mask;
+	u32 clk_mask;
+};
+
+#define DOMAIN_MAX_CLKS 3
+
+struct imx8m_blk_ctrl_domain {
+	struct generic_pm_domain genpd;
+	const struct imx8m_blk_ctrl_domain_data *data;
+	struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
+	struct device *power_dev;
+	struct imx8m_blk_ctrl *bc;
+};
+
+struct imx8m_blk_ctrl_data {
+	int max_reg;
+	notifier_fn_t power_notifier_fn;
+	const struct imx8m_blk_ctrl_domain_data *domains;
+	int num_domains;
+};
+
+static inline struct imx8m_blk_ctrl_domain *
+to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd)
+{
+	return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd);
+}
+
+static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd)
+{
+	struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);
+	const struct imx8m_blk_ctrl_domain_data *data = domain->data;
+	struct imx8m_blk_ctrl *bc = domain->bc;
+	int ret;
+
+	/* make sure bus domain is awake */
+	ret = pm_runtime_get_sync(bc->bus_power_dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(bc->bus_power_dev);
+		dev_err(bc->dev, "failed to power up bus domain\n");
+		return ret;
+	}
+
+	/* put devices into reset */
+	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
+
+	/* enable upstream and blk-ctrl clocks to allow reset to propagate */
+	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
+	if (ret) {
+		dev_err(bc->dev, "failed to enable clocks\n");
+		goto bus_put;
+	}
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
+
+	/* power up upstream GPC domain */
+	ret = pm_runtime_get_sync(domain->power_dev);
+	if (ret) {
+		dev_err(bc->dev, "failed to power up peripheral domain\n");
+		goto clk_disable;
+	}
+
+	/* wait for reset to propagate */
+	udelay(5);
+
+	/* release reset */
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
+
+	/* disable upstream clocks */
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+
+	return 0;
+
+clk_disable:
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+bus_put:
+	pm_runtime_put(bc->bus_power_dev);
+
+	return ret;
+}
+
+static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd)
+{
+	struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);
+	const struct imx8m_blk_ctrl_domain_data *data = domain->data;
+	struct imx8m_blk_ctrl *bc = domain->bc;
+
+	/* put devices into reset and disable clocks */
+	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
+	regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
+
+	/* power down upstream GPC domain */
+	pm_runtime_put(domain->power_dev);
+
+	/* allow bus domain to suspend */
+	pm_runtime_put(bc->bus_power_dev);
+
+	return 0;
+}
+
+static struct generic_pm_domain *
+imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data)
+{
+	struct genpd_onecell_data *onecell_data = data;
+	unsigned int index = args->args[0];
+
+	if (args->args_count != 1 ||
+	    index > onecell_data->num_domains)
+		return ERR_PTR(-EINVAL);
+
+	return onecell_data->domains[index];
+}
+
+static struct lock_class_key blk_ctrl_genpd_lock_class;
+
+static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
+{
+	const struct imx8m_blk_ctrl_data *bc_data;
+	struct device *dev = &pdev->dev;
+	struct imx8m_blk_ctrl *bc;
+	void __iomem *base;
+	int i, ret;
+
+	struct regmap_config regmap_config = {
+		.reg_bits	= 32,
+		.val_bits	= 32,
+		.reg_stride	= 4,
+	};
+
+	bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
+	if (!bc)
+		return -ENOMEM;
+
+	bc->dev = dev;
+
+	bc_data = of_device_get_match_data(dev);
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	regmap_config.max_register = bc_data->max_reg;
+	bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
+	if (IS_ERR(bc->regmap))
+		return dev_err_probe(dev, PTR_ERR(bc->regmap),
+				     "failed to init regmap \n");
+
+	bc->domains = devm_kcalloc(dev, bc_data->num_domains,
+				    sizeof(struct imx8m_blk_ctrl_domain),
+				    GFP_KERNEL);
+	if (!bc->domains)
+		return -ENOMEM;
+
+	bc->onecell_data.num_domains = bc_data->num_domains;
+	bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
+	bc->onecell_data.domains =
+		devm_kcalloc(dev, bc_data->num_domains,
+			     sizeof(struct generic_pm_domain *), GFP_KERNEL);
+	if (!bc->onecell_data.domains)
+		return -ENOMEM;
+
+	bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
+	if (IS_ERR(bc->bus_power_dev))
+		return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
+				     "failed to attach power domain\n");
+
+	for (i = 0; i < bc_data->num_domains; i++) {
+		const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i];
+		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
+		int j;
+
+		domain->data = data;
+
+		for (j = 0; j < data->num_clks; j++)
+			domain->clks[j].id = data->clk_names[j];
+
+		ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
+		if (ret) {
+			dev_err_probe(dev, ret, "failed to get clock\n");
+			goto cleanup_pds;
+		}
+
+		domain->power_dev =
+			dev_pm_domain_attach_by_name(dev, data->gpc_name);
+		if (IS_ERR(domain->power_dev )) {
+			dev_err_probe(dev, PTR_ERR(domain->power_dev),
+				      "failed to attach power domain\n");
+			goto cleanup_pds;
+		}
+
+		domain->genpd.name = data->name;
+		domain->genpd.power_on = imx8m_blk_ctrl_power_on;
+		domain->genpd.power_off = imx8m_blk_ctrl_power_off;
+		domain->bc = bc;
+
+		ret = pm_genpd_init(&domain->genpd, NULL, true);
+		if (ret) {
+			dev_err_probe(dev, ret, "failed to init power domain\n");
+			dev_pm_domain_detach(domain->power_dev, true);
+			goto cleanup_pds;
+		}
+
+		/*
+		 * We use runtime PM to trigger power on/off of the upstream GPC
+		 * domain, as a strict hierarchical parent/child power domain
+		 * setup doesn't allow us to meet the sequencing requirements.
+		 * This means we have nested locking of genpd locks, without the
+		 * nesting being visible at the genpd level, so we need a
+		 * separate lock class to make lockdep aware of the fact that
+		 * this are separate domain locks that can be nested without a
+		 * self-deadlock.
+		 */
+		lockdep_set_class(&domain->genpd.mlock,
+				  &blk_ctrl_genpd_lock_class);
+
+		bc->onecell_data.domains[i] = &domain->genpd;
+	}
+
+	ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to add power domain provider\n");
+		goto cleanup_pds;
+	}
+
+	bc->power_nb.notifier_call = bc_data->power_notifier_fn;
+	ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to add power notifier\n");
+		goto cleanup_provider;
+	}
+
+	dev_set_drvdata(dev, bc);
+
+	return 0;
+
+cleanup_provider:
+	of_genpd_del_provider(dev->of_node);
+cleanup_pds:
+	for (i--; i >= 0; i--) {
+		pm_genpd_remove(&bc->domains[i].genpd);
+		dev_pm_domain_detach(bc->domains[i].power_dev, true);
+	}
+
+	dev_pm_domain_detach(bc->bus_power_dev, true);
+
+	return ret;
+}
+
+static int imx8m_blk_ctrl_remove(struct platform_device *pdev)
+{
+	struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
+	int i;
+
+	of_genpd_del_provider(pdev->dev.of_node);
+
+	for (i = 0; bc->onecell_data.num_domains; i++) {
+		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
+
+		pm_genpd_remove(&domain->genpd);
+		dev_pm_domain_detach(domain->power_dev, true);
+	}
+
+	dev_pm_genpd_remove_notifier(bc->bus_power_dev);
+
+	dev_pm_domain_detach(bc->bus_power_dev, true);
+
+	return 0;
+}
+
+static int imx8mm_vpu_power_notifier(struct notifier_block *nb,
+				     unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/*
+	 * The ADB in the VPUMIX domain has no separate reset and clock
+	 * enable bits, but is ungated together with the VPU clocks. To
+	 * allow the handshake with the GPC to progress we put the VPUs
+	 * in reset and ungate the clocks.
+	 */
+	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN,
+			  BIT(0) | BIT(1) | BIT(2));
+	regmap_set_bits(bc->regmap, BLK_CLK_EN,
+			BIT(0) | BIT(1) | BIT(2));
+
+	if (action == GENPD_NOTIFY_ON) {
+		/*
+		 * On power up we have no software backchannel to the GPC to
+		 * wait for the ADB handshake to happen, so we just delay for a
+		 * bit. On power down the GPC driver waits for the handshake.
+		 */
+		udelay(5);
+
+		/* set "fuse" bits to enable the VPUs */
+		regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0x14, 0xffffffff);
+	}
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8m_blk_ctrl_domain_data imx8m_vpu_blk_ctl_domain_data[] = {
+	[IMX8MM_VPUBLK_PD_G1] = {
+		.name = "vpublk-g1",
+		.clk_names = (const char *[]){ "g1", },
+		.num_clks = 1,
+		.gpc_name = "g1",
+		.rst_mask = BIT(1),
+		.clk_mask = BIT(1),
+	},
+	[IMX8MM_VPUBLK_PD_G2] = {
+		.name = "vpublk-g2",
+		.clk_names = (const char *[]){ "g2", },
+		.num_clks = 1,
+		.gpc_name = "g2",
+		.rst_mask = BIT(0),
+		.clk_mask = BIT(0),
+	},
+	[IMX8MM_VPUBLK_PD_H1] = {
+		.name = "vpublk-h1",
+		.clk_names = (const char *[]){ "h1", },
+		.num_clks = 1,
+		.gpc_name = "h1",
+		.rst_mask = BIT(2),
+		.clk_mask = BIT(2),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8m_vpu_blk_ctl_dev_data = {
+	.max_reg = 0x18,
+	.power_notifier_fn = imx8mm_vpu_power_notifier,
+	.domains = imx8m_vpu_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
+};
+
+static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
+	{
+		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
+		.data = &imx8m_vpu_blk_ctl_dev_data
+	}, {
+		/* Sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
+
+static struct platform_driver imx8m_blk_ctrl_driver = {
+	.probe = imx8m_blk_ctrl_probe,
+	.remove = imx8m_blk_ctrl_remove,
+	.driver = {
+		.name = "imx8m-blk-ctrl",
+		.of_match_table = imx8m_blk_ctrl_of_match,
+	},
+};
+module_platform_driver(imx8m_blk_ctrl_driver);
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 09/17] soc: imx: add i.MX8M blk-ctrl driver
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds a driver for the blk-ctrl blocks found in the i.MX8M* line of
SoCs. The blk-ctrl is a top-level peripheral located in the various *MIX
power domains and interacts with the GPC power controller to provide the
peripherals in the power domain access to the NoC and ensures that those
peripherals are properly reset when their respective power domain is
brought back to life.

Software needs to do different things to make the bus handshake happen
after the the GPC *MIX domain is power up and before it is powered down.
As the requirements are quite different between the various blk-ctrls
there is a callback function provided to hook in the proper sequence.

The peripheral domains are quite uniform, they handle the soft clock
enables and resets in the blk-ctrl address space and sequencing with the
upstream GPC power domains.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
This commit includes the full code to drive the VPUMIX domain on the
i.MX8MM, as the skeleton driver would probably be harder to review
without the context provided by one blk-ctrl implementation. Other
blk-ctrl implementations will follow, based on this overall structure.
---
 drivers/soc/imx/Makefile         |   1 +
 drivers/soc/imx/imx8m-blk-ctrl.c | 394 +++++++++++++++++++++++++++++++
 2 files changed, 395 insertions(+)
 create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c

diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index 078dc918f4f3..8a707077914c 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -5,3 +5,4 @@ endif
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
 obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
+obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
new file mode 100644
index 000000000000..90ff845b2643
--- /dev/null
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -0,0 +1,394 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2021 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/clk.h>
+
+#include <dt-bindings/power/imx8mm-power.h>
+
+#define BLK_SFT_RSTN	0x0
+#define BLK_CLK_EN	0x4
+
+struct imx8m_blk_ctrl_domain;
+
+struct imx8m_blk_ctrl {
+	struct device *dev;
+	struct notifier_block power_nb;
+	struct device *bus_power_dev;
+	struct regmap *regmap;
+	struct imx8m_blk_ctrl_domain *domains;
+	struct genpd_onecell_data onecell_data;
+};
+
+struct imx8m_blk_ctrl_domain_data {
+	const char *name;
+	const char **clk_names;
+	int num_clks;
+	const char *gpc_name;
+	u32 rst_mask;
+	u32 clk_mask;
+};
+
+#define DOMAIN_MAX_CLKS 3
+
+struct imx8m_blk_ctrl_domain {
+	struct generic_pm_domain genpd;
+	const struct imx8m_blk_ctrl_domain_data *data;
+	struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
+	struct device *power_dev;
+	struct imx8m_blk_ctrl *bc;
+};
+
+struct imx8m_blk_ctrl_data {
+	int max_reg;
+	notifier_fn_t power_notifier_fn;
+	const struct imx8m_blk_ctrl_domain_data *domains;
+	int num_domains;
+};
+
+static inline struct imx8m_blk_ctrl_domain *
+to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd)
+{
+	return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd);
+}
+
+static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd)
+{
+	struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);
+	const struct imx8m_blk_ctrl_domain_data *data = domain->data;
+	struct imx8m_blk_ctrl *bc = domain->bc;
+	int ret;
+
+	/* make sure bus domain is awake */
+	ret = pm_runtime_get_sync(bc->bus_power_dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(bc->bus_power_dev);
+		dev_err(bc->dev, "failed to power up bus domain\n");
+		return ret;
+	}
+
+	/* put devices into reset */
+	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
+
+	/* enable upstream and blk-ctrl clocks to allow reset to propagate */
+	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
+	if (ret) {
+		dev_err(bc->dev, "failed to enable clocks\n");
+		goto bus_put;
+	}
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
+
+	/* power up upstream GPC domain */
+	ret = pm_runtime_get_sync(domain->power_dev);
+	if (ret) {
+		dev_err(bc->dev, "failed to power up peripheral domain\n");
+		goto clk_disable;
+	}
+
+	/* wait for reset to propagate */
+	udelay(5);
+
+	/* release reset */
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
+
+	/* disable upstream clocks */
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+
+	return 0;
+
+clk_disable:
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+bus_put:
+	pm_runtime_put(bc->bus_power_dev);
+
+	return ret;
+}
+
+static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd)
+{
+	struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);
+	const struct imx8m_blk_ctrl_domain_data *data = domain->data;
+	struct imx8m_blk_ctrl *bc = domain->bc;
+
+	/* put devices into reset and disable clocks */
+	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
+	regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
+
+	/* power down upstream GPC domain */
+	pm_runtime_put(domain->power_dev);
+
+	/* allow bus domain to suspend */
+	pm_runtime_put(bc->bus_power_dev);
+
+	return 0;
+}
+
+static struct generic_pm_domain *
+imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data)
+{
+	struct genpd_onecell_data *onecell_data = data;
+	unsigned int index = args->args[0];
+
+	if (args->args_count != 1 ||
+	    index > onecell_data->num_domains)
+		return ERR_PTR(-EINVAL);
+
+	return onecell_data->domains[index];
+}
+
+static struct lock_class_key blk_ctrl_genpd_lock_class;
+
+static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
+{
+	const struct imx8m_blk_ctrl_data *bc_data;
+	struct device *dev = &pdev->dev;
+	struct imx8m_blk_ctrl *bc;
+	void __iomem *base;
+	int i, ret;
+
+	struct regmap_config regmap_config = {
+		.reg_bits	= 32,
+		.val_bits	= 32,
+		.reg_stride	= 4,
+	};
+
+	bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
+	if (!bc)
+		return -ENOMEM;
+
+	bc->dev = dev;
+
+	bc_data = of_device_get_match_data(dev);
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	regmap_config.max_register = bc_data->max_reg;
+	bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
+	if (IS_ERR(bc->regmap))
+		return dev_err_probe(dev, PTR_ERR(bc->regmap),
+				     "failed to init regmap \n");
+
+	bc->domains = devm_kcalloc(dev, bc_data->num_domains,
+				    sizeof(struct imx8m_blk_ctrl_domain),
+				    GFP_KERNEL);
+	if (!bc->domains)
+		return -ENOMEM;
+
+	bc->onecell_data.num_domains = bc_data->num_domains;
+	bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
+	bc->onecell_data.domains =
+		devm_kcalloc(dev, bc_data->num_domains,
+			     sizeof(struct generic_pm_domain *), GFP_KERNEL);
+	if (!bc->onecell_data.domains)
+		return -ENOMEM;
+
+	bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
+	if (IS_ERR(bc->bus_power_dev))
+		return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
+				     "failed to attach power domain\n");
+
+	for (i = 0; i < bc_data->num_domains; i++) {
+		const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i];
+		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
+		int j;
+
+		domain->data = data;
+
+		for (j = 0; j < data->num_clks; j++)
+			domain->clks[j].id = data->clk_names[j];
+
+		ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
+		if (ret) {
+			dev_err_probe(dev, ret, "failed to get clock\n");
+			goto cleanup_pds;
+		}
+
+		domain->power_dev =
+			dev_pm_domain_attach_by_name(dev, data->gpc_name);
+		if (IS_ERR(domain->power_dev )) {
+			dev_err_probe(dev, PTR_ERR(domain->power_dev),
+				      "failed to attach power domain\n");
+			goto cleanup_pds;
+		}
+
+		domain->genpd.name = data->name;
+		domain->genpd.power_on = imx8m_blk_ctrl_power_on;
+		domain->genpd.power_off = imx8m_blk_ctrl_power_off;
+		domain->bc = bc;
+
+		ret = pm_genpd_init(&domain->genpd, NULL, true);
+		if (ret) {
+			dev_err_probe(dev, ret, "failed to init power domain\n");
+			dev_pm_domain_detach(domain->power_dev, true);
+			goto cleanup_pds;
+		}
+
+		/*
+		 * We use runtime PM to trigger power on/off of the upstream GPC
+		 * domain, as a strict hierarchical parent/child power domain
+		 * setup doesn't allow us to meet the sequencing requirements.
+		 * This means we have nested locking of genpd locks, without the
+		 * nesting being visible at the genpd level, so we need a
+		 * separate lock class to make lockdep aware of the fact that
+		 * this are separate domain locks that can be nested without a
+		 * self-deadlock.
+		 */
+		lockdep_set_class(&domain->genpd.mlock,
+				  &blk_ctrl_genpd_lock_class);
+
+		bc->onecell_data.domains[i] = &domain->genpd;
+	}
+
+	ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to add power domain provider\n");
+		goto cleanup_pds;
+	}
+
+	bc->power_nb.notifier_call = bc_data->power_notifier_fn;
+	ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to add power notifier\n");
+		goto cleanup_provider;
+	}
+
+	dev_set_drvdata(dev, bc);
+
+	return 0;
+
+cleanup_provider:
+	of_genpd_del_provider(dev->of_node);
+cleanup_pds:
+	for (i--; i >= 0; i--) {
+		pm_genpd_remove(&bc->domains[i].genpd);
+		dev_pm_domain_detach(bc->domains[i].power_dev, true);
+	}
+
+	dev_pm_domain_detach(bc->bus_power_dev, true);
+
+	return ret;
+}
+
+static int imx8m_blk_ctrl_remove(struct platform_device *pdev)
+{
+	struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
+	int i;
+
+	of_genpd_del_provider(pdev->dev.of_node);
+
+	for (i = 0; bc->onecell_data.num_domains; i++) {
+		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
+
+		pm_genpd_remove(&domain->genpd);
+		dev_pm_domain_detach(domain->power_dev, true);
+	}
+
+	dev_pm_genpd_remove_notifier(bc->bus_power_dev);
+
+	dev_pm_domain_detach(bc->bus_power_dev, true);
+
+	return 0;
+}
+
+static int imx8mm_vpu_power_notifier(struct notifier_block *nb,
+				     unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/*
+	 * The ADB in the VPUMIX domain has no separate reset and clock
+	 * enable bits, but is ungated together with the VPU clocks. To
+	 * allow the handshake with the GPC to progress we put the VPUs
+	 * in reset and ungate the clocks.
+	 */
+	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN,
+			  BIT(0) | BIT(1) | BIT(2));
+	regmap_set_bits(bc->regmap, BLK_CLK_EN,
+			BIT(0) | BIT(1) | BIT(2));
+
+	if (action == GENPD_NOTIFY_ON) {
+		/*
+		 * On power up we have no software backchannel to the GPC to
+		 * wait for the ADB handshake to happen, so we just delay for a
+		 * bit. On power down the GPC driver waits for the handshake.
+		 */
+		udelay(5);
+
+		/* set "fuse" bits to enable the VPUs */
+		regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0x14, 0xffffffff);
+	}
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8m_blk_ctrl_domain_data imx8m_vpu_blk_ctl_domain_data[] = {
+	[IMX8MM_VPUBLK_PD_G1] = {
+		.name = "vpublk-g1",
+		.clk_names = (const char *[]){ "g1", },
+		.num_clks = 1,
+		.gpc_name = "g1",
+		.rst_mask = BIT(1),
+		.clk_mask = BIT(1),
+	},
+	[IMX8MM_VPUBLK_PD_G2] = {
+		.name = "vpublk-g2",
+		.clk_names = (const char *[]){ "g2", },
+		.num_clks = 1,
+		.gpc_name = "g2",
+		.rst_mask = BIT(0),
+		.clk_mask = BIT(0),
+	},
+	[IMX8MM_VPUBLK_PD_H1] = {
+		.name = "vpublk-h1",
+		.clk_names = (const char *[]){ "h1", },
+		.num_clks = 1,
+		.gpc_name = "h1",
+		.rst_mask = BIT(2),
+		.clk_mask = BIT(2),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8m_vpu_blk_ctl_dev_data = {
+	.max_reg = 0x18,
+	.power_notifier_fn = imx8mm_vpu_power_notifier,
+	.domains = imx8m_vpu_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
+};
+
+static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
+	{
+		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
+		.data = &imx8m_vpu_blk_ctl_dev_data
+	}, {
+		/* Sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
+
+static struct platform_driver imx8m_blk_ctrl_driver = {
+	.probe = imx8m_blk_ctrl_probe,
+	.remove = imx8m_blk_ctrl_remove,
+	.driver = {
+		.name = "imx8m-blk-ctrl",
+		.of_match_table = imx8m_blk_ctrl_of_match,
+	},
+};
+module_platform_driver(imx8m_blk_ctrl_driver);
-- 
2.30.2


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 10/17] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the DT binding for the i.MX8MM VPU blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     | 97 +++++++++++++++++++
 1 file changed, 97 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
new file mode 100644
index 000000000000..a2c947b8dd52
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MM DISP blk-ctrl
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+  The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
+  the NoC and ensuring proper power sequencing of the display and MIPI CSI
+  peripherals located in the DISP domain of the SoC.
+
+properties:
+  compatible:
+    - const: fsl,imx8mm-disp-blk-ctrl
+    - const: syscon
+
+  reg:
+    maxItems: 1
+
+  "#power-domains-cells":
+    const: 1
+
+  power-domains:
+    minItems: 5
+    maxItems: 5
+
+  power-domain-names:
+    minItems: 5
+    maxItems: 5
+    items:
+      - bus
+      - csi-bridge
+      - lcdif
+      - mipi-dsi
+      - mipi-csi
+
+  clocks:
+    minItems: 10
+    maxItems: 10
+
+  clock-names:
+    minItems: 10
+    maxItems: 10
+    items:
+      - csi-bridge-axi
+      - csi-bridge-apb
+      - csi-bridge-core
+      - lcdif-axi
+      - lcdif-apb
+      - lcdif-pix
+      - dsi-pclk
+      - dsi-ref
+      - csi-aclk
+      - csi-pclk
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mm-clock.h>
+    #include <dt-bindings/power/imx8mm-power.h
+
+    disp_blk_ctl: blk_ctrl@32e28000 {
+      compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
+      reg = <0x32e28000 0x100>;
+      power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>,
+                      <&pgc_mipi>, <&pgc_mipi>;
+      power-domain-names = "bus", "csi-bridge", "lcdif",
+                           "mipi-dsi", "mipi-csi";
+      clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+               <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+               <&clk IMX8MM_CLK_CSI1_ROOT>,
+               <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+               <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+               <&clk IMX8MM_CLK_DISP_ROOT>,
+               <&clk IMX8MM_CLK_DSI_CORE>,
+               <&clk IMX8MM_CLK_DSI_PHY_REF>,
+               <&clk IMX8MM_CLK_CSI1_CORE>,
+               <&clk IMX8MM_CLK_CSI1_PHY_REF>;
+       clock-names = "csi-bridge-axi","csi-bridge-apb", "csi-bridge-core",
+                     "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
+                     "dsi-ref","csi-aclk", "csi-pclk";
+       #power-domain-cells = <1>;
+    };
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 10/17] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the DT binding for the i.MX8MM VPU blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     | 97 +++++++++++++++++++
 1 file changed, 97 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
new file mode 100644
index 000000000000..a2c947b8dd52
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MM DISP blk-ctrl
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+  The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
+  the NoC and ensuring proper power sequencing of the display and MIPI CSI
+  peripherals located in the DISP domain of the SoC.
+
+properties:
+  compatible:
+    - const: fsl,imx8mm-disp-blk-ctrl
+    - const: syscon
+
+  reg:
+    maxItems: 1
+
+  "#power-domains-cells":
+    const: 1
+
+  power-domains:
+    minItems: 5
+    maxItems: 5
+
+  power-domain-names:
+    minItems: 5
+    maxItems: 5
+    items:
+      - bus
+      - csi-bridge
+      - lcdif
+      - mipi-dsi
+      - mipi-csi
+
+  clocks:
+    minItems: 10
+    maxItems: 10
+
+  clock-names:
+    minItems: 10
+    maxItems: 10
+    items:
+      - csi-bridge-axi
+      - csi-bridge-apb
+      - csi-bridge-core
+      - lcdif-axi
+      - lcdif-apb
+      - lcdif-pix
+      - dsi-pclk
+      - dsi-ref
+      - csi-aclk
+      - csi-pclk
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mm-clock.h>
+    #include <dt-bindings/power/imx8mm-power.h
+
+    disp_blk_ctl: blk_ctrl@32e28000 {
+      compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
+      reg = <0x32e28000 0x100>;
+      power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>,
+                      <&pgc_mipi>, <&pgc_mipi>;
+      power-domain-names = "bus", "csi-bridge", "lcdif",
+                           "mipi-dsi", "mipi-csi";
+      clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+               <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+               <&clk IMX8MM_CLK_CSI1_ROOT>,
+               <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+               <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+               <&clk IMX8MM_CLK_DISP_ROOT>,
+               <&clk IMX8MM_CLK_DSI_CORE>,
+               <&clk IMX8MM_CLK_DSI_PHY_REF>,
+               <&clk IMX8MM_CLK_CSI1_CORE>,
+               <&clk IMX8MM_CLK_CSI1_PHY_REF>;
+       clock-names = "csi-bridge-axi","csi-bridge-apb", "csi-bridge-core",
+                     "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
+                     "dsi-ref","csi-aclk", "csi-pclk";
+       #power-domain-cells = <1>;
+    };
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 11/17] dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the defines for the power domains provided by the DISP
blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 include/dt-bindings/power/imx8mm-power.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
index 38b0a56fd7d0..d7f7cdb5200f 100644
--- a/include/dt-bindings/power/imx8mm-power.h
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -23,4 +23,9 @@
 #define IMX8MM_VPUBLK_PD_G2		1
 #define IMX8MM_VPUBLK_PD_H1		2
 
+#define IMX8MM_DISPBLK_CSI_BRIDGE	0
+#define IMX8MM_DISPBLK_LCDIF		1
+#define IMX8MM_DISPBLK_MIPI_DSI		2
+#define IMX8MM_DISPBLK_MIPI_CSI		3
+
 #endif
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 11/17] dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the defines for the power domains provided by the DISP
blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 include/dt-bindings/power/imx8mm-power.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
index 38b0a56fd7d0..d7f7cdb5200f 100644
--- a/include/dt-bindings/power/imx8mm-power.h
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -23,4 +23,9 @@
 #define IMX8MM_VPUBLK_PD_G2		1
 #define IMX8MM_VPUBLK_PD_H1		2
 
+#define IMX8MM_DISPBLK_CSI_BRIDGE	0
+#define IMX8MM_DISPBLK_LCDIF		1
+#define IMX8MM_DISPBLK_MIPI_DSI		2
+#define IMX8MM_DISPBLK_MIPI_CSI		3
+
 #endif
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 12/17] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the description for the i.MX8MM disp blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/imx8m-blk-ctrl.c | 70 ++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 90ff845b2643..81315e71d3be 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -373,11 +373,81 @@ static const struct imx8m_blk_ctrl_data imx8m_vpu_blk_ctl_dev_data = {
 	.num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
 };
 
+static int imx8mm_disp_power_notifier(struct notifier_block *nb,
+				      unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/* Enable bus clock and deassert bus reset */
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12));
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6));
+
+	/*
+	 * On power up we have no software backchannel to the GPC to
+	 * wait for the ADB handshake to happen, so we just delay for a
+	 * bit. On power down the GPC driver waits for the handshake.
+	 */
+	if (action == GENPD_NOTIFY_ON)
+		udelay(5);
+
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8m_blk_ctrl_domain_data imx8m_disp_blk_ctl_domain_data[] = {
+	[IMX8MM_DISPBLK_CSI_BRIDGE] = {
+		.name = "dispblk-csi-bridge",
+		.clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb",
+					       "csi-bridge-core", },
+		.num_clks = 3,
+		.gpc_name = "csi-bridge",
+		.rst_mask = BIT(0) | BIT(1) | BIT(2),
+		.clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
+	},
+	[IMX8MM_DISPBLK_LCDIF] = {
+		.name = "dispblk-lcdif",
+		.clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
+		.num_clks = 3,
+		.gpc_name = "lcdif",
+		.clk_mask = BIT(6) | BIT(7),
+	},
+	[IMX8MM_DISPBLK_MIPI_DSI] = {
+		.name = "dispblk-mipi-dsi",
+		.clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
+		.num_clks = 2,
+		.gpc_name = "mipi-dsi",
+		.rst_mask = BIT(5),
+		.clk_mask = BIT(8) | BIT(9),
+	},
+	[IMX8MM_DISPBLK_MIPI_CSI] = {
+		.name = "dispblk-mipi-csi",
+		.clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
+		.num_clks = 2,
+		.gpc_name = "mipi-csi",
+		.rst_mask = BIT(3) | BIT(4),
+		.clk_mask = BIT(10) | BIT(11),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8m_disp_blk_ctl_dev_data = {
+	.max_reg = 0x2c,
+	.power_notifier_fn = imx8mm_disp_power_notifier,
+	.domains = imx8m_disp_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8m_disp_blk_ctl_domain_data),
+};
+
 static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
 	{
 		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
 		.data = &imx8m_vpu_blk_ctl_dev_data
 	}, {
+		.compatible = "fsl,imx8mm-disp-blk-ctrl",
+		.data = &imx8m_disp_blk_ctl_dev_data
+	} ,{
 		/* Sentinel */
 	}
 };
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 12/17] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the description for the i.MX8MM disp blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/imx8m-blk-ctrl.c | 70 ++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 90ff845b2643..81315e71d3be 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -373,11 +373,81 @@ static const struct imx8m_blk_ctrl_data imx8m_vpu_blk_ctl_dev_data = {
 	.num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
 };
 
+static int imx8mm_disp_power_notifier(struct notifier_block *nb,
+				      unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/* Enable bus clock and deassert bus reset */
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12));
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6));
+
+	/*
+	 * On power up we have no software backchannel to the GPC to
+	 * wait for the ADB handshake to happen, so we just delay for a
+	 * bit. On power down the GPC driver waits for the handshake.
+	 */
+	if (action == GENPD_NOTIFY_ON)
+		udelay(5);
+
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8m_blk_ctrl_domain_data imx8m_disp_blk_ctl_domain_data[] = {
+	[IMX8MM_DISPBLK_CSI_BRIDGE] = {
+		.name = "dispblk-csi-bridge",
+		.clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb",
+					       "csi-bridge-core", },
+		.num_clks = 3,
+		.gpc_name = "csi-bridge",
+		.rst_mask = BIT(0) | BIT(1) | BIT(2),
+		.clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
+	},
+	[IMX8MM_DISPBLK_LCDIF] = {
+		.name = "dispblk-lcdif",
+		.clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
+		.num_clks = 3,
+		.gpc_name = "lcdif",
+		.clk_mask = BIT(6) | BIT(7),
+	},
+	[IMX8MM_DISPBLK_MIPI_DSI] = {
+		.name = "dispblk-mipi-dsi",
+		.clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
+		.num_clks = 2,
+		.gpc_name = "mipi-dsi",
+		.rst_mask = BIT(5),
+		.clk_mask = BIT(8) | BIT(9),
+	},
+	[IMX8MM_DISPBLK_MIPI_CSI] = {
+		.name = "dispblk-mipi-csi",
+		.clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
+		.num_clks = 2,
+		.gpc_name = "mipi-csi",
+		.rst_mask = BIT(3) | BIT(4),
+		.clk_mask = BIT(10) | BIT(11),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8m_disp_blk_ctl_dev_data = {
+	.max_reg = 0x2c,
+	.power_notifier_fn = imx8mm_disp_power_notifier,
+	.domains = imx8m_disp_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8m_disp_blk_ctl_domain_data),
+};
+
 static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
 	{
 		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
 		.data = &imx8m_vpu_blk_ctl_dev_data
 	}, {
+		.compatible = "fsl,imx8mm-disp-blk-ctrl",
+		.data = &imx8m_disp_blk_ctl_dev_data
+	} ,{
 		/* Sentinel */
 	}
 };
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 13/17] arm64: dts: imx8mm: add GPC node
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Add the DT node for the GPC, including all the PGC power domains,
some of them are not fully functional yet, as they require interaction
with the blk-ctrls to properly power up/down the peripherals.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 107 ++++++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a27e02bee6b4..1cdb475b5895 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -7,6 +7,8 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/imx8mm-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/thermal/thermal.h>
 
 #include "imx8mm-pinfunc.h"
@@ -600,6 +602,111 @@ src: reset-controller@30390000 {
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
+
+			gpc: gpc@303a0000 {
+				compatible = "fsl,imx8mm-gpc";
+				reg = <0x303a0000 0x10000>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&gic>;
+				interrupt-controller;
+				#interrupt-cells = <3>;
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pgc_hsiomix: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
+						clocks = <&clk IMX8MM_CLK_USB_BUS>;
+						assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
+					};
+
+					pgc_pcie: power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_PCIE>;
+						power-domains = <&pgc_hsiomix>;
+						clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
+					};
+
+					pgc_otg1: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_OTG1>;
+						power-domains = <&pgc_hsiomix>;
+					};
+
+					pgc_otg2: power-domain@3 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_OTG2>;
+						power-domains = <&pgc_hsiomix>;
+					};
+
+					pgc_gpumix: power-domain@4 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
+						clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+							 <&clk IMX8MM_CLK_GPU_AHB>;
+						assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
+								  <&clk IMX8MM_CLK_GPU_AHB>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
+									 <&clk IMX8MM_SYS_PLL1_800M>;
+						assigned-clock-rates = <800000000>, <400000000>;
+					};
+
+					pgc_gpu: power-domain@5 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_GPU>;
+						clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+							 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+							 <&clk IMX8MM_CLK_GPU2D_ROOT>,
+							 <&clk IMX8MM_CLK_GPU3D_ROOT>;
+						resets = <&src IMX8MQ_RESET_GPU_RESET>;
+						power-domains = <&pgc_gpumix>;
+					};
+
+					pgc_vpumix: power-domain@6 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
+						clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
+						assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
+						resets = <&src IMX8MQ_RESET_VPU_RESET>;
+					};
+
+					pgc_vpu_g1: power-domain@7 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
+					};
+
+					pgc_vpu_g2: power-domain@8 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
+					};
+
+					pgc_vpu_h1: power-domain@9 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
+					};
+
+					pgc_dispmix: power-domain@10 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
+						clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+							 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
+						assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
+								  <&clk IMX8MM_CLK_DISP_APB>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
+									 <&clk IMX8MM_SYS_PLL1_800M>;
+						assigned-clock-rates = <500000000>, <200000000>;
+					};
+
+					pgc_mipi: power-domain@11 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_MIPI>;
+					};
+				};
+			};
 		};
 
 		aips2: bus@30400000 {
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 13/17] arm64: dts: imx8mm: add GPC node
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Add the DT node for the GPC, including all the PGC power domains,
some of them are not fully functional yet, as they require interaction
with the blk-ctrls to properly power up/down the peripherals.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 107 ++++++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a27e02bee6b4..1cdb475b5895 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -7,6 +7,8 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/imx8mm-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/thermal/thermal.h>
 
 #include "imx8mm-pinfunc.h"
@@ -600,6 +602,111 @@ src: reset-controller@30390000 {
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
+
+			gpc: gpc@303a0000 {
+				compatible = "fsl,imx8mm-gpc";
+				reg = <0x303a0000 0x10000>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&gic>;
+				interrupt-controller;
+				#interrupt-cells = <3>;
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pgc_hsiomix: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
+						clocks = <&clk IMX8MM_CLK_USB_BUS>;
+						assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
+					};
+
+					pgc_pcie: power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_PCIE>;
+						power-domains = <&pgc_hsiomix>;
+						clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
+					};
+
+					pgc_otg1: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_OTG1>;
+						power-domains = <&pgc_hsiomix>;
+					};
+
+					pgc_otg2: power-domain@3 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_OTG2>;
+						power-domains = <&pgc_hsiomix>;
+					};
+
+					pgc_gpumix: power-domain@4 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
+						clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+							 <&clk IMX8MM_CLK_GPU_AHB>;
+						assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
+								  <&clk IMX8MM_CLK_GPU_AHB>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
+									 <&clk IMX8MM_SYS_PLL1_800M>;
+						assigned-clock-rates = <800000000>, <400000000>;
+					};
+
+					pgc_gpu: power-domain@5 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_GPU>;
+						clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+							 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+							 <&clk IMX8MM_CLK_GPU2D_ROOT>,
+							 <&clk IMX8MM_CLK_GPU3D_ROOT>;
+						resets = <&src IMX8MQ_RESET_GPU_RESET>;
+						power-domains = <&pgc_gpumix>;
+					};
+
+					pgc_vpumix: power-domain@6 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
+						clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
+						assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
+						resets = <&src IMX8MQ_RESET_VPU_RESET>;
+					};
+
+					pgc_vpu_g1: power-domain@7 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
+					};
+
+					pgc_vpu_g2: power-domain@8 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
+					};
+
+					pgc_vpu_h1: power-domain@9 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
+					};
+
+					pgc_dispmix: power-domain@10 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
+						clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+							 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
+						assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
+								  <&clk IMX8MM_CLK_DISP_APB>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
+									 <&clk IMX8MM_SYS_PLL1_800M>;
+						assigned-clock-rates = <500000000>, <200000000>;
+					};
+
+					pgc_mipi: power-domain@11 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_MIPI>;
+					};
+				};
+			};
 		};
 
 		aips2: bus@30400000 {
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 14/17] arm64: dts: imx8mm: put USB controllers into power-domains
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Now that we have support for the power domain controller on the i.MX8MM
we can put the USB controllers in their respective power domains to allow
them to power down the PHY when possible.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 1cdb475b5895..39d651612d0e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1060,6 +1060,7 @@ usbotg1: usb@32e40000 {
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				fsl,usbphy = <&usbphynop1>;
 				fsl,usbmisc = <&usbmisc1 0>;
+				power-domains = <&pgc_otg1>;
 				status = "disabled";
 			};
 
@@ -1079,6 +1080,7 @@ usbotg2: usb@32e50000 {
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				fsl,usbphy = <&usbphynop2>;
 				fsl,usbmisc = <&usbmisc2 0>;
+				power-domains = <&pgc_otg2>;
 				status = "disabled";
 			};
 
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 14/17] arm64: dts: imx8mm: put USB controllers into power-domains
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Now that we have support for the power domain controller on the i.MX8MM
we can put the USB controllers in their respective power domains to allow
them to power down the PHY when possible.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 1cdb475b5895..39d651612d0e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1060,6 +1060,7 @@ usbotg1: usb@32e40000 {
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				fsl,usbphy = <&usbphynop1>;
 				fsl,usbmisc = <&usbmisc1 0>;
+				power-domains = <&pgc_otg1>;
 				status = "disabled";
 			};
 
@@ -1079,6 +1080,7 @@ usbotg2: usb@32e50000 {
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				fsl,usbphy = <&usbphynop2>;
 				fsl,usbmisc = <&usbmisc2 0>;
+				power-domains = <&pgc_otg2>;
 				status = "disabled";
 			};
 
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 15/17] arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

From: Frieder Schrempf <frieder.schrempf@kontron.de>

According to the documents, the i.MX8M-Mini features a GC320 and a
GCNanoUltra GPU core. Etnaviv detects them as:

	etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653
	etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341

This seems to work fine more or less without any changes to the HWDB,
which still might be needed in the future to correct some features,
etc.

[lst]: Added power domains and switched clock assignments to the
       new clock defines used for the composite clocks, instead of
       relying on the backwards compat defines.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 31 +++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 39d651612d0e..a937018556a1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1121,6 +1121,37 @@ gpmi: nand-controller@33002000{
 			status = "disabled";
 		};
 
+		gpu_3d: gpu@38000000 {
+			compatible = "vivante,gc";
+			reg = <0x38000000 0x8000>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+				 <&clk IMX8MM_CLK_GPU3D_ROOT>,
+				 <&clk IMX8MM_CLK_GPU3D_ROOT>;
+			clock-names = "reg", "bus", "core", "shader";
+			assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
+					  <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-rates = <0>, <1000000000>;
+			power-domains = <&pgc_gpu>;
+		};
+
+		gpu_2d: gpu@38008000 {
+			compatible = "vivante,gc";
+			reg = <0x38008000 0x8000>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+				 <&clk IMX8MM_CLK_GPU2D_ROOT>;
+			clock-names = "reg", "bus", "core";
+			assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
+					  <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-rates = <0>, <1000000000>;
+			power-domains = <&pgc_gpu>;
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>, /* GIC Dist */
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 15/17] arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

From: Frieder Schrempf <frieder.schrempf@kontron.de>

According to the documents, the i.MX8M-Mini features a GC320 and a
GCNanoUltra GPU core. Etnaviv detects them as:

	etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653
	etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341

This seems to work fine more or less without any changes to the HWDB,
which still might be needed in the future to correct some features,
etc.

[lst]: Added power domains and switched clock assignments to the
       new clock defines used for the composite clocks, instead of
       relying on the backwards compat defines.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 31 +++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 39d651612d0e..a937018556a1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1121,6 +1121,37 @@ gpmi: nand-controller@33002000{
 			status = "disabled";
 		};
 
+		gpu_3d: gpu@38000000 {
+			compatible = "vivante,gc";
+			reg = <0x38000000 0x8000>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+				 <&clk IMX8MM_CLK_GPU3D_ROOT>,
+				 <&clk IMX8MM_CLK_GPU3D_ROOT>;
+			clock-names = "reg", "bus", "core", "shader";
+			assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
+					  <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-rates = <0>, <1000000000>;
+			power-domains = <&pgc_gpu>;
+		};
+
+		gpu_2d: gpu@38008000 {
+			compatible = "vivante,gc";
+			reg = <0x38008000 0x8000>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+				 <&clk IMX8MM_CLK_GPU2D_ROOT>;
+			clock-names = "reg", "bus", "core";
+			assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
+					  <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-rates = <0>, <1000000000>;
+			power-domains = <&pgc_gpu>;
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>, /* GIC Dist */
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 16/17] arm64: dts: imx8mm: add VPU blk-ctrl
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Add the DT node for the VPU blk-ctrl. With this in place the
VPU power domains are fully functional.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a937018556a1..fdca74ece767 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1152,6 +1152,19 @@ gpu_2d: gpu@38008000 {
 			power-domains = <&pgc_gpu>;
 		};
 
+		vpu_blk_ctrl: blk-ctrl@38330000 {
+			compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
+			reg = <0x38330000 0x100>;
+			power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
+					<&pgc_vpu_g2>, <&pgc_vpu_h1>;
+			power-domain-names = "bus", "g1", "g2", "h1";
+			clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
+				 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
+				 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
+			clock-names = "g1", "g2", "h1";
+			#power-domain-cells = <1>;
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>, /* GIC Dist */
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 16/17] arm64: dts: imx8mm: add VPU blk-ctrl
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Add the DT node for the VPU blk-ctrl. With this in place the
VPU power domains are fully functional.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a937018556a1..fdca74ece767 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1152,6 +1152,19 @@ gpu_2d: gpu@38008000 {
 			power-domains = <&pgc_gpu>;
 		};
 
+		vpu_blk_ctrl: blk-ctrl@38330000 {
+			compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
+			reg = <0x38330000 0x100>;
+			power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
+					<&pgc_vpu_g2>, <&pgc_vpu_h1>;
+			power-domain-names = "bus", "g1", "g2", "h1";
+			clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
+				 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
+				 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
+			clock-names = "g1", "g2", "h1";
+			#power-domain-cells = <1>;
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>, /* GIC Dist */
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 17/17] arm64: dts: imx8mm: add DISP blk-ctrl
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-16 23:29   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Add the DT node for the DISP blk-ctrl. With this in place the
display/mipi power domains are fully functional.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 27 +++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index fdca74ece767..72688c578b3f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1050,6 +1050,33 @@ aips4: bus@32c00000 {
 			#size-cells = <1>;
 			ranges = <0x32c00000 0x32c00000 0x400000>;
 
+			disp_blk_ctrl: blk-ctrl@32e28000 {
+				compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
+				reg = <0x32e28000 0x100>;
+				power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
+						<&pgc_dispmix>, <&pgc_mipi>,
+						<&pgc_mipi>;
+				power-domain-names = "bus", "csi-bridge",
+						     "lcdif", "mipi-dsi",
+						     "mipi-csi";
+				clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MM_CLK_CSI1_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_ROOT>,
+					 <&clk IMX8MM_CLK_DSI_CORE>,
+					 <&clk IMX8MM_CLK_DSI_PHY_REF>,
+					 <&clk IMX8MM_CLK_CSI1_CORE>,
+					 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
+				clock-names = "csi-bridge-axi","csi-bridge-apb",
+					      "csi-bridge-core", "lcdif-axi",
+					      "lcdif-apb", "lcdif-pix",
+					      "dsi-pclk", "dsi-ref",
+					      "csi-aclk", "csi-pclk";
+				#power-domain-cells = <1>;
+			};
+
 			usbotg1: usb@32e40000 {
 				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
 				reg = <0x32e40000 0x200>;
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH 17/17] arm64: dts: imx8mm: add DISP blk-ctrl
@ 2021-07-16 23:29   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-16 23:29 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Add the DT node for the DISP blk-ctrl. With this in place the
display/mipi power domains are fully functional.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 27 +++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index fdca74ece767..72688c578b3f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1050,6 +1050,33 @@ aips4: bus@32c00000 {
 			#size-cells = <1>;
 			ranges = <0x32c00000 0x32c00000 0x400000>;
 
+			disp_blk_ctrl: blk-ctrl@32e28000 {
+				compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
+				reg = <0x32e28000 0x100>;
+				power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
+						<&pgc_dispmix>, <&pgc_mipi>,
+						<&pgc_mipi>;
+				power-domain-names = "bus", "csi-bridge",
+						     "lcdif", "mipi-dsi",
+						     "mipi-csi";
+				clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MM_CLK_CSI1_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_ROOT>,
+					 <&clk IMX8MM_CLK_DSI_CORE>,
+					 <&clk IMX8MM_CLK_DSI_PHY_REF>,
+					 <&clk IMX8MM_CLK_CSI1_CORE>,
+					 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
+				clock-names = "csi-bridge-axi","csi-bridge-apb",
+					      "csi-bridge-core", "lcdif-axi",
+					      "lcdif-apb", "lcdif-pix",
+					      "dsi-pclk", "dsi-ref",
+					      "csi-aclk", "csi-pclk";
+				#power-domain-cells = <1>;
+			};
+
 			usbotg1: usb@32e40000 {
 				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
 				reg = <0x32e40000 0x200>;
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH 09/17] soc: imx: add i.MX8M blk-ctrl driver
  2021-07-16 23:29   ` Lucas Stach
@ 2021-07-19  6:12     ` Dan Carpenter
  -1 siblings, 0 replies; 136+ messages in thread
From: Dan Carpenter @ 2021-07-19  6:12 UTC (permalink / raw)
  To: kbuild, Lucas Stach, Shawn Guo, Rob Herring
  Cc: lkp, kbuild-all, NXP Linux Team, Adam Ford, Frieder Schrempf,
	Peng Fan, Marek Vasut, devicetree, linux-arm-kernel, kernel

Hi Lucas,

url:    https://github.com/0day-ci/linux/commits/Lucas-Stach/i-MX8MM-GPC-improvements-and-BLK_CTRL-driver/20210718-102944
base:   https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
config: i386-randconfig-m021-20210718 (attached as .config)
compiler: gcc-10 (Ubuntu 10.3.0-1ubuntu1~20.04) 10.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/soc/imx/imx8m-blk-ctrl.c:222 imx8m_blk_ctrl_probe() warn: missing error code 'ret'

vim +/ret +222 drivers/soc/imx/imx8m-blk-ctrl.c

446185fda14696 Lucas Stach 2021-07-17  150  static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
446185fda14696 Lucas Stach 2021-07-17  151  {
446185fda14696 Lucas Stach 2021-07-17  152  	const struct imx8m_blk_ctrl_data *bc_data;
446185fda14696 Lucas Stach 2021-07-17  153  	struct device *dev = &pdev->dev;
446185fda14696 Lucas Stach 2021-07-17  154  	struct imx8m_blk_ctrl *bc;
446185fda14696 Lucas Stach 2021-07-17  155  	void __iomem *base;
446185fda14696 Lucas Stach 2021-07-17  156  	int i, ret;
446185fda14696 Lucas Stach 2021-07-17  157  
446185fda14696 Lucas Stach 2021-07-17  158  	struct regmap_config regmap_config = {
446185fda14696 Lucas Stach 2021-07-17  159  		.reg_bits	= 32,
446185fda14696 Lucas Stach 2021-07-17  160  		.val_bits	= 32,
446185fda14696 Lucas Stach 2021-07-17  161  		.reg_stride	= 4,
446185fda14696 Lucas Stach 2021-07-17  162  	};
446185fda14696 Lucas Stach 2021-07-17  163  
446185fda14696 Lucas Stach 2021-07-17  164  	bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
446185fda14696 Lucas Stach 2021-07-17  165  	if (!bc)
446185fda14696 Lucas Stach 2021-07-17  166  		return -ENOMEM;
446185fda14696 Lucas Stach 2021-07-17  167  
446185fda14696 Lucas Stach 2021-07-17  168  	bc->dev = dev;
446185fda14696 Lucas Stach 2021-07-17  169  
446185fda14696 Lucas Stach 2021-07-17  170  	bc_data = of_device_get_match_data(dev);
446185fda14696 Lucas Stach 2021-07-17  171  
446185fda14696 Lucas Stach 2021-07-17  172  	base = devm_platform_ioremap_resource(pdev, 0);
446185fda14696 Lucas Stach 2021-07-17  173  	if (IS_ERR(base))
446185fda14696 Lucas Stach 2021-07-17  174  		return PTR_ERR(base);
446185fda14696 Lucas Stach 2021-07-17  175  
446185fda14696 Lucas Stach 2021-07-17  176  	regmap_config.max_register = bc_data->max_reg;
446185fda14696 Lucas Stach 2021-07-17  177  	bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
446185fda14696 Lucas Stach 2021-07-17  178  	if (IS_ERR(bc->regmap))
446185fda14696 Lucas Stach 2021-07-17  179  		return dev_err_probe(dev, PTR_ERR(bc->regmap),
446185fda14696 Lucas Stach 2021-07-17  180  				     "failed to init regmap \n");
446185fda14696 Lucas Stach 2021-07-17  181  
446185fda14696 Lucas Stach 2021-07-17  182  	bc->domains = devm_kcalloc(dev, bc_data->num_domains,
446185fda14696 Lucas Stach 2021-07-17  183  				    sizeof(struct imx8m_blk_ctrl_domain),
446185fda14696 Lucas Stach 2021-07-17  184  				    GFP_KERNEL);
446185fda14696 Lucas Stach 2021-07-17  185  	if (!bc->domains)
446185fda14696 Lucas Stach 2021-07-17  186  		return -ENOMEM;
446185fda14696 Lucas Stach 2021-07-17  187  
446185fda14696 Lucas Stach 2021-07-17  188  	bc->onecell_data.num_domains = bc_data->num_domains;
446185fda14696 Lucas Stach 2021-07-17  189  	bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
446185fda14696 Lucas Stach 2021-07-17  190  	bc->onecell_data.domains =
446185fda14696 Lucas Stach 2021-07-17  191  		devm_kcalloc(dev, bc_data->num_domains,
446185fda14696 Lucas Stach 2021-07-17  192  			     sizeof(struct generic_pm_domain *), GFP_KERNEL);
446185fda14696 Lucas Stach 2021-07-17  193  	if (!bc->onecell_data.domains)
446185fda14696 Lucas Stach 2021-07-17  194  		return -ENOMEM;
446185fda14696 Lucas Stach 2021-07-17  195  
446185fda14696 Lucas Stach 2021-07-17  196  	bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
446185fda14696 Lucas Stach 2021-07-17  197  	if (IS_ERR(bc->bus_power_dev))
446185fda14696 Lucas Stach 2021-07-17  198  		return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
446185fda14696 Lucas Stach 2021-07-17  199  				     "failed to attach power domain\n");
446185fda14696 Lucas Stach 2021-07-17  200  
446185fda14696 Lucas Stach 2021-07-17  201  	for (i = 0; i < bc_data->num_domains; i++) {
446185fda14696 Lucas Stach 2021-07-17  202  		const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i];
446185fda14696 Lucas Stach 2021-07-17  203  		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
446185fda14696 Lucas Stach 2021-07-17  204  		int j;
446185fda14696 Lucas Stach 2021-07-17  205  
446185fda14696 Lucas Stach 2021-07-17  206  		domain->data = data;
446185fda14696 Lucas Stach 2021-07-17  207  
446185fda14696 Lucas Stach 2021-07-17  208  		for (j = 0; j < data->num_clks; j++)
446185fda14696 Lucas Stach 2021-07-17  209  			domain->clks[j].id = data->clk_names[j];
446185fda14696 Lucas Stach 2021-07-17  210  
446185fda14696 Lucas Stach 2021-07-17  211  		ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
446185fda14696 Lucas Stach 2021-07-17  212  		if (ret) {
446185fda14696 Lucas Stach 2021-07-17  213  			dev_err_probe(dev, ret, "failed to get clock\n");
446185fda14696 Lucas Stach 2021-07-17  214  			goto cleanup_pds;
446185fda14696 Lucas Stach 2021-07-17  215  		}
446185fda14696 Lucas Stach 2021-07-17  216  
446185fda14696 Lucas Stach 2021-07-17  217  		domain->power_dev =
446185fda14696 Lucas Stach 2021-07-17  218  			dev_pm_domain_attach_by_name(dev, data->gpc_name);
446185fda14696 Lucas Stach 2021-07-17  219  		if (IS_ERR(domain->power_dev )) {
                                                                                    ^
Extra space character.

446185fda14696 Lucas Stach 2021-07-17  220  			dev_err_probe(dev, PTR_ERR(domain->power_dev),
446185fda14696 Lucas Stach 2021-07-17  221  				      "failed to attach power domain\n");
446185fda14696 Lucas Stach 2021-07-17 @222  			goto cleanup_pds;

	ret = PTR_ERR(domain->power_dev);

446185fda14696 Lucas Stach 2021-07-17  223  		}
446185fda14696 Lucas Stach 2021-07-17  224  
446185fda14696 Lucas Stach 2021-07-17  225  		domain->genpd.name = data->name;
446185fda14696 Lucas Stach 2021-07-17  226  		domain->genpd.power_on = imx8m_blk_ctrl_power_on;
446185fda14696 Lucas Stach 2021-07-17  227  		domain->genpd.power_off = imx8m_blk_ctrl_power_off;
446185fda14696 Lucas Stach 2021-07-17  228  		domain->bc = bc;
446185fda14696 Lucas Stach 2021-07-17  229  
446185fda14696 Lucas Stach 2021-07-17  230  		ret = pm_genpd_init(&domain->genpd, NULL, true);
446185fda14696 Lucas Stach 2021-07-17  231  		if (ret) {
446185fda14696 Lucas Stach 2021-07-17  232  			dev_err_probe(dev, ret, "failed to init power domain\n");
446185fda14696 Lucas Stach 2021-07-17  233  			dev_pm_domain_detach(domain->power_dev, true);
446185fda14696 Lucas Stach 2021-07-17  234  			goto cleanup_pds;
446185fda14696 Lucas Stach 2021-07-17  235  		}
446185fda14696 Lucas Stach 2021-07-17  236  
446185fda14696 Lucas Stach 2021-07-17  237  		/*
446185fda14696 Lucas Stach 2021-07-17  238  		 * We use runtime PM to trigger power on/off of the upstream GPC
446185fda14696 Lucas Stach 2021-07-17  239  		 * domain, as a strict hierarchical parent/child power domain
446185fda14696 Lucas Stach 2021-07-17  240  		 * setup doesn't allow us to meet the sequencing requirements.
446185fda14696 Lucas Stach 2021-07-17  241  		 * This means we have nested locking of genpd locks, without the
446185fda14696 Lucas Stach 2021-07-17  242  		 * nesting being visible at the genpd level, so we need a
446185fda14696 Lucas Stach 2021-07-17  243  		 * separate lock class to make lockdep aware of the fact that
446185fda14696 Lucas Stach 2021-07-17  244  		 * this are separate domain locks that can be nested without a
446185fda14696 Lucas Stach 2021-07-17  245  		 * self-deadlock.
446185fda14696 Lucas Stach 2021-07-17  246  		 */
446185fda14696 Lucas Stach 2021-07-17  247  		lockdep_set_class(&domain->genpd.mlock,
446185fda14696 Lucas Stach 2021-07-17  248  				  &blk_ctrl_genpd_lock_class);
446185fda14696 Lucas Stach 2021-07-17  249  
446185fda14696 Lucas Stach 2021-07-17  250  		bc->onecell_data.domains[i] = &domain->genpd;
446185fda14696 Lucas Stach 2021-07-17  251  	}
446185fda14696 Lucas Stach 2021-07-17  252  
446185fda14696 Lucas Stach 2021-07-17  253  	ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
446185fda14696 Lucas Stach 2021-07-17  254  	if (ret) {
446185fda14696 Lucas Stach 2021-07-17  255  		dev_err_probe(dev, ret, "failed to add power domain provider\n");
446185fda14696 Lucas Stach 2021-07-17  256  		goto cleanup_pds;
446185fda14696 Lucas Stach 2021-07-17  257  	}
446185fda14696 Lucas Stach 2021-07-17  258  
446185fda14696 Lucas Stach 2021-07-17  259  	bc->power_nb.notifier_call = bc_data->power_notifier_fn;
446185fda14696 Lucas Stach 2021-07-17  260  	ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
446185fda14696 Lucas Stach 2021-07-17  261  	if (ret) {
446185fda14696 Lucas Stach 2021-07-17  262  		dev_err_probe(dev, ret, "failed to add power notifier\n");
446185fda14696 Lucas Stach 2021-07-17  263  		goto cleanup_provider;
446185fda14696 Lucas Stach 2021-07-17  264  	}
446185fda14696 Lucas Stach 2021-07-17  265  
446185fda14696 Lucas Stach 2021-07-17  266  	dev_set_drvdata(dev, bc);
446185fda14696 Lucas Stach 2021-07-17  267  
446185fda14696 Lucas Stach 2021-07-17  268  	return 0;
446185fda14696 Lucas Stach 2021-07-17  269  
446185fda14696 Lucas Stach 2021-07-17  270  cleanup_provider:
446185fda14696 Lucas Stach 2021-07-17  271  	of_genpd_del_provider(dev->of_node);
446185fda14696 Lucas Stach 2021-07-17  272  cleanup_pds:
446185fda14696 Lucas Stach 2021-07-17  273  	for (i--; i >= 0; i--) {
446185fda14696 Lucas Stach 2021-07-17  274  		pm_genpd_remove(&bc->domains[i].genpd);
446185fda14696 Lucas Stach 2021-07-17  275  		dev_pm_domain_detach(bc->domains[i].power_dev, true);
446185fda14696 Lucas Stach 2021-07-17  276  	}
446185fda14696 Lucas Stach 2021-07-17  277  
446185fda14696 Lucas Stach 2021-07-17  278  	dev_pm_domain_detach(bc->bus_power_dev, true);
446185fda14696 Lucas Stach 2021-07-17  279  
446185fda14696 Lucas Stach 2021-07-17  280  	return ret;
446185fda14696 Lucas Stach 2021-07-17  281  }

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org


^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH 09/17] soc: imx: add i.MX8M blk-ctrl driver
@ 2021-07-19  6:12     ` Dan Carpenter
  0 siblings, 0 replies; 136+ messages in thread
From: Dan Carpenter @ 2021-07-19  6:12 UTC (permalink / raw)
  To: kbuild, Lucas Stach, Shawn Guo, Rob Herring
  Cc: lkp, kbuild-all, NXP Linux Team, Adam Ford, Frieder Schrempf,
	Peng Fan, Marek Vasut, devicetree, linux-arm-kernel, kernel

Hi Lucas,

url:    https://github.com/0day-ci/linux/commits/Lucas-Stach/i-MX8MM-GPC-improvements-and-BLK_CTRL-driver/20210718-102944
base:   https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
config: i386-randconfig-m021-20210718 (attached as .config)
compiler: gcc-10 (Ubuntu 10.3.0-1ubuntu1~20.04) 10.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/soc/imx/imx8m-blk-ctrl.c:222 imx8m_blk_ctrl_probe() warn: missing error code 'ret'

vim +/ret +222 drivers/soc/imx/imx8m-blk-ctrl.c

446185fda14696 Lucas Stach 2021-07-17  150  static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
446185fda14696 Lucas Stach 2021-07-17  151  {
446185fda14696 Lucas Stach 2021-07-17  152  	const struct imx8m_blk_ctrl_data *bc_data;
446185fda14696 Lucas Stach 2021-07-17  153  	struct device *dev = &pdev->dev;
446185fda14696 Lucas Stach 2021-07-17  154  	struct imx8m_blk_ctrl *bc;
446185fda14696 Lucas Stach 2021-07-17  155  	void __iomem *base;
446185fda14696 Lucas Stach 2021-07-17  156  	int i, ret;
446185fda14696 Lucas Stach 2021-07-17  157  
446185fda14696 Lucas Stach 2021-07-17  158  	struct regmap_config regmap_config = {
446185fda14696 Lucas Stach 2021-07-17  159  		.reg_bits	= 32,
446185fda14696 Lucas Stach 2021-07-17  160  		.val_bits	= 32,
446185fda14696 Lucas Stach 2021-07-17  161  		.reg_stride	= 4,
446185fda14696 Lucas Stach 2021-07-17  162  	};
446185fda14696 Lucas Stach 2021-07-17  163  
446185fda14696 Lucas Stach 2021-07-17  164  	bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
446185fda14696 Lucas Stach 2021-07-17  165  	if (!bc)
446185fda14696 Lucas Stach 2021-07-17  166  		return -ENOMEM;
446185fda14696 Lucas Stach 2021-07-17  167  
446185fda14696 Lucas Stach 2021-07-17  168  	bc->dev = dev;
446185fda14696 Lucas Stach 2021-07-17  169  
446185fda14696 Lucas Stach 2021-07-17  170  	bc_data = of_device_get_match_data(dev);
446185fda14696 Lucas Stach 2021-07-17  171  
446185fda14696 Lucas Stach 2021-07-17  172  	base = devm_platform_ioremap_resource(pdev, 0);
446185fda14696 Lucas Stach 2021-07-17  173  	if (IS_ERR(base))
446185fda14696 Lucas Stach 2021-07-17  174  		return PTR_ERR(base);
446185fda14696 Lucas Stach 2021-07-17  175  
446185fda14696 Lucas Stach 2021-07-17  176  	regmap_config.max_register = bc_data->max_reg;
446185fda14696 Lucas Stach 2021-07-17  177  	bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
446185fda14696 Lucas Stach 2021-07-17  178  	if (IS_ERR(bc->regmap))
446185fda14696 Lucas Stach 2021-07-17  179  		return dev_err_probe(dev, PTR_ERR(bc->regmap),
446185fda14696 Lucas Stach 2021-07-17  180  				     "failed to init regmap \n");
446185fda14696 Lucas Stach 2021-07-17  181  
446185fda14696 Lucas Stach 2021-07-17  182  	bc->domains = devm_kcalloc(dev, bc_data->num_domains,
446185fda14696 Lucas Stach 2021-07-17  183  				    sizeof(struct imx8m_blk_ctrl_domain),
446185fda14696 Lucas Stach 2021-07-17  184  				    GFP_KERNEL);
446185fda14696 Lucas Stach 2021-07-17  185  	if (!bc->domains)
446185fda14696 Lucas Stach 2021-07-17  186  		return -ENOMEM;
446185fda14696 Lucas Stach 2021-07-17  187  
446185fda14696 Lucas Stach 2021-07-17  188  	bc->onecell_data.num_domains = bc_data->num_domains;
446185fda14696 Lucas Stach 2021-07-17  189  	bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
446185fda14696 Lucas Stach 2021-07-17  190  	bc->onecell_data.domains =
446185fda14696 Lucas Stach 2021-07-17  191  		devm_kcalloc(dev, bc_data->num_domains,
446185fda14696 Lucas Stach 2021-07-17  192  			     sizeof(struct generic_pm_domain *), GFP_KERNEL);
446185fda14696 Lucas Stach 2021-07-17  193  	if (!bc->onecell_data.domains)
446185fda14696 Lucas Stach 2021-07-17  194  		return -ENOMEM;
446185fda14696 Lucas Stach 2021-07-17  195  
446185fda14696 Lucas Stach 2021-07-17  196  	bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
446185fda14696 Lucas Stach 2021-07-17  197  	if (IS_ERR(bc->bus_power_dev))
446185fda14696 Lucas Stach 2021-07-17  198  		return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
446185fda14696 Lucas Stach 2021-07-17  199  				     "failed to attach power domain\n");
446185fda14696 Lucas Stach 2021-07-17  200  
446185fda14696 Lucas Stach 2021-07-17  201  	for (i = 0; i < bc_data->num_domains; i++) {
446185fda14696 Lucas Stach 2021-07-17  202  		const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i];
446185fda14696 Lucas Stach 2021-07-17  203  		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
446185fda14696 Lucas Stach 2021-07-17  204  		int j;
446185fda14696 Lucas Stach 2021-07-17  205  
446185fda14696 Lucas Stach 2021-07-17  206  		domain->data = data;
446185fda14696 Lucas Stach 2021-07-17  207  
446185fda14696 Lucas Stach 2021-07-17  208  		for (j = 0; j < data->num_clks; j++)
446185fda14696 Lucas Stach 2021-07-17  209  			domain->clks[j].id = data->clk_names[j];
446185fda14696 Lucas Stach 2021-07-17  210  
446185fda14696 Lucas Stach 2021-07-17  211  		ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
446185fda14696 Lucas Stach 2021-07-17  212  		if (ret) {
446185fda14696 Lucas Stach 2021-07-17  213  			dev_err_probe(dev, ret, "failed to get clock\n");
446185fda14696 Lucas Stach 2021-07-17  214  			goto cleanup_pds;
446185fda14696 Lucas Stach 2021-07-17  215  		}
446185fda14696 Lucas Stach 2021-07-17  216  
446185fda14696 Lucas Stach 2021-07-17  217  		domain->power_dev =
446185fda14696 Lucas Stach 2021-07-17  218  			dev_pm_domain_attach_by_name(dev, data->gpc_name);
446185fda14696 Lucas Stach 2021-07-17  219  		if (IS_ERR(domain->power_dev )) {
                                                                                    ^
Extra space character.

446185fda14696 Lucas Stach 2021-07-17  220  			dev_err_probe(dev, PTR_ERR(domain->power_dev),
446185fda14696 Lucas Stach 2021-07-17  221  				      "failed to attach power domain\n");
446185fda14696 Lucas Stach 2021-07-17 @222  			goto cleanup_pds;

	ret = PTR_ERR(domain->power_dev);

446185fda14696 Lucas Stach 2021-07-17  223  		}
446185fda14696 Lucas Stach 2021-07-17  224  
446185fda14696 Lucas Stach 2021-07-17  225  		domain->genpd.name = data->name;
446185fda14696 Lucas Stach 2021-07-17  226  		domain->genpd.power_on = imx8m_blk_ctrl_power_on;
446185fda14696 Lucas Stach 2021-07-17  227  		domain->genpd.power_off = imx8m_blk_ctrl_power_off;
446185fda14696 Lucas Stach 2021-07-17  228  		domain->bc = bc;
446185fda14696 Lucas Stach 2021-07-17  229  
446185fda14696 Lucas Stach 2021-07-17  230  		ret = pm_genpd_init(&domain->genpd, NULL, true);
446185fda14696 Lucas Stach 2021-07-17  231  		if (ret) {
446185fda14696 Lucas Stach 2021-07-17  232  			dev_err_probe(dev, ret, "failed to init power domain\n");
446185fda14696 Lucas Stach 2021-07-17  233  			dev_pm_domain_detach(domain->power_dev, true);
446185fda14696 Lucas Stach 2021-07-17  234  			goto cleanup_pds;
446185fda14696 Lucas Stach 2021-07-17  235  		}
446185fda14696 Lucas Stach 2021-07-17  236  
446185fda14696 Lucas Stach 2021-07-17  237  		/*
446185fda14696 Lucas Stach 2021-07-17  238  		 * We use runtime PM to trigger power on/off of the upstream GPC
446185fda14696 Lucas Stach 2021-07-17  239  		 * domain, as a strict hierarchical parent/child power domain
446185fda14696 Lucas Stach 2021-07-17  240  		 * setup doesn't allow us to meet the sequencing requirements.
446185fda14696 Lucas Stach 2021-07-17  241  		 * This means we have nested locking of genpd locks, without the
446185fda14696 Lucas Stach 2021-07-17  242  		 * nesting being visible at the genpd level, so we need a
446185fda14696 Lucas Stach 2021-07-17  243  		 * separate lock class to make lockdep aware of the fact that
446185fda14696 Lucas Stach 2021-07-17  244  		 * this are separate domain locks that can be nested without a
446185fda14696 Lucas Stach 2021-07-17  245  		 * self-deadlock.
446185fda14696 Lucas Stach 2021-07-17  246  		 */
446185fda14696 Lucas Stach 2021-07-17  247  		lockdep_set_class(&domain->genpd.mlock,
446185fda14696 Lucas Stach 2021-07-17  248  				  &blk_ctrl_genpd_lock_class);
446185fda14696 Lucas Stach 2021-07-17  249  
446185fda14696 Lucas Stach 2021-07-17  250  		bc->onecell_data.domains[i] = &domain->genpd;
446185fda14696 Lucas Stach 2021-07-17  251  	}
446185fda14696 Lucas Stach 2021-07-17  252  
446185fda14696 Lucas Stach 2021-07-17  253  	ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
446185fda14696 Lucas Stach 2021-07-17  254  	if (ret) {
446185fda14696 Lucas Stach 2021-07-17  255  		dev_err_probe(dev, ret, "failed to add power domain provider\n");
446185fda14696 Lucas Stach 2021-07-17  256  		goto cleanup_pds;
446185fda14696 Lucas Stach 2021-07-17  257  	}
446185fda14696 Lucas Stach 2021-07-17  258  
446185fda14696 Lucas Stach 2021-07-17  259  	bc->power_nb.notifier_call = bc_data->power_notifier_fn;
446185fda14696 Lucas Stach 2021-07-17  260  	ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
446185fda14696 Lucas Stach 2021-07-17  261  	if (ret) {
446185fda14696 Lucas Stach 2021-07-17  262  		dev_err_probe(dev, ret, "failed to add power notifier\n");
446185fda14696 Lucas Stach 2021-07-17  263  		goto cleanup_provider;
446185fda14696 Lucas Stach 2021-07-17  264  	}
446185fda14696 Lucas Stach 2021-07-17  265  
446185fda14696 Lucas Stach 2021-07-17  266  	dev_set_drvdata(dev, bc);
446185fda14696 Lucas Stach 2021-07-17  267  
446185fda14696 Lucas Stach 2021-07-17  268  	return 0;
446185fda14696 Lucas Stach 2021-07-17  269  
446185fda14696 Lucas Stach 2021-07-17  270  cleanup_provider:
446185fda14696 Lucas Stach 2021-07-17  271  	of_genpd_del_provider(dev->of_node);
446185fda14696 Lucas Stach 2021-07-17  272  cleanup_pds:
446185fda14696 Lucas Stach 2021-07-17  273  	for (i--; i >= 0; i--) {
446185fda14696 Lucas Stach 2021-07-17  274  		pm_genpd_remove(&bc->domains[i].genpd);
446185fda14696 Lucas Stach 2021-07-17  275  		dev_pm_domain_detach(bc->domains[i].power_dev, true);
446185fda14696 Lucas Stach 2021-07-17  276  	}
446185fda14696 Lucas Stach 2021-07-17  277  
446185fda14696 Lucas Stach 2021-07-17  278  	dev_pm_domain_detach(bc->bus_power_dev, true);
446185fda14696 Lucas Stach 2021-07-17  279  
446185fda14696 Lucas Stach 2021-07-17  280  	return ret;
446185fda14696 Lucas Stach 2021-07-17  281  }

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH 09/17] soc: imx: add i.MX8M blk-ctrl driver
  2021-07-19  6:12     ` Dan Carpenter
@ 2021-07-19  9:11       ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-19  9:11 UTC (permalink / raw)
  To: Dan Carpenter, kbuild, Shawn Guo, Rob Herring
  Cc: lkp, kbuild-all, NXP Linux Team, Adam Ford, Frieder Schrempf,
	Peng Fan, Marek Vasut, devicetree, linux-arm-kernel, kernel

Hi Dan,

Am Montag, dem 19.07.2021 um 09:12 +0300 schrieb Dan Carpenter:
> Hi Lucas,
> 
> url:    https://github.com/0day-ci/linux/commits/Lucas-Stach/i-MX8MM-GPC-improvements-and-BLK_CTRL-driver/20210718-102944
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
> config: i386-randconfig-m021-20210718 (attached as .config)
> compiler: gcc-10 (Ubuntu 10.3.0-1ubuntu1~20.04) 10.3.0
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
> 
> smatch warnings:
> drivers/soc/imx/imx8m-blk-ctrl.c:222 imx8m_blk_ctrl_probe() warn: missing error code 'ret'

Thanks for the report! Fixed up locally.

Regards,
Lucas


^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH 09/17] soc: imx: add i.MX8M blk-ctrl driver
@ 2021-07-19  9:11       ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-19  9:11 UTC (permalink / raw)
  To: Dan Carpenter, kbuild, Shawn Guo, Rob Herring
  Cc: lkp, kbuild-all, NXP Linux Team, Adam Ford, Frieder Schrempf,
	Peng Fan, Marek Vasut, devicetree, linux-arm-kernel, kernel

Hi Dan,

Am Montag, dem 19.07.2021 um 09:12 +0300 schrieb Dan Carpenter:
> Hi Lucas,
> 
> url:    https://github.com/0day-ci/linux/commits/Lucas-Stach/i-MX8MM-GPC-improvements-and-BLK_CTRL-driver/20210718-102944
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
> config: i386-randconfig-m021-20210718 (attached as .config)
> compiler: gcc-10 (Ubuntu 10.3.0-1ubuntu1~20.04) 10.3.0
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
> 
> smatch warnings:
> drivers/soc/imx/imx8m-blk-ctrl.c:222 imx8m_blk_ctrl_probe() warn: missing error code 'ret'

Thanks for the report! Fixed up locally.

Regards,
Lucas


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-19 12:53   ` Peng Fan
  -1 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-07-19 12:53 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

Hi Lucas,

> Subject: [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver

Thanks for your work on this. I'll give a look and test tomorrow.

> 
> Hi all,
> 
> over the last few days I've taken on the job to give the blk-ctrl driver initially
> worked on by Peng Fan another spin. What I've come up with now looks quite
> a bit different, as the power sequencing shared between the blk-ctrls and the
> GPC is not really feasible to model with a strict hierarchy of power domains.
> In my design the blk-ctrl driver is the instance driving the sequence for those
> power domains where a blk-ctrl is part of the picture.
> 
> For those that aren't familiar with the power domain architecture on the
> i.MX8M*, here's a short overview, to hopefully make it easier to review this
> series. The i.MX8M* reuses the GPCv2 (General Power Controller)IP block,
> already known from the i.MX7. On the i.MX7 all power domains were
> independent and all the reset and bus isolation sequencing was handled in
> hardware by the GPC. Software only needed to request power up/down for
> the domain and things mostly happened behind the scenes. On i.MX8M*
> things got more complex, as there are now nested power domains and
> coupling of the data busses is handled by AMBA domain bridges (ADB), which
> aren't sequenced by the GPC hardware, but have handshake requests/acks
> wired up to a register in the GPC that needs to be handled by software. Due
> to hardware issues some of the reset sequencing also needs to be handled by
> software, as the GPC isn't always able to properly trigger the SRC reset for the
> peripherals inside the power domains.
> 
> Generally with all those nested domains there exists a outer *MIX (e.g.
> VPUMIX, DISPMIX) domain that contains the ADB and the BLK_CTRL.
> Handshake with the ADB can only happen after the *MIX domain is powered
> up and some domain specific initialization in the BLK_CTRL is done. The ADB
> is connected to a bus clock from CCM that needs to be enabled for the ADB to
> work. Also there might be additional resets and clock gates for the ADB in the
> BLK_CTRL MMIO region, which is also only accessible after the *MIX domain
> is powered up.
> Some peripherals are directly located in the *MIX domain, but others are
> placed in inner domains located in the *MIX domain. In order to power up
> those nested domains the *MIX domain must already be powered up and the
> ADB handshake must be finished. Reset is handled via the BLK_CTRL, instead
> of the SRC, which contains resets and clock gates for the peripherals.
> The general flow for those inner domains is:
> 1. Assert reset and ungate clocks in BLK_CTRL to allow reset to propagate 2.
> Request power up at the GPC 3. Deassert reset
> 
> Failing to meet the ADB handshake and/or reset sequencing requirements will
> generally lead to system hangs (not necessarily at the point where the
> sequence is violated). The blk-ctrl driver as implemented hides this behind
> virtual power domains. Peripherals don't need to care whether they are
> located directly inside the *MIX domain or in a nested domain, they all just
> use the power domains exposed by the BLK_CTRL driver, which handles the
> sequencing requiments internally.
> 
> Currently this series implements both the VPU and DISP blk-ctrls for the
> i.MX8MM SoC, but I'm quite confident that the design is sound and can be
> trivially extended for the other i.MX8M* SoCs. On my personal TODO list is
> the conversion of the i.MX8MQ VPU blk-ctrl to the new model, which should
> finally allow us to drive the G1 and G2 VPUs independently. After that I'm
> going to look at the i.MX8MP, 

Would you take 8MP before 8MQ? 8MP is more popular.
If you not mind, I could post my local 8MP GPC part based on your patchset.
Anyway my local 8MP blk-ctl will be dropped.

as this is a current focus of my work and has
> even more blk-ctrl instances. But before moving on to those, I would like to
> gather some feedback and testing on this series.
> 
> I will also provide a branch with those patches and the WIP VPU and display
> patches I used to test this. But that will have to wait for next week, as it's
> getting pretty late here.

Do you have a public branch now?

Thanks,
Peng.

> 
> Regards,
> Lucas
> 
> Frieder Schrempf (1):
>   arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core
> 
> Lucas Stach (14):
>   Revert "soc: imx: gpcv2: move reset assert after requesting domain
>     power up"
>   soc: imx: gpcv2: add lockdep annotation
>   soc: imx: gpcv2: add domain option to keep domain clocks enabled
>   soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
>   dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
>   dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains
>   soc: imx: add i.MX8M blk-ctrl driver
>   dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
>   dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains
>   soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
>   arm64: dts: imx8mm: add GPC node
>   arm64: dts: imx8mm: put USB controllers into power-domains
>   arm64: dts: imx8mm: add VPU blk-ctrl
>   arm64: dts: imx8mm: add DISP blk-ctrl
> 
> Marek Vasut (2):
>   soc: imx: gpcv2: Turn domain->pgc into bitfield
>   soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM
> GPU
>     domain
> 
>  .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     |  97 ++++
>  .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      |  79 +++
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 180 +++++++
>  drivers/soc/imx/Makefile                      |   1 +
>  drivers/soc/imx/gpcv2.c                       |  99 ++--
>  drivers/soc/imx/imx8m-blk-ctrl.c              | 464
> ++++++++++++++++++
>  include/dt-bindings/power/imx8mm-power.h      |   9 +
>  7 files changed, 888 insertions(+), 41 deletions(-)  create mode 100644
> Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
>  create mode 100644
> Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
>  create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c
> 
> --
> 2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-07-19 12:53   ` Peng Fan
  0 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-07-19 12:53 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

Hi Lucas,

> Subject: [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver

Thanks for your work on this. I'll give a look and test tomorrow.

> 
> Hi all,
> 
> over the last few days I've taken on the job to give the blk-ctrl driver initially
> worked on by Peng Fan another spin. What I've come up with now looks quite
> a bit different, as the power sequencing shared between the blk-ctrls and the
> GPC is not really feasible to model with a strict hierarchy of power domains.
> In my design the blk-ctrl driver is the instance driving the sequence for those
> power domains where a blk-ctrl is part of the picture.
> 
> For those that aren't familiar with the power domain architecture on the
> i.MX8M*, here's a short overview, to hopefully make it easier to review this
> series. The i.MX8M* reuses the GPCv2 (General Power Controller)IP block,
> already known from the i.MX7. On the i.MX7 all power domains were
> independent and all the reset and bus isolation sequencing was handled in
> hardware by the GPC. Software only needed to request power up/down for
> the domain and things mostly happened behind the scenes. On i.MX8M*
> things got more complex, as there are now nested power domains and
> coupling of the data busses is handled by AMBA domain bridges (ADB), which
> aren't sequenced by the GPC hardware, but have handshake requests/acks
> wired up to a register in the GPC that needs to be handled by software. Due
> to hardware issues some of the reset sequencing also needs to be handled by
> software, as the GPC isn't always able to properly trigger the SRC reset for the
> peripherals inside the power domains.
> 
> Generally with all those nested domains there exists a outer *MIX (e.g.
> VPUMIX, DISPMIX) domain that contains the ADB and the BLK_CTRL.
> Handshake with the ADB can only happen after the *MIX domain is powered
> up and some domain specific initialization in the BLK_CTRL is done. The ADB
> is connected to a bus clock from CCM that needs to be enabled for the ADB to
> work. Also there might be additional resets and clock gates for the ADB in the
> BLK_CTRL MMIO region, which is also only accessible after the *MIX domain
> is powered up.
> Some peripherals are directly located in the *MIX domain, but others are
> placed in inner domains located in the *MIX domain. In order to power up
> those nested domains the *MIX domain must already be powered up and the
> ADB handshake must be finished. Reset is handled via the BLK_CTRL, instead
> of the SRC, which contains resets and clock gates for the peripherals.
> The general flow for those inner domains is:
> 1. Assert reset and ungate clocks in BLK_CTRL to allow reset to propagate 2.
> Request power up at the GPC 3. Deassert reset
> 
> Failing to meet the ADB handshake and/or reset sequencing requirements will
> generally lead to system hangs (not necessarily at the point where the
> sequence is violated). The blk-ctrl driver as implemented hides this behind
> virtual power domains. Peripherals don't need to care whether they are
> located directly inside the *MIX domain or in a nested domain, they all just
> use the power domains exposed by the BLK_CTRL driver, which handles the
> sequencing requiments internally.
> 
> Currently this series implements both the VPU and DISP blk-ctrls for the
> i.MX8MM SoC, but I'm quite confident that the design is sound and can be
> trivially extended for the other i.MX8M* SoCs. On my personal TODO list is
> the conversion of the i.MX8MQ VPU blk-ctrl to the new model, which should
> finally allow us to drive the G1 and G2 VPUs independently. After that I'm
> going to look at the i.MX8MP, 

Would you take 8MP before 8MQ? 8MP is more popular.
If you not mind, I could post my local 8MP GPC part based on your patchset.
Anyway my local 8MP blk-ctl will be dropped.

as this is a current focus of my work and has
> even more blk-ctrl instances. But before moving on to those, I would like to
> gather some feedback and testing on this series.
> 
> I will also provide a branch with those patches and the WIP VPU and display
> patches I used to test this. But that will have to wait for next week, as it's
> getting pretty late here.

Do you have a public branch now?

Thanks,
Peng.

> 
> Regards,
> Lucas
> 
> Frieder Schrempf (1):
>   arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core
> 
> Lucas Stach (14):
>   Revert "soc: imx: gpcv2: move reset assert after requesting domain
>     power up"
>   soc: imx: gpcv2: add lockdep annotation
>   soc: imx: gpcv2: add domain option to keep domain clocks enabled
>   soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
>   dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
>   dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains
>   soc: imx: add i.MX8M blk-ctrl driver
>   dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
>   dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains
>   soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
>   arm64: dts: imx8mm: add GPC node
>   arm64: dts: imx8mm: put USB controllers into power-domains
>   arm64: dts: imx8mm: add VPU blk-ctrl
>   arm64: dts: imx8mm: add DISP blk-ctrl
> 
> Marek Vasut (2):
>   soc: imx: gpcv2: Turn domain->pgc into bitfield
>   soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM
> GPU
>     domain
> 
>  .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     |  97 ++++
>  .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      |  79 +++
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 180 +++++++
>  drivers/soc/imx/Makefile                      |   1 +
>  drivers/soc/imx/gpcv2.c                       |  99 ++--
>  drivers/soc/imx/imx8m-blk-ctrl.c              | 464
> ++++++++++++++++++
>  include/dt-bindings/power/imx8mm-power.h      |   9 +
>  7 files changed, 888 insertions(+), 41 deletions(-)  create mode 100644
> Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
>  create mode 100644
> Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
>  create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c
> 
> --
> 2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH 10/17] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
  2021-07-16 23:29   ` Lucas Stach
@ 2021-07-19 13:47     ` Rob Herring
  -1 siblings, 0 replies; 136+ messages in thread
From: Rob Herring @ 2021-07-19 13:47 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Adam Ford, Peng Fan, kernel, Marek Vasut, Rob Herring, Shawn Guo,
	linux-arm-kernel, Frieder Schrempf, patchwork-lst, devicetree,
	NXP Linux Team

On Sat, 17 Jul 2021 01:29:09 +0200, Lucas Stach wrote:
> This adds the DT binding for the i.MX8MM VPU blk-ctrl.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     | 97 +++++++++++++++++++
>  1 file changed, 97 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:compatible: [{'const': 'fsl,imx8mm-disp-blk-ctrl'}, {'const': 'syscon'}] is not of type 'object', 'boolean'
	from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:clock-names:items: 'anyOf' conditional failed, one must be fixed:
	['csi-bridge-axi', 'csi-bridge-apb', 'csi-bridge-core', 'lcdif-axi', 'lcdif-apb', 'lcdif-pix', 'dsi-pclk', 'dsi-ref', 'csi-aclk', 'csi-pclk'] is not of type 'object', 'boolean'
	'csi-bridge-axi' is not of type 'object', 'boolean'
	'csi-bridge-apb' is not of type 'object', 'boolean'
	'csi-bridge-core' is not of type 'object', 'boolean'
	'lcdif-axi' is not of type 'object', 'boolean'
	'lcdif-apb' is not of type 'object', 'boolean'
	'lcdif-pix' is not of type 'object', 'boolean'
	'dsi-pclk' is not of type 'object', 'boolean'
	'dsi-ref' is not of type 'object', 'boolean'
	'csi-aclk' is not of type 'object', 'boolean'
	'csi-pclk' is not of type 'object', 'boolean'
	from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:power-domain-names:items: 'anyOf' conditional failed, one must be fixed:
	['bus', 'csi-bridge', 'lcdif', 'mipi-dsi', 'mipi-csi'] is not of type 'object', 'boolean'
	'bus' is not of type 'object', 'boolean'
	'csi-bridge' is not of type 'object', 'boolean'
	'lcdif' is not of type 'object', 'boolean'
	'mipi-dsi' is not of type 'object', 'boolean'
	'mipi-csi' is not of type 'object', 'boolean'
	from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: $id: 'http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl#' does not match 'http://devicetree.org/schemas/.*\\.yaml#'
	from schema $id: http://devicetree.org/meta-schemas/base.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:power-domain-names:minItems: False schema does not allow 5
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:power-domain-names:maxItems: False schema does not allow 5
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:clock-names:minItems: False schema does not allow 10
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:clock-names:maxItems: False schema does not allow 10
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
./Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: $id: relative path/filename doesn't match actual path or filename
	expected: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: ignoring, error in schema: properties: clock-names: items
warning: no schema found in file: ./Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.example.dts:20:51: error: missing terminating > character
   20 |         #include <dt-bindings/power/imx8mm-power.h
      |                                                   ^
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1418: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1506316

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH 07/17] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
  2021-07-16 23:29   ` Lucas Stach
@ 2021-07-19 13:47     ` Rob Herring
  -1 siblings, 0 replies; 136+ messages in thread
From: Rob Herring @ 2021-07-19 13:47 UTC (permalink / raw)
  To: Lucas Stach
  Cc: NXP Linux Team, Rob Herring, kernel, Peng Fan, Frieder Schrempf,
	Adam Ford, Shawn Guo, patchwork-lst, Marek Vasut,
	linux-arm-kernel, devicetree

On Sat, 17 Jul 2021 01:29:06 +0200, Lucas Stach wrote:
> This adds the DT binding for the i.MX8MM VPU blk-ctrl.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      | 79 +++++++++++++++++++
>  1 file changed, 79 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:compatible: [{'const': 'fsl,imx8mm-vpu-blk-ctrl'}, {'const': 'syscon'}] is not of type 'object', 'boolean'
	from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:clock-names:items: 'anyOf' conditional failed, one must be fixed:
	['g1', 'g2', 'h1'] is not of type 'object', 'boolean'
	'g1' is not of type 'object', 'boolean'
	'g2' is not of type 'object', 'boolean'
	'h1' is not of type 'object', 'boolean'
	from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:power-domain-names:items: 'anyOf' conditional failed, one must be fixed:
	['bus', 'g1', 'g1', 'h1'] is not of type 'object', 'boolean'
	'bus' is not of type 'object', 'boolean'
	'g1' is not of type 'object', 'boolean'
	'h1' is not of type 'object', 'boolean'
	from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: $id: 'http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl#' does not match 'http://devicetree.org/schemas/.*\\.yaml#'
	from schema $id: http://devicetree.org/meta-schemas/base.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:power-domain-names:minItems: False schema does not allow 4
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:power-domain-names:maxItems: False schema does not allow 4
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:clock-names:minItems: False schema does not allow 3
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:clock-names:maxItems: False schema does not allow 3
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
./Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: $id: relative path/filename doesn't match actual path or filename
	expected: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: ignoring, error in schema: properties: compatible
warning: no schema found in file: ./Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.example.dts:20:51: error: missing terminating > character
   20 |         #include <dt-bindings/power/imx8mm-power.h
      |                                                   ^
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1418: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1506314

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH 07/17] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
@ 2021-07-19 13:47     ` Rob Herring
  0 siblings, 0 replies; 136+ messages in thread
From: Rob Herring @ 2021-07-19 13:47 UTC (permalink / raw)
  To: Lucas Stach
  Cc: NXP Linux Team, Rob Herring, kernel, Peng Fan, Frieder Schrempf,
	Adam Ford, Shawn Guo, patchwork-lst, Marek Vasut,
	linux-arm-kernel, devicetree

On Sat, 17 Jul 2021 01:29:06 +0200, Lucas Stach wrote:
> This adds the DT binding for the i.MX8MM VPU blk-ctrl.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      | 79 +++++++++++++++++++
>  1 file changed, 79 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:compatible: [{'const': 'fsl,imx8mm-vpu-blk-ctrl'}, {'const': 'syscon'}] is not of type 'object', 'boolean'
	from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:clock-names:items: 'anyOf' conditional failed, one must be fixed:
	['g1', 'g2', 'h1'] is not of type 'object', 'boolean'
	'g1' is not of type 'object', 'boolean'
	'g2' is not of type 'object', 'boolean'
	'h1' is not of type 'object', 'boolean'
	from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:power-domain-names:items: 'anyOf' conditional failed, one must be fixed:
	['bus', 'g1', 'g1', 'h1'] is not of type 'object', 'boolean'
	'bus' is not of type 'object', 'boolean'
	'g1' is not of type 'object', 'boolean'
	'h1' is not of type 'object', 'boolean'
	from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: $id: 'http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl#' does not match 'http://devicetree.org/schemas/.*\\.yaml#'
	from schema $id: http://devicetree.org/meta-schemas/base.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:power-domain-names:minItems: False schema does not allow 4
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:power-domain-names:maxItems: False schema does not allow 4
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:clock-names:minItems: False schema does not allow 3
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: properties:clock-names:maxItems: False schema does not allow 3
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
./Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: $id: relative path/filename doesn't match actual path or filename
	expected: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml: ignoring, error in schema: properties: compatible
warning: no schema found in file: ./Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.example.dts:20:51: error: missing terminating > character
   20 |         #include <dt-bindings/power/imx8mm-power.h
      |                                                   ^
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1418: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1506314

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH 10/17] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
@ 2021-07-19 13:47     ` Rob Herring
  0 siblings, 0 replies; 136+ messages in thread
From: Rob Herring @ 2021-07-19 13:47 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Adam Ford, Peng Fan, kernel, Marek Vasut, Rob Herring, Shawn Guo,
	linux-arm-kernel, Frieder Schrempf, patchwork-lst, devicetree,
	NXP Linux Team

On Sat, 17 Jul 2021 01:29:09 +0200, Lucas Stach wrote:
> This adds the DT binding for the i.MX8MM VPU blk-ctrl.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     | 97 +++++++++++++++++++
>  1 file changed, 97 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:compatible: [{'const': 'fsl,imx8mm-disp-blk-ctrl'}, {'const': 'syscon'}] is not of type 'object', 'boolean'
	from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:clock-names:items: 'anyOf' conditional failed, one must be fixed:
	['csi-bridge-axi', 'csi-bridge-apb', 'csi-bridge-core', 'lcdif-axi', 'lcdif-apb', 'lcdif-pix', 'dsi-pclk', 'dsi-ref', 'csi-aclk', 'csi-pclk'] is not of type 'object', 'boolean'
	'csi-bridge-axi' is not of type 'object', 'boolean'
	'csi-bridge-apb' is not of type 'object', 'boolean'
	'csi-bridge-core' is not of type 'object', 'boolean'
	'lcdif-axi' is not of type 'object', 'boolean'
	'lcdif-apb' is not of type 'object', 'boolean'
	'lcdif-pix' is not of type 'object', 'boolean'
	'dsi-pclk' is not of type 'object', 'boolean'
	'dsi-ref' is not of type 'object', 'boolean'
	'csi-aclk' is not of type 'object', 'boolean'
	'csi-pclk' is not of type 'object', 'boolean'
	from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:power-domain-names:items: 'anyOf' conditional failed, one must be fixed:
	['bus', 'csi-bridge', 'lcdif', 'mipi-dsi', 'mipi-csi'] is not of type 'object', 'boolean'
	'bus' is not of type 'object', 'boolean'
	'csi-bridge' is not of type 'object', 'boolean'
	'lcdif' is not of type 'object', 'boolean'
	'mipi-dsi' is not of type 'object', 'boolean'
	'mipi-csi' is not of type 'object', 'boolean'
	from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: $id: 'http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl#' does not match 'http://devicetree.org/schemas/.*\\.yaml#'
	from schema $id: http://devicetree.org/meta-schemas/base.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:power-domain-names:minItems: False schema does not allow 5
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:power-domain-names:maxItems: False schema does not allow 5
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:clock-names:minItems: False schema does not allow 10
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: properties:clock-names:maxItems: False schema does not allow 10
	hint: "minItems/maxItems" equal to the "items" list length are not necessary
	from schema $id: http://devicetree.org/meta-schemas/items.yaml#
./Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: $id: relative path/filename doesn't match actual path or filename
	expected: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml: ignoring, error in schema: properties: clock-names: items
warning: no schema found in file: ./Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.example.dts:20:51: error: missing terminating > character
   20 |         #include <dt-bindings/power/imx8mm-power.h
      |                                                   ^
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1418: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1506316

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-07-19 12:53   ` Peng Fan
@ 2021-07-19 16:56     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-19 16:56 UTC (permalink / raw)
  To: Peng Fan, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

Hi Peng,

Am Montag, dem 19.07.2021 um 12:53 +0000 schrieb Peng Fan:
> Hi Lucas,
> 
> > Subject: [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver
> 
> Thanks for your work on this. I'll give a look and test tomorrow.
> 
> > 
> > Hi all,
> > 
> > over the last few days I've taken on the job to give the blk-ctrl driver initially
> > worked on by Peng Fan another spin. What I've come up with now looks quite
> > a bit different, as the power sequencing shared between the blk-ctrls and the
> > GPC is not really feasible to model with a strict hierarchy of power domains.
> > In my design the blk-ctrl driver is the instance driving the sequence for those
> > power domains where a blk-ctrl is part of the picture.
> > 
> > For those that aren't familiar with the power domain architecture on the
> > i.MX8M*, here's a short overview, to hopefully make it easier to review this
> > series. The i.MX8M* reuses the GPCv2 (General Power Controller)IP block,
> > already known from the i.MX7. On the i.MX7 all power domains were
> > independent and all the reset and bus isolation sequencing was handled in
> > hardware by the GPC. Software only needed to request power up/down for
> > the domain and things mostly happened behind the scenes. On i.MX8M*
> > things got more complex, as there are now nested power domains and
> > coupling of the data busses is handled by AMBA domain bridges (ADB), which
> > aren't sequenced by the GPC hardware, but have handshake requests/acks
> > wired up to a register in the GPC that needs to be handled by software. Due
> > to hardware issues some of the reset sequencing also needs to be handled by
> > software, as the GPC isn't always able to properly trigger the SRC reset for the
> > peripherals inside the power domains.
> > 
> > Generally with all those nested domains there exists a outer *MIX (e.g.
> > VPUMIX, DISPMIX) domain that contains the ADB and the BLK_CTRL.
> > Handshake with the ADB can only happen after the *MIX domain is powered
> > up and some domain specific initialization in the BLK_CTRL is done. The ADB
> > is connected to a bus clock from CCM that needs to be enabled for the ADB to
> > work. Also there might be additional resets and clock gates for the ADB in the
> > BLK_CTRL MMIO region, which is also only accessible after the *MIX domain
> > is powered up.
> > Some peripherals are directly located in the *MIX domain, but others are
> > placed in inner domains located in the *MIX domain. In order to power up
> > those nested domains the *MIX domain must already be powered up and the
> > ADB handshake must be finished. Reset is handled via the BLK_CTRL, instead
> > of the SRC, which contains resets and clock gates for the peripherals.
> > The general flow for those inner domains is:
> > 1. Assert reset and ungate clocks in BLK_CTRL to allow reset to propagate 2.
> > Request power up at the GPC 3. Deassert reset
> > 
> > Failing to meet the ADB handshake and/or reset sequencing requirements will
> > generally lead to system hangs (not necessarily at the point where the
> > sequence is violated). The blk-ctrl driver as implemented hides this behind
> > virtual power domains. Peripherals don't need to care whether they are
> > located directly inside the *MIX domain or in a nested domain, they all just
> > use the power domains exposed by the BLK_CTRL driver, which handles the
> > sequencing requiments internally.
> > 
> > Currently this series implements both the VPU and DISP blk-ctrls for the
> > i.MX8MM SoC, but I'm quite confident that the design is sound and can be
> > trivially extended for the other i.MX8M* SoCs. On my personal TODO list is
> > the conversion of the i.MX8MQ VPU blk-ctrl to the new model, which should
> > finally allow us to drive the G1 and G2 VPUs independently. After that I'm
> > going to look at the i.MX8MP, 
> 
> Would you take 8MP before 8MQ? 8MP is more popular.
> If you not mind, I could post my local 8MP GPC part based on your patchset.
> Anyway my local 8MP blk-ctl will be dropped.

The 8MQ VPU conversion should be pretty trivial, now that I've worked
out the overall structure of the blk-ctrl driver. I'm also aware of
multiple people in the community waiting for this part to land, as it's
blocking Hantro G2 support on i.MX8MQ upstream, so I'm going to stick
to this order. While there is a lot interest in 8MP, there aren't that
many people that even have the hardware yet, while the 8MQ is in pretty
widespread use.

I also have some 8MP GPC work bitrotting in a branch, which I planned
to revive. If you already have something ready, I'm happy to skip that
and review your patches instead.

> 
> as this is a current focus of my work and has
> > even more blk-ctrl instances. But before moving on to those, I would like to
> > gather some feedback and testing on this series.
> > 
> > I will also provide a branch with those patches and the WIP VPU and display
> > patches I used to test this. But that will have to wait for next week, as it's
> > getting pretty late here.
> 
> Do you have a public branch now?

This series (with fixes for the reported issues already squashed in)
can be found here:
https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains

Additional patches to enable MIPI DSI display and one VPU can be found
here:
https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing

Please note that the display patches do not reflect the current status
of the upstream discussions, it's just my known-good stack at the
moment. I'm providing those patches just for contextual reference and
to allow people to see my test setup. I've worked on a custom i.MX8MM
board, so the bits to hook this up for the EVK board are missing. I am
not seeking feedback on any of the display/vpu patches at the moment.

Regards,
Lucas



^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-07-19 16:56     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-19 16:56 UTC (permalink / raw)
  To: Peng Fan, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

Hi Peng,

Am Montag, dem 19.07.2021 um 12:53 +0000 schrieb Peng Fan:
> Hi Lucas,
> 
> > Subject: [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver
> 
> Thanks for your work on this. I'll give a look and test tomorrow.
> 
> > 
> > Hi all,
> > 
> > over the last few days I've taken on the job to give the blk-ctrl driver initially
> > worked on by Peng Fan another spin. What I've come up with now looks quite
> > a bit different, as the power sequencing shared between the blk-ctrls and the
> > GPC is not really feasible to model with a strict hierarchy of power domains.
> > In my design the blk-ctrl driver is the instance driving the sequence for those
> > power domains where a blk-ctrl is part of the picture.
> > 
> > For those that aren't familiar with the power domain architecture on the
> > i.MX8M*, here's a short overview, to hopefully make it easier to review this
> > series. The i.MX8M* reuses the GPCv2 (General Power Controller)IP block,
> > already known from the i.MX7. On the i.MX7 all power domains were
> > independent and all the reset and bus isolation sequencing was handled in
> > hardware by the GPC. Software only needed to request power up/down for
> > the domain and things mostly happened behind the scenes. On i.MX8M*
> > things got more complex, as there are now nested power domains and
> > coupling of the data busses is handled by AMBA domain bridges (ADB), which
> > aren't sequenced by the GPC hardware, but have handshake requests/acks
> > wired up to a register in the GPC that needs to be handled by software. Due
> > to hardware issues some of the reset sequencing also needs to be handled by
> > software, as the GPC isn't always able to properly trigger the SRC reset for the
> > peripherals inside the power domains.
> > 
> > Generally with all those nested domains there exists a outer *MIX (e.g.
> > VPUMIX, DISPMIX) domain that contains the ADB and the BLK_CTRL.
> > Handshake with the ADB can only happen after the *MIX domain is powered
> > up and some domain specific initialization in the BLK_CTRL is done. The ADB
> > is connected to a bus clock from CCM that needs to be enabled for the ADB to
> > work. Also there might be additional resets and clock gates for the ADB in the
> > BLK_CTRL MMIO region, which is also only accessible after the *MIX domain
> > is powered up.
> > Some peripherals are directly located in the *MIX domain, but others are
> > placed in inner domains located in the *MIX domain. In order to power up
> > those nested domains the *MIX domain must already be powered up and the
> > ADB handshake must be finished. Reset is handled via the BLK_CTRL, instead
> > of the SRC, which contains resets and clock gates for the peripherals.
> > The general flow for those inner domains is:
> > 1. Assert reset and ungate clocks in BLK_CTRL to allow reset to propagate 2.
> > Request power up at the GPC 3. Deassert reset
> > 
> > Failing to meet the ADB handshake and/or reset sequencing requirements will
> > generally lead to system hangs (not necessarily at the point where the
> > sequence is violated). The blk-ctrl driver as implemented hides this behind
> > virtual power domains. Peripherals don't need to care whether they are
> > located directly inside the *MIX domain or in a nested domain, they all just
> > use the power domains exposed by the BLK_CTRL driver, which handles the
> > sequencing requiments internally.
> > 
> > Currently this series implements both the VPU and DISP blk-ctrls for the
> > i.MX8MM SoC, but I'm quite confident that the design is sound and can be
> > trivially extended for the other i.MX8M* SoCs. On my personal TODO list is
> > the conversion of the i.MX8MQ VPU blk-ctrl to the new model, which should
> > finally allow us to drive the G1 and G2 VPUs independently. After that I'm
> > going to look at the i.MX8MP, 
> 
> Would you take 8MP before 8MQ? 8MP is more popular.
> If you not mind, I could post my local 8MP GPC part based on your patchset.
> Anyway my local 8MP blk-ctl will be dropped.

The 8MQ VPU conversion should be pretty trivial, now that I've worked
out the overall structure of the blk-ctrl driver. I'm also aware of
multiple people in the community waiting for this part to land, as it's
blocking Hantro G2 support on i.MX8MQ upstream, so I'm going to stick
to this order. While there is a lot interest in 8MP, there aren't that
many people that even have the hardware yet, while the 8MQ is in pretty
widespread use.

I also have some 8MP GPC work bitrotting in a branch, which I planned
to revive. If you already have something ready, I'm happy to skip that
and review your patches instead.

> 
> as this is a current focus of my work and has
> > even more blk-ctrl instances. But before moving on to those, I would like to
> > gather some feedback and testing on this series.
> > 
> > I will also provide a branch with those patches and the WIP VPU and display
> > patches I used to test this. But that will have to wait for next week, as it's
> > getting pretty late here.
> 
> Do you have a public branch now?

This series (with fixes for the reported issues already squashed in)
can be found here:
https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains

Additional patches to enable MIPI DSI display and one VPU can be found
here:
https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing

Please note that the display patches do not reflect the current status
of the upstream discussions, it's just my known-good stack at the
moment. I'm providing those patches just for contextual reference and
to allow people to see my test setup. I've worked on a custom i.MX8MM
board, so the bits to hook this up for the EVK board are missing. I am
not seeking feedback on any of the display/vpu patches at the moment.

Regards,
Lucas



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-07-19 16:56     ` Lucas Stach
@ 2021-07-21 11:21       ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 11:21 UTC (permalink / raw)
  To: Peng Fan, Shawn Guo, Rob Herring
  Cc: Marek Vasut, devicetree, Frieder Schrempf, patchwork-lst,
	dl-linux-imx, kernel, Adam Ford, linux-arm-kernel

Am Montag, dem 19.07.2021 um 18:56 +0200 schrieb Lucas Stach:
> Hi Peng,
> > > 
[...]
> > > I will also provide a branch with those patches and the WIP VPU and display
> > > patches I used to test this. But that will have to wait for next week, as it's
> > > getting pretty late here.
> > 
> > Do you have a public branch now?
> 
> This series (with fixes for the reported issues already squashed in)
> can be found here:
> https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains
> 
> Additional patches to enable MIPI DSI display and one VPU can be found
> here:
> https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing
> 
> Please note that the display patches do not reflect the current status
> of the upstream discussions, it's just my known-good stack at the
> moment. I'm providing those patches just for contextual reference and
> to allow people to see my test setup. I've worked on a custom i.MX8MM
> board, so the bits to hook this up for the EVK board are missing. I am
> not seeking feedback on any of the display/vpu patches at the moment.
> 
And just a heads-up in case anyone is testing this series right now:
I've found some issues with suspend-resume and I'm working on them
right now. I'll send a v2 shortly and will also update those public
branches.

Regards,
Lucas


^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-07-21 11:21       ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 11:21 UTC (permalink / raw)
  To: Peng Fan, Shawn Guo, Rob Herring
  Cc: Marek Vasut, devicetree, Frieder Schrempf, patchwork-lst,
	dl-linux-imx, kernel, Adam Ford, linux-arm-kernel

Am Montag, dem 19.07.2021 um 18:56 +0200 schrieb Lucas Stach:
> Hi Peng,
> > > 
[...]
> > > I will also provide a branch with those patches and the WIP VPU and display
> > > patches I used to test this. But that will have to wait for next week, as it's
> > > getting pretty late here.
> > 
> > Do you have a public branch now?
> 
> This series (with fixes for the reported issues already squashed in)
> can be found here:
> https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains
> 
> Additional patches to enable MIPI DSI display and one VPU can be found
> here:
> https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing
> 
> Please note that the display patches do not reflect the current status
> of the upstream discussions, it's just my known-good stack at the
> moment. I'm providing those patches just for contextual reference and
> to allow people to see my test setup. I've worked on a custom i.MX8MM
> board, so the bits to hook this up for the EVK board are missing. I am
> not seeking feedback on any of the display/vpu patches at the moment.
> 
And just a heads-up in case anyone is testing this series right now:
I've found some issues with suspend-resume and I'm working on them
right now. I'll send a v2 shortly and will also update those public
branches.

Regards,
Lucas


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-07-16 23:28 ` Lucas Stach
@ 2021-07-21 20:46   ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Hi all,

second revision of the GPC improvements and BLK_CTRL driver to make use
of all the power-domains on the i.MX8MM. I'm not going to repeat the full
blurb from the v1 cover letter here, but if you are not familiar with
i.MX8MM power domains, it may be worth a read.

This 2nd revision fixes the DT bindings to be valid yaml, some small
failure path issues and most importantly the interaction with system
suspend/resume. With the previous version some of the power domains
would not come up correctly after a suspend/resume cycle.

Updated testing git trees here, disclaimer still applies:
https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains
https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing

Regards,
Lucas

Frieder Schrempf (1):
  arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core

Lucas Stach (15):
  Revert "soc: imx: gpcv2: move reset assert after requesting domain
    power up"
  soc: imx: gpcv2: add lockdep annotation
  soc: imx: gpcv2: add domain option to keep domain clocks enabled
  soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
  soc: imx: gpcv2: support system suspend/resume
  dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
  dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains
  soc: imx: add i.MX8M blk-ctrl driver
  dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
  dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains
  soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
  arm64: dts: imx8mm: add GPC node
  arm64: dts: imx8mm: put USB controllers into power-domains
  arm64: dts: imx8mm: add VPU blk-ctrl
  arm64: dts: imx8mm: add DISP blk-ctrl

Marek Vasut (2):
  soc: imx: gpcv2: Turn domain->pgc into bitfield
  soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU
    domain

 .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     |  94 ++++
 .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      |  76 +++
 arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 180 ++++++
 drivers/soc/imx/Makefile                      |   1 +
 drivers/soc/imx/gpcv2.c                       | 130 +++--
 drivers/soc/imx/imx8m-blk-ctrl.c              | 525 ++++++++++++++++++
 include/dt-bindings/power/imx8mm-power.h      |   9 +
 7 files changed, 974 insertions(+), 41 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
 create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c

-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-07-21 20:46   ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Hi all,

second revision of the GPC improvements and BLK_CTRL driver to make use
of all the power-domains on the i.MX8MM. I'm not going to repeat the full
blurb from the v1 cover letter here, but if you are not familiar with
i.MX8MM power domains, it may be worth a read.

This 2nd revision fixes the DT bindings to be valid yaml, some small
failure path issues and most importantly the interaction with system
suspend/resume. With the previous version some of the power domains
would not come up correctly after a suspend/resume cycle.

Updated testing git trees here, disclaimer still applies:
https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains
https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing

Regards,
Lucas

Frieder Schrempf (1):
  arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core

Lucas Stach (15):
  Revert "soc: imx: gpcv2: move reset assert after requesting domain
    power up"
  soc: imx: gpcv2: add lockdep annotation
  soc: imx: gpcv2: add domain option to keep domain clocks enabled
  soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
  soc: imx: gpcv2: support system suspend/resume
  dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
  dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains
  soc: imx: add i.MX8M blk-ctrl driver
  dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
  dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains
  soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
  arm64: dts: imx8mm: add GPC node
  arm64: dts: imx8mm: put USB controllers into power-domains
  arm64: dts: imx8mm: add VPU blk-ctrl
  arm64: dts: imx8mm: add DISP blk-ctrl

Marek Vasut (2):
  soc: imx: gpcv2: Turn domain->pgc into bitfield
  soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU
    domain

 .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     |  94 ++++
 .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      |  76 +++
 arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 180 ++++++
 drivers/soc/imx/Makefile                      |   1 +
 drivers/soc/imx/gpcv2.c                       | 130 +++--
 drivers/soc/imx/imx8m-blk-ctrl.c              | 525 ++++++++++++++++++
 include/dt-bindings/power/imx8mm-power.h      |   9 +
 7 files changed, 974 insertions(+), 41 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
 create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c

-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 01/18] Revert "soc: imx: gpcv2: move reset assert after requesting domain power up"
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This reverts commit a77ebdd9f553. It turns out that the VPU domain has no
different requirements, even though the downstream ATF implementation seems
to suggest otherwise. Powering on the domain with the reset asserted works
fine. As the changed sequence has caused sporadic issues with the GPU
domains, just revert the change to go back to the working sequence.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 34a9ac1f2b9b..8b7a01773aec 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -244,6 +244,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 		goto out_regulator_disable;
 	}
 
+	reset_control_assert(domain->reset);
+
 	if (domain->bits.pxx) {
 		/* request the domain to power up */
 		regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
@@ -266,8 +268,6 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 				  GPC_PGC_CTRL_PCR);
 	}
 
-	reset_control_assert(domain->reset);
-
 	/* delay for reset to propagate */
 	udelay(5);
 
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 01/18] Revert "soc: imx: gpcv2: move reset assert after requesting domain power up"
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This reverts commit a77ebdd9f553. It turns out that the VPU domain has no
different requirements, even though the downstream ATF implementation seems
to suggest otherwise. Powering on the domain with the reset asserted works
fine. As the changed sequence has caused sporadic issues with the GPU
domains, just revert the change to go back to the working sequence.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 34a9ac1f2b9b..8b7a01773aec 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -244,6 +244,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 		goto out_regulator_disable;
 	}
 
+	reset_control_assert(domain->reset);
+
 	if (domain->bits.pxx) {
 		/* request the domain to power up */
 		regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
@@ -266,8 +268,6 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 				  GPC_PGC_CTRL_PCR);
 	}
 
-	reset_control_assert(domain->reset);
-
 	/* delay for reset to propagate */
 	udelay(5);
 
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 02/18] soc: imx: gpcv2: Turn domain->pgc into bitfield
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

From: Marek Vasut <marex@denx.de>

There is currently the MX8MM GPU domain, which is in fact a composite domain
for both GPU2D and GPU3D. To correctly configure this domain, it is necessary
to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same
time. This is currently not possible.

Turn the domain->pgc from value into bitfield and use for_each_set_bit() to
iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL
register array. This way it is possible to configure all GPC_PGC_nCTRL
registers required in a particular domain.

This is a preparatory patch, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
v2 (Lucas Stach):
- rebase on top of reverted reset sequence change
- also convert i.MX8MN domains
---
 drivers/soc/imx/gpcv2.c | 72 ++++++++++++++++++++++-------------------
 1 file changed, 38 insertions(+), 34 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 8b7a01773aec..c7826ce92f0d 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -192,7 +192,7 @@ struct imx_pgc_domain {
 	struct clk_bulk_data *clks;
 	int num_clks;
 
-	unsigned int pgc;
+	unsigned long pgc;
 
 	const struct {
 		u32 pxx;
@@ -220,7 +220,7 @@ to_imx_pgc_domain(struct generic_pm_domain *genpd)
 static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 {
 	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
-	u32 reg_val;
+	u32 reg_val, pgc;
 	int ret;
 
 	ret = pm_runtime_get_sync(domain->dev);
@@ -264,8 +264,10 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 		}
 
 		/* disable power control */
-		regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
-				  GPC_PGC_CTRL_PCR);
+		for_each_set_bit(pgc, &domain->pgc, 32) {
+			regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
+					  GPC_PGC_CTRL_PCR);
+		}
 	}
 
 	/* delay for reset to propagate */
@@ -311,7 +313,7 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 {
 	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
-	u32 reg_val;
+	u32 reg_val, pgc;
 	int ret;
 
 	/* Enable reset clocks for all devices in the domain */
@@ -338,8 +340,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 
 	if (domain->bits.pxx) {
 		/* enable power control */
-		regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
-				   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+		for_each_set_bit(pgc, &domain->pgc, 32) {
+			regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
+					   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+		}
 
 		/* request the domain to power down */
 		regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
@@ -389,7 +393,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1000000,
-		.pgc	   = IMX7_PGC_MIPI,
+		.pgc	   = BIT(IMX7_PGC_MIPI),
 	},
 
 	[IMX7_POWER_DOMAIN_PCIE_PHY] = {
@@ -401,7 +405,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1000000,
-		.pgc	   = IMX7_PGC_PCIE,
+		.pgc	   = BIT(IMX7_PGC_PCIE),
 	},
 
 	[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
@@ -413,7 +417,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1200000,
-		.pgc	   = IMX7_PGC_USB_HSIC,
+		.pgc	   = BIT(IMX7_PGC_USB_HSIC),
 	},
 };
 
@@ -448,7 +452,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_MIPI_SW_Pxx_REQ,
 			.map = IMX8M_MIPI_A53_DOMAIN,
 		},
-		.pgc	   = IMX8M_PGC_MIPI,
+		.pgc	   = BIT(IMX8M_PGC_MIPI),
 	},
 
 	[IMX8M_POWER_DOMAIN_PCIE1] = {
@@ -459,7 +463,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_PCIE1_SW_Pxx_REQ,
 			.map = IMX8M_PCIE1_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_PCIE1,
+		.pgc   = BIT(IMX8M_PGC_PCIE1),
 	},
 
 	[IMX8M_POWER_DOMAIN_USB_OTG1] = {
@@ -470,7 +474,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_OTG1_SW_Pxx_REQ,
 			.map = IMX8M_OTG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_OTG1,
+		.pgc   = BIT(IMX8M_PGC_OTG1),
 	},
 
 	[IMX8M_POWER_DOMAIN_USB_OTG2] = {
@@ -481,7 +485,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_OTG2_SW_Pxx_REQ,
 			.map = IMX8M_OTG2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_OTG2,
+		.pgc   = BIT(IMX8M_PGC_OTG2),
 	},
 
 	[IMX8M_POWER_DOMAIN_DDR1] = {
@@ -492,7 +496,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_DDR1_SW_Pxx_REQ,
 			.map = IMX8M_DDR2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_DDR1,
+		.pgc   = BIT(IMX8M_PGC_DDR1),
 	},
 
 	[IMX8M_POWER_DOMAIN_GPU] = {
@@ -505,7 +509,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.hskreq = IMX8M_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8M_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8M_PGC_GPU,
+		.pgc   = BIT(IMX8M_PGC_GPU),
 	},
 
 	[IMX8M_POWER_DOMAIN_VPU] = {
@@ -518,7 +522,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.hskreq = IMX8M_VPU_HSK_PWRDNREQN,
 			.hskack = IMX8M_VPU_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8M_PGC_VPU,
+		.pgc   = BIT(IMX8M_PGC_VPU),
 	},
 
 	[IMX8M_POWER_DOMAIN_DISP] = {
@@ -531,7 +535,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.hskreq = IMX8M_DISP_HSK_PWRDNREQN,
 			.hskack = IMX8M_DISP_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8M_PGC_DISP,
+		.pgc   = BIT(IMX8M_PGC_DISP),
 	},
 
 	[IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
@@ -542,7 +546,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
 			.map = IMX8M_MIPI_CSI1_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_MIPI_CSI1,
+		.pgc   = BIT(IMX8M_PGC_MIPI_CSI1),
 	},
 
 	[IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
@@ -553,7 +557,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
 			.map = IMX8M_MIPI_CSI2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_MIPI_CSI2,
+		.pgc   = BIT(IMX8M_PGC_MIPI_CSI2),
 	},
 
 	[IMX8M_POWER_DOMAIN_PCIE2] = {
@@ -564,7 +568,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_PCIE2_SW_Pxx_REQ,
 			.map = IMX8M_PCIE2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_PCIE2,
+		.pgc   = BIT(IMX8M_PGC_PCIE2),
 	},
 };
 
@@ -627,7 +631,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_PCIE_SW_Pxx_REQ,
 			.map = IMX8MM_PCIE_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_PCIE,
+		.pgc   = BIT(IMX8MM_PGC_PCIE),
 	},
 
 	[IMX8MM_POWER_DOMAIN_OTG1] = {
@@ -638,7 +642,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_OTG1_SW_Pxx_REQ,
 			.map = IMX8MM_OTG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_OTG1,
+		.pgc   = BIT(IMX8MM_PGC_OTG1),
 	},
 
 	[IMX8MM_POWER_DOMAIN_OTG2] = {
@@ -649,7 +653,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_OTG2_SW_Pxx_REQ,
 			.map = IMX8MM_OTG2_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_OTG2,
+		.pgc   = BIT(IMX8MM_PGC_OTG2),
 	},
 
 	[IMX8MM_POWER_DOMAIN_GPUMIX] = {
@@ -662,7 +666,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_GPUMIX,
+		.pgc   = BIT(IMX8MM_PGC_GPUMIX),
 	},
 
 	[IMX8MM_POWER_DOMAIN_GPU] = {
@@ -675,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_GPU2D,
+		.pgc   = BIT(IMX8MM_PGC_GPU2D),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
@@ -688,7 +692,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_VPUMIX,
+		.pgc   = BIT(IMX8MM_PGC_VPUMIX),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUG1] = {
@@ -699,7 +703,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
 			.map = IMX8MM_VPUG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_VPUG1,
+		.pgc   = BIT(IMX8MM_PGC_VPUG1),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUG2] = {
@@ -710,7 +714,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
 			.map = IMX8MM_VPUG2_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_VPUG2,
+		.pgc   = BIT(IMX8MM_PGC_VPUG2),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUH1] = {
@@ -721,7 +725,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
 			.map = IMX8MM_VPUH1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_VPUH1,
+		.pgc   = BIT(IMX8MM_PGC_VPUH1),
 	},
 
 	[IMX8MM_POWER_DOMAIN_DISPMIX] = {
@@ -734,7 +738,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_DISPMIX,
+		.pgc   = BIT(IMX8MM_PGC_DISPMIX),
 	},
 
 	[IMX8MM_POWER_DOMAIN_MIPI] = {
@@ -745,7 +749,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_MIPI_SW_Pxx_REQ,
 			.map = IMX8MM_MIPI_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_MIPI,
+		.pgc   = BIT(IMX8MM_PGC_MIPI),
 	},
 };
 
@@ -812,7 +816,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 			.pxx = IMX8MN_OTG1_SW_Pxx_REQ,
 			.map = IMX8MN_OTG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MN_PGC_OTG1,
+		.pgc   = BIT(IMX8MN_PGC_OTG1),
 	},
 
 	[IMX8MN_POWER_DOMAIN_GPUMIX] = {
@@ -825,7 +829,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 			.hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MN_PGC_GPUMIX,
+		.pgc   = BIT(IMX8MN_PGC_GPUMIX),
 	},
 };
 
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 02/18] soc: imx: gpcv2: Turn domain->pgc into bitfield
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

From: Marek Vasut <marex@denx.de>

There is currently the MX8MM GPU domain, which is in fact a composite domain
for both GPU2D and GPU3D. To correctly configure this domain, it is necessary
to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same
time. This is currently not possible.

Turn the domain->pgc from value into bitfield and use for_each_set_bit() to
iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL
register array. This way it is possible to configure all GPC_PGC_nCTRL
registers required in a particular domain.

This is a preparatory patch, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
v2 (Lucas Stach):
- rebase on top of reverted reset sequence change
- also convert i.MX8MN domains
---
 drivers/soc/imx/gpcv2.c | 72 ++++++++++++++++++++++-------------------
 1 file changed, 38 insertions(+), 34 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 8b7a01773aec..c7826ce92f0d 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -192,7 +192,7 @@ struct imx_pgc_domain {
 	struct clk_bulk_data *clks;
 	int num_clks;
 
-	unsigned int pgc;
+	unsigned long pgc;
 
 	const struct {
 		u32 pxx;
@@ -220,7 +220,7 @@ to_imx_pgc_domain(struct generic_pm_domain *genpd)
 static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 {
 	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
-	u32 reg_val;
+	u32 reg_val, pgc;
 	int ret;
 
 	ret = pm_runtime_get_sync(domain->dev);
@@ -264,8 +264,10 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 		}
 
 		/* disable power control */
-		regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
-				  GPC_PGC_CTRL_PCR);
+		for_each_set_bit(pgc, &domain->pgc, 32) {
+			regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
+					  GPC_PGC_CTRL_PCR);
+		}
 	}
 
 	/* delay for reset to propagate */
@@ -311,7 +313,7 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 {
 	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
-	u32 reg_val;
+	u32 reg_val, pgc;
 	int ret;
 
 	/* Enable reset clocks for all devices in the domain */
@@ -338,8 +340,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 
 	if (domain->bits.pxx) {
 		/* enable power control */
-		regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
-				   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+		for_each_set_bit(pgc, &domain->pgc, 32) {
+			regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
+					   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+		}
 
 		/* request the domain to power down */
 		regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
@@ -389,7 +393,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1000000,
-		.pgc	   = IMX7_PGC_MIPI,
+		.pgc	   = BIT(IMX7_PGC_MIPI),
 	},
 
 	[IMX7_POWER_DOMAIN_PCIE_PHY] = {
@@ -401,7 +405,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1000000,
-		.pgc	   = IMX7_PGC_PCIE,
+		.pgc	   = BIT(IMX7_PGC_PCIE),
 	},
 
 	[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
@@ -413,7 +417,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1200000,
-		.pgc	   = IMX7_PGC_USB_HSIC,
+		.pgc	   = BIT(IMX7_PGC_USB_HSIC),
 	},
 };
 
@@ -448,7 +452,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_MIPI_SW_Pxx_REQ,
 			.map = IMX8M_MIPI_A53_DOMAIN,
 		},
-		.pgc	   = IMX8M_PGC_MIPI,
+		.pgc	   = BIT(IMX8M_PGC_MIPI),
 	},
 
 	[IMX8M_POWER_DOMAIN_PCIE1] = {
@@ -459,7 +463,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_PCIE1_SW_Pxx_REQ,
 			.map = IMX8M_PCIE1_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_PCIE1,
+		.pgc   = BIT(IMX8M_PGC_PCIE1),
 	},
 
 	[IMX8M_POWER_DOMAIN_USB_OTG1] = {
@@ -470,7 +474,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_OTG1_SW_Pxx_REQ,
 			.map = IMX8M_OTG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_OTG1,
+		.pgc   = BIT(IMX8M_PGC_OTG1),
 	},
 
 	[IMX8M_POWER_DOMAIN_USB_OTG2] = {
@@ -481,7 +485,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_OTG2_SW_Pxx_REQ,
 			.map = IMX8M_OTG2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_OTG2,
+		.pgc   = BIT(IMX8M_PGC_OTG2),
 	},
 
 	[IMX8M_POWER_DOMAIN_DDR1] = {
@@ -492,7 +496,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_DDR1_SW_Pxx_REQ,
 			.map = IMX8M_DDR2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_DDR1,
+		.pgc   = BIT(IMX8M_PGC_DDR1),
 	},
 
 	[IMX8M_POWER_DOMAIN_GPU] = {
@@ -505,7 +509,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.hskreq = IMX8M_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8M_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8M_PGC_GPU,
+		.pgc   = BIT(IMX8M_PGC_GPU),
 	},
 
 	[IMX8M_POWER_DOMAIN_VPU] = {
@@ -518,7 +522,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.hskreq = IMX8M_VPU_HSK_PWRDNREQN,
 			.hskack = IMX8M_VPU_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8M_PGC_VPU,
+		.pgc   = BIT(IMX8M_PGC_VPU),
 	},
 
 	[IMX8M_POWER_DOMAIN_DISP] = {
@@ -531,7 +535,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.hskreq = IMX8M_DISP_HSK_PWRDNREQN,
 			.hskack = IMX8M_DISP_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8M_PGC_DISP,
+		.pgc   = BIT(IMX8M_PGC_DISP),
 	},
 
 	[IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
@@ -542,7 +546,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
 			.map = IMX8M_MIPI_CSI1_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_MIPI_CSI1,
+		.pgc   = BIT(IMX8M_PGC_MIPI_CSI1),
 	},
 
 	[IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
@@ -553,7 +557,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
 			.map = IMX8M_MIPI_CSI2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_MIPI_CSI2,
+		.pgc   = BIT(IMX8M_PGC_MIPI_CSI2),
 	},
 
 	[IMX8M_POWER_DOMAIN_PCIE2] = {
@@ -564,7 +568,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 			.pxx = IMX8M_PCIE2_SW_Pxx_REQ,
 			.map = IMX8M_PCIE2_A53_DOMAIN,
 		},
-		.pgc   = IMX8M_PGC_PCIE2,
+		.pgc   = BIT(IMX8M_PGC_PCIE2),
 	},
 };
 
@@ -627,7 +631,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_PCIE_SW_Pxx_REQ,
 			.map = IMX8MM_PCIE_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_PCIE,
+		.pgc   = BIT(IMX8MM_PGC_PCIE),
 	},
 
 	[IMX8MM_POWER_DOMAIN_OTG1] = {
@@ -638,7 +642,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_OTG1_SW_Pxx_REQ,
 			.map = IMX8MM_OTG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_OTG1,
+		.pgc   = BIT(IMX8MM_PGC_OTG1),
 	},
 
 	[IMX8MM_POWER_DOMAIN_OTG2] = {
@@ -649,7 +653,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_OTG2_SW_Pxx_REQ,
 			.map = IMX8MM_OTG2_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_OTG2,
+		.pgc   = BIT(IMX8MM_PGC_OTG2),
 	},
 
 	[IMX8MM_POWER_DOMAIN_GPUMIX] = {
@@ -662,7 +666,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_GPUMIX,
+		.pgc   = BIT(IMX8MM_PGC_GPUMIX),
 	},
 
 	[IMX8MM_POWER_DOMAIN_GPU] = {
@@ -675,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_GPU2D,
+		.pgc   = BIT(IMX8MM_PGC_GPU2D),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
@@ -688,7 +692,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_VPUMIX,
+		.pgc   = BIT(IMX8MM_PGC_VPUMIX),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUG1] = {
@@ -699,7 +703,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
 			.map = IMX8MM_VPUG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_VPUG1,
+		.pgc   = BIT(IMX8MM_PGC_VPUG1),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUG2] = {
@@ -710,7 +714,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
 			.map = IMX8MM_VPUG2_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_VPUG2,
+		.pgc   = BIT(IMX8MM_PGC_VPUG2),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUH1] = {
@@ -721,7 +725,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
 			.map = IMX8MM_VPUH1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_VPUH1,
+		.pgc   = BIT(IMX8MM_PGC_VPUH1),
 	},
 
 	[IMX8MM_POWER_DOMAIN_DISPMIX] = {
@@ -734,7 +738,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MM_PGC_DISPMIX,
+		.pgc   = BIT(IMX8MM_PGC_DISPMIX),
 	},
 
 	[IMX8MM_POWER_DOMAIN_MIPI] = {
@@ -745,7 +749,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.pxx = IMX8MM_MIPI_SW_Pxx_REQ,
 			.map = IMX8MM_MIPI_A53_DOMAIN,
 		},
-		.pgc   = IMX8MM_PGC_MIPI,
+		.pgc   = BIT(IMX8MM_PGC_MIPI),
 	},
 };
 
@@ -812,7 +816,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 			.pxx = IMX8MN_OTG1_SW_Pxx_REQ,
 			.map = IMX8MN_OTG1_A53_DOMAIN,
 		},
-		.pgc   = IMX8MN_PGC_OTG1,
+		.pgc   = BIT(IMX8MN_PGC_OTG1),
 	},
 
 	[IMX8MN_POWER_DOMAIN_GPUMIX] = {
@@ -825,7 +829,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 			.hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
 			.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
 		},
-		.pgc   = IMX8MN_PGC_GPUMIX,
+		.pgc   = BIT(IMX8MN_PGC_GPUMIX),
 	},
 };
 
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 03/18] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

From: Marek Vasut <marex@denx.de>

To bring up the MX8MM GPU domain, it is necessary to configure both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
this configuration, the system might hang on boot when bringing up
the GPU power domain. This is sporadically observed on multiple
disparate systems.

Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
configured when bringing up the GPU domain. This fixes the sporadic
hang.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index c7826ce92f0d..2c43e74db0be 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -679,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = BIT(IMX8MM_PGC_GPU2D),
+		.pgc   = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 03/18] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

From: Marek Vasut <marex@denx.de>

To bring up the MX8MM GPU domain, it is necessary to configure both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
this configuration, the system might hang on boot when bringing up
the GPU power domain. This is sporadically observed on multiple
disparate systems.

Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
configured when bringing up the GPU domain. This fixes the sporadic
hang.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index c7826ce92f0d..2c43e74db0be 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -679,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 		},
-		.pgc   = BIT(IMX8MM_PGC_GPU2D),
+		.pgc   = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 04/18] soc: imx: gpcv2: add lockdep annotation
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Some of the GPCv2 power domains are nested inside each other without
visibility to lockdep at the genpd level, as they are in separate
driver instances and don't have a parent/child power-domain relationship.

Add a subclass annotation to the nested domains to let lockdep know that
it is okay to take the genpd lock in a nested fashion.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 2c43e74db0be..35f26f57d1ac 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -898,6 +898,10 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
 		goto out_domain_unmap;
 	}
 
+	if (IS_ENABLED(CONFIG_LOCKDEP) &&
+	    of_property_read_bool(domain->dev->of_node, "power-domains"))
+		lockdep_set_subclass(&domain->genpd.mlock, 1);
+
 	ret = of_genpd_add_provider_simple(domain->dev->of_node,
 					   &domain->genpd);
 	if (ret) {
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 04/18] soc: imx: gpcv2: add lockdep annotation
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Some of the GPCv2 power domains are nested inside each other without
visibility to lockdep at the genpd level, as they are in separate
driver instances and don't have a parent/child power-domain relationship.

Add a subclass annotation to the nested domains to let lockdep know that
it is okay to take the genpd lock in a nested fashion.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 2c43e74db0be..35f26f57d1ac 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -898,6 +898,10 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
 		goto out_domain_unmap;
 	}
 
+	if (IS_ENABLED(CONFIG_LOCKDEP) &&
+	    of_property_read_bool(domain->dev->of_node, "power-domains"))
+		lockdep_set_subclass(&domain->genpd.mlock, 1);
+
 	ret = of_genpd_add_provider_simple(domain->dev->of_node,
 					   &domain->genpd);
 	if (ret) {
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 05/18] soc: imx: gpcv2: add domain option to keep domain clocks enabled
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Some of the MIX domains are using clocks to drive the bus bridges. Those
must be enabled at all times, as long as the domain is powered up and
they don't have any other consumer than the power domain. Add an option
to keep the clocks attached to a domain enabled as long as the domain
is power up and only disable them after the domain is powered down.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 35f26f57d1ac..c3b1d2580963 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -202,6 +202,7 @@ struct imx_pgc_domain {
 	} bits;
 
 	const int voltage;
+	const bool keep_clocks;
 	struct device *dev;
 };
 
@@ -295,7 +296,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 	}
 
 	/* Disable reset clocks for all devices in the domain */
-	clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
+	if (!domain->keep_clocks)
+		clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 
 	return 0;
 
@@ -317,10 +319,12 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 	int ret;
 
 	/* Enable reset clocks for all devices in the domain */
-	ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
-	if (ret) {
-		dev_err(domain->dev, "failed to enable reset clocks\n");
-		return ret;
+	if (!domain->keep_clocks) {
+		ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
+		if (ret) {
+			dev_err(domain->dev, "failed to enable reset clocks\n");
+			return ret;
+		}
 	}
 
 	/* request the ADB400 to power down */
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 05/18] soc: imx: gpcv2: add domain option to keep domain clocks enabled
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Some of the MIX domains are using clocks to drive the bus bridges. Those
must be enabled at all times, as long as the domain is powered up and
they don't have any other consumer than the power domain. Add an option
to keep the clocks attached to a domain enabled as long as the domain
is power up and only disable them after the domain is powered down.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 35f26f57d1ac..c3b1d2580963 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -202,6 +202,7 @@ struct imx_pgc_domain {
 	} bits;
 
 	const int voltage;
+	const bool keep_clocks;
 	struct device *dev;
 };
 
@@ -295,7 +296,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 	}
 
 	/* Disable reset clocks for all devices in the domain */
-	clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
+	if (!domain->keep_clocks)
+		clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 
 	return 0;
 
@@ -317,10 +319,12 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 	int ret;
 
 	/* Enable reset clocks for all devices in the domain */
-	ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
-	if (ret) {
-		dev_err(domain->dev, "failed to enable reset clocks\n");
-		return ret;
+	if (!domain->keep_clocks) {
+		ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
+		if (ret) {
+			dev_err(domain->dev, "failed to enable reset clocks\n");
+			return ret;
+		}
 	}
 
 	/* request the ADB400 to power down */
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 06/18] soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Annotate the domains with bus clocks to keep those clocks enabled
as long as the domain is active.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index c3b1d2580963..c48f37f203ab 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -625,6 +625,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
 			.hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
 		},
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_PCIE] = {
@@ -671,6 +672,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
 		},
 		.pgc   = BIT(IMX8MM_PGC_GPUMIX),
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_GPU] = {
@@ -697,6 +699,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
 		},
 		.pgc   = BIT(IMX8MM_PGC_VPUMIX),
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUG1] = {
@@ -743,6 +746,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
 		},
 		.pgc   = BIT(IMX8MM_PGC_DISPMIX),
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_MIPI] = {
@@ -810,6 +814,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 			.hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
 			.hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
 		},
+		.keep_clocks = true,
 	},
 
 	[IMX8MN_POWER_DOMAIN_OTG1] = {
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 06/18] soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Annotate the domains with bus clocks to keep those clocks enabled
as long as the domain is active.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index c3b1d2580963..c48f37f203ab 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -625,6 +625,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
 			.hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
 		},
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_PCIE] = {
@@ -671,6 +672,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
 		},
 		.pgc   = BIT(IMX8MM_PGC_GPUMIX),
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_GPU] = {
@@ -697,6 +699,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
 		},
 		.pgc   = BIT(IMX8MM_PGC_VPUMIX),
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_VPUG1] = {
@@ -743,6 +746,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 			.hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
 		},
 		.pgc   = BIT(IMX8MM_PGC_DISPMIX),
+		.keep_clocks = true,
 	},
 
 	[IMX8MM_POWER_DOMAIN_MIPI] = {
@@ -810,6 +814,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
 			.hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
 			.hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
 		},
+		.keep_clocks = true,
 	},
 
 	[IMX8MN_POWER_DOMAIN_OTG1] = {
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 07/18] soc: imx: gpcv2: support system suspend/resume
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Our usage of runtime PM to control the hierarchy of power domains is
slightly unusual and means that powering up a domain may fail in early
system resume, as runtime PM is still disallowed at this stage.

However the system suspend/resume path takes care of powering down/up
the power domains in the order defined by the device parent/child and
power-domain provider/consumer hierarachy. So we can just runtime
resume all our power-domain devices to allow the power-up to work
properly in the resume path. System suspend will still disable all
domains as intended.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index c48f37f203ab..57ed0a6bfb13 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -947,6 +947,36 @@ static int imx_pgc_domain_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int imx_pgc_domain_suspend(struct device *dev)
+{
+	int ret;
+
+	/*
+	 * This may look strange, but is done so the generic PM_SLEEP code
+	 * can power down our domain and more importantly power it up again
+	 * after resume, without tripping over our usage of runtime PM to
+	 * power up/down the nested domains.
+	 */
+	ret = pm_runtime_get_sync(dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(dev);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int imx_pgc_domain_resume(struct device *dev)
+{
+	return pm_runtime_put(dev);
+}
+#endif
+
+static const struct dev_pm_ops imx_pgc_domain_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(imx_pgc_domain_suspend, imx_pgc_domain_resume)
+};
+
 static const struct platform_device_id imx_pgc_domain_id[] = {
 	{ "imx-pgc-domain", },
 	{ },
@@ -955,6 +985,7 @@ static const struct platform_device_id imx_pgc_domain_id[] = {
 static struct platform_driver imx_pgc_domain_driver = {
 	.driver = {
 		.name = "imx-pgc",
+		.pm = &imx_pgc_domain_pm_ops,
 	},
 	.probe    = imx_pgc_domain_probe,
 	.remove   = imx_pgc_domain_remove,
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 07/18] soc: imx: gpcv2: support system suspend/resume
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Our usage of runtime PM to control the hierarchy of power domains is
slightly unusual and means that powering up a domain may fail in early
system resume, as runtime PM is still disallowed at this stage.

However the system suspend/resume path takes care of powering down/up
the power domains in the order defined by the device parent/child and
power-domain provider/consumer hierarachy. So we can just runtime
resume all our power-domain devices to allow the power-up to work
properly in the resume path. System suspend will still disable all
domains as intended.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/gpcv2.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index c48f37f203ab..57ed0a6bfb13 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -947,6 +947,36 @@ static int imx_pgc_domain_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int imx_pgc_domain_suspend(struct device *dev)
+{
+	int ret;
+
+	/*
+	 * This may look strange, but is done so the generic PM_SLEEP code
+	 * can power down our domain and more importantly power it up again
+	 * after resume, without tripping over our usage of runtime PM to
+	 * power up/down the nested domains.
+	 */
+	ret = pm_runtime_get_sync(dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(dev);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int imx_pgc_domain_resume(struct device *dev)
+{
+	return pm_runtime_put(dev);
+}
+#endif
+
+static const struct dev_pm_ops imx_pgc_domain_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(imx_pgc_domain_suspend, imx_pgc_domain_resume)
+};
+
 static const struct platform_device_id imx_pgc_domain_id[] = {
 	{ "imx-pgc-domain", },
 	{ },
@@ -955,6 +985,7 @@ static const struct platform_device_id imx_pgc_domain_id[] = {
 static struct platform_driver imx_pgc_domain_driver = {
 	.driver = {
 		.name = "imx-pgc",
+		.pm = &imx_pgc_domain_pm_ops,
 	},
 	.probe    = imx_pgc_domain_probe,
 	.remove   = imx_pgc_domain_remove,
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 08/18] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the DT binding for the i.MX8MM VPU blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      | 76 +++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
new file mode 100644
index 000000000000..3ea99e3d2b94
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MM VPU blk-ctrl
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+  The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
+  the NoC and ensuring proper power sequencing of the VPU peripherals
+  located in the VPU domain of the SoC.
+
+properties:
+  compatible:
+    items:
+      - const: fsl,imx8mm-vpu-blk-ctrl
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#power-domains-cells':
+    const: 1
+
+  power-domains:
+    minItems: 4
+    maxItems: 4
+
+  power-domain-names:
+    items:
+      - const: bus
+      - const: g1
+      - const: g2
+      - const: h1
+
+  clocks:
+    minItems: 3
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: g1
+      - const: g2
+      - const: h1
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mm-clock.h>
+    #include <dt-bindings/power/imx8mm-power.h>
+
+    vpu_blk_ctrl: blk-ctrl@38330000 {
+      compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
+      reg = <0x38330000 0x100>;
+      power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
+                      <&pgc_vpu_g2>, <&pgc_vpu_h1>;
+      power-domain-names = "bus", "g1", "g2", "h1";
+      clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
+               <&clk IMX8MM_CLK_VPU_G2_ROOT>,
+               <&clk IMX8MM_CLK_VPU_H1_ROOT>;
+      clock-names = "g1", "g2", "h1";
+      #power-domain-cells = <1>;
+    };
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 08/18] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the DT binding for the i.MX8MM VPU blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      | 76 +++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
new file mode 100644
index 000000000000..3ea99e3d2b94
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MM VPU blk-ctrl
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+  The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
+  the NoC and ensuring proper power sequencing of the VPU peripherals
+  located in the VPU domain of the SoC.
+
+properties:
+  compatible:
+    items:
+      - const: fsl,imx8mm-vpu-blk-ctrl
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#power-domains-cells':
+    const: 1
+
+  power-domains:
+    minItems: 4
+    maxItems: 4
+
+  power-domain-names:
+    items:
+      - const: bus
+      - const: g1
+      - const: g2
+      - const: h1
+
+  clocks:
+    minItems: 3
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: g1
+      - const: g2
+      - const: h1
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mm-clock.h>
+    #include <dt-bindings/power/imx8mm-power.h>
+
+    vpu_blk_ctrl: blk-ctrl@38330000 {
+      compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
+      reg = <0x38330000 0x100>;
+      power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
+                      <&pgc_vpu_g2>, <&pgc_vpu_h1>;
+      power-domain-names = "bus", "g1", "g2", "h1";
+      clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
+               <&clk IMX8MM_CLK_VPU_G2_ROOT>,
+               <&clk IMX8MM_CLK_VPU_H1_ROOT>;
+      clock-names = "g1", "g2", "h1";
+      #power-domain-cells = <1>;
+    };
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 09/18] dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the defines for the power domains provided by the VPU
blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 include/dt-bindings/power/imx8mm-power.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
index fc9c2e16aadc..38b0a56fd7d0 100644
--- a/include/dt-bindings/power/imx8mm-power.h
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -19,4 +19,8 @@
 #define IMX8MM_POWER_DOMAIN_DISPMIX	10
 #define IMX8MM_POWER_DOMAIN_MIPI	11
 
+#define IMX8MM_VPUBLK_PD_G1		0
+#define IMX8MM_VPUBLK_PD_G2		1
+#define IMX8MM_VPUBLK_PD_H1		2
+
 #endif
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 09/18] dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the defines for the power domains provided by the VPU
blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 include/dt-bindings/power/imx8mm-power.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
index fc9c2e16aadc..38b0a56fd7d0 100644
--- a/include/dt-bindings/power/imx8mm-power.h
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -19,4 +19,8 @@
 #define IMX8MM_POWER_DOMAIN_DISPMIX	10
 #define IMX8MM_POWER_DOMAIN_MIPI	11
 
+#define IMX8MM_VPUBLK_PD_G1		0
+#define IMX8MM_VPUBLK_PD_G2		1
+#define IMX8MM_VPUBLK_PD_H1		2
+
 #endif
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 10/18] soc: imx: add i.MX8M blk-ctrl driver
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds a driver for the blk-ctrl blocks found in the i.MX8M* line of
SoCs. The blk-ctrl is a top-level peripheral located in the various *MIX
power domains and interacts with the GPC power controller to provide the
peripherals in the power domain access to the NoC and ensures that those
peripherals are properly reset when their respective power domain is
brought back to life.

Software needs to do different things to make the bus handshake happen
after the the GPC *MIX domain is power up and before it is powered down.
As the requirements are quite different between the various blk-ctrls
there is a callback function provided to hook in the proper sequence.

The peripheral domains are quite uniform, they handle the soft clock
enables and resets in the blk-ctrl address space and sequencing with the
upstream GPC power domains.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
This commit includes the full code to drive the VPUMIX domain on the
i.MX8MM, as the skeleton driver would probably be harder to review
without the context provided by one blk-ctrl implementation. Other
blk-ctrl implementations will follow, based on this overall structure.
---
 drivers/soc/imx/Makefile         |   1 +
 drivers/soc/imx/imx8m-blk-ctrl.c | 455 +++++++++++++++++++++++++++++++
 2 files changed, 456 insertions(+)
 create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c

diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index 078dc918f4f3..8a707077914c 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -5,3 +5,4 @@ endif
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
 obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
+obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
new file mode 100644
index 000000000000..3dd17b903636
--- /dev/null
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2021 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/clk.h>
+
+#include <dt-bindings/power/imx8mm-power.h>
+
+#define BLK_SFT_RSTN	0x0
+#define BLK_CLK_EN	0x4
+
+struct imx8m_blk_ctrl_domain;
+
+struct imx8m_blk_ctrl {
+	struct device *dev;
+	struct notifier_block power_nb;
+	struct device *bus_power_dev;
+	struct regmap *regmap;
+	struct imx8m_blk_ctrl_domain *domains;
+	struct genpd_onecell_data onecell_data;
+};
+
+struct imx8m_blk_ctrl_domain_data {
+	const char *name;
+	const char **clk_names;
+	int num_clks;
+	const char *gpc_name;
+	u32 rst_mask;
+	u32 clk_mask;
+};
+
+#define DOMAIN_MAX_CLKS 3
+
+struct imx8m_blk_ctrl_domain {
+	struct generic_pm_domain genpd;
+	const struct imx8m_blk_ctrl_domain_data *data;
+	struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
+	struct device *power_dev;
+	struct imx8m_blk_ctrl *bc;
+};
+
+struct imx8m_blk_ctrl_data {
+	int max_reg;
+	notifier_fn_t power_notifier_fn;
+	const struct imx8m_blk_ctrl_domain_data *domains;
+	int num_domains;
+};
+
+static inline struct imx8m_blk_ctrl_domain *
+to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd)
+{
+	return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd);
+}
+
+static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd)
+{
+	struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);
+	const struct imx8m_blk_ctrl_domain_data *data = domain->data;
+	struct imx8m_blk_ctrl *bc = domain->bc;
+	int ret;
+
+	/* make sure bus domain is awake */
+	ret = pm_runtime_get_sync(bc->bus_power_dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(bc->bus_power_dev);
+		dev_err(bc->dev, "failed to power up bus domain\n");
+		return ret;
+	}
+
+	/* put devices into reset */
+	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
+
+	/* enable upstream and blk-ctrl clocks to allow reset to propagate */
+	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
+	if (ret) {
+		dev_err(bc->dev, "failed to enable clocks\n");
+		goto bus_put;
+	}
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
+
+	/* power up upstream GPC domain */
+	ret = pm_runtime_get_sync(domain->power_dev);
+	if (ret < 0) {
+		dev_err(bc->dev, "failed to power up peripheral domain\n");
+		goto clk_disable;
+	}
+
+	/* wait for reset to propagate */
+	udelay(5);
+
+	/* release reset */
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
+
+	/* disable upstream clocks */
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+
+	return 0;
+
+clk_disable:
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+bus_put:
+	pm_runtime_put(bc->bus_power_dev);
+
+	return ret;
+}
+
+static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd)
+{
+	struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);
+	const struct imx8m_blk_ctrl_domain_data *data = domain->data;
+	struct imx8m_blk_ctrl *bc = domain->bc;
+
+	/* put devices into reset and disable clocks */
+	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
+	regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
+
+	/* power down upstream GPC domain */
+	pm_runtime_put(domain->power_dev);
+
+	/* allow bus domain to suspend */
+	pm_runtime_put(bc->bus_power_dev);
+
+	return 0;
+}
+
+static struct generic_pm_domain *
+imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data)
+{
+	struct genpd_onecell_data *onecell_data = data;
+	unsigned int index = args->args[0];
+
+	if (args->args_count != 1 ||
+	    index > onecell_data->num_domains)
+		return ERR_PTR(-EINVAL);
+
+	return onecell_data->domains[index];
+}
+
+static struct lock_class_key blk_ctrl_genpd_lock_class;
+
+static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
+{
+	const struct imx8m_blk_ctrl_data *bc_data;
+	struct device *dev = &pdev->dev;
+	struct imx8m_blk_ctrl *bc;
+	void __iomem *base;
+	int i, ret;
+
+	struct regmap_config regmap_config = {
+		.reg_bits	= 32,
+		.val_bits	= 32,
+		.reg_stride	= 4,
+	};
+
+	bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
+	if (!bc)
+		return -ENOMEM;
+
+	bc->dev = dev;
+
+	bc_data = of_device_get_match_data(dev);
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	regmap_config.max_register = bc_data->max_reg;
+	bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
+	if (IS_ERR(bc->regmap))
+		return dev_err_probe(dev, PTR_ERR(bc->regmap),
+				     "failed to init regmap \n");
+
+	bc->domains = devm_kcalloc(dev, bc_data->num_domains,
+				    sizeof(struct imx8m_blk_ctrl_domain),
+				    GFP_KERNEL);
+	if (!bc->domains)
+		return -ENOMEM;
+
+	bc->onecell_data.num_domains = bc_data->num_domains;
+	bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
+	bc->onecell_data.domains =
+		devm_kcalloc(dev, bc_data->num_domains,
+			     sizeof(struct generic_pm_domain *), GFP_KERNEL);
+	if (!bc->onecell_data.domains)
+		return -ENOMEM;
+
+	bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
+	if (IS_ERR(bc->bus_power_dev))
+		return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
+				     "failed to attach power domain\n");
+
+	for (i = 0; i < bc_data->num_domains; i++) {
+		const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i];
+		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
+		int j;
+
+		domain->data = data;
+
+		for (j = 0; j < data->num_clks; j++)
+			domain->clks[j].id = data->clk_names[j];
+
+		ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
+		if (ret) {
+			dev_err_probe(dev, ret, "failed to get clock\n");
+			goto cleanup_pds;
+		}
+
+		domain->power_dev =
+			dev_pm_domain_attach_by_name(dev, data->gpc_name);
+		if (IS_ERR(domain->power_dev)) {
+			dev_err_probe(dev, PTR_ERR(domain->power_dev),
+				      "failed to attach power domain\n");
+			ret = PTR_ERR(domain->power_dev);
+			goto cleanup_pds;
+		}
+
+		domain->genpd.name = data->name;
+		domain->genpd.power_on = imx8m_blk_ctrl_power_on;
+		domain->genpd.power_off = imx8m_blk_ctrl_power_off;
+		domain->bc = bc;
+
+		ret = pm_genpd_init(&domain->genpd, NULL, true);
+		if (ret) {
+			dev_err_probe(dev, ret, "failed to init power domain\n");
+			dev_pm_domain_detach(domain->power_dev, true);
+			goto cleanup_pds;
+		}
+
+		/*
+		 * We use runtime PM to trigger power on/off of the upstream GPC
+		 * domain, as a strict hierarchical parent/child power domain
+		 * setup doesn't allow us to meet the sequencing requirements.
+		 * This means we have nested locking of genpd locks, without the
+		 * nesting being visible at the genpd level, so we need a
+		 * separate lock class to make lockdep aware of the fact that
+		 * this are separate domain locks that can be nested without a
+		 * self-deadlock.
+		 */
+		lockdep_set_class(&domain->genpd.mlock,
+				  &blk_ctrl_genpd_lock_class);
+
+		bc->onecell_data.domains[i] = &domain->genpd;
+	}
+
+	ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to add power domain provider\n");
+		goto cleanup_pds;
+	}
+
+	bc->power_nb.notifier_call = bc_data->power_notifier_fn;
+	ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to add power notifier\n");
+		goto cleanup_provider;
+	}
+
+	dev_set_drvdata(dev, bc);
+
+	return 0;
+
+cleanup_provider:
+	of_genpd_del_provider(dev->of_node);
+cleanup_pds:
+	for (i--; i >= 0; i--) {
+		pm_genpd_remove(&bc->domains[i].genpd);
+		dev_pm_domain_detach(bc->domains[i].power_dev, true);
+	}
+
+	dev_pm_domain_detach(bc->bus_power_dev, true);
+
+	return ret;
+}
+
+static int imx8m_blk_ctrl_remove(struct platform_device *pdev)
+{
+	struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
+	int i;
+
+	of_genpd_del_provider(pdev->dev.of_node);
+
+	for (i = 0; bc->onecell_data.num_domains; i++) {
+		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
+
+		pm_genpd_remove(&domain->genpd);
+		dev_pm_domain_detach(domain->power_dev, true);
+	}
+
+	dev_pm_genpd_remove_notifier(bc->bus_power_dev);
+
+	dev_pm_domain_detach(bc->bus_power_dev, true);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int imx8m_blk_ctrl_suspend(struct device *dev)
+{
+	struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);
+	int ret, i;
+
+	/*
+	 * This may look strange, but is done so the generic PM_SLEEP code
+	 * can power down our domains and more importantly power them up again
+	 * after resume, without tripping over our usage of runtime PM to
+	 * control the upstream GPC domains. Things happen in the right order
+	 * in the system suspend/resume paths due to the device parent/child
+	 * hierarchy.
+	 */
+	ret = pm_runtime_get_sync(bc->bus_power_dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(bc->bus_power_dev);
+		return ret;
+	}
+
+	for (i = 0; i < bc->onecell_data.num_domains; i++) {
+		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
+
+		ret = pm_runtime_get_sync(domain->power_dev);
+		if (ret < 0) {
+			pm_runtime_put_noidle(domain->power_dev);
+			goto out_fail;
+		}
+	}
+
+	return 0;
+
+out_fail:
+	for (i--; i >= 0; i--)
+		pm_runtime_put(bc->domains[i].power_dev);
+
+	pm_runtime_put(bc->bus_power_dev);
+
+	return ret;
+}
+
+static int imx8m_blk_ctrl_resume(struct device *dev)
+{
+	struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < bc->onecell_data.num_domains; i++)
+		pm_runtime_put(bc->domains[i].power_dev);
+
+	pm_runtime_put(bc->bus_power_dev);
+
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops imx8m_blk_ctrl_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(imx8m_blk_ctrl_suspend, imx8m_blk_ctrl_resume)
+};
+
+static int imx8mm_vpu_power_notifier(struct notifier_block *nb,
+				     unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/*
+	 * The ADB in the VPUMIX domain has no separate reset and clock
+	 * enable bits, but is ungated together with the VPU clocks. To
+	 * allow the handshake with the GPC to progress we put the VPUs
+	 * in reset and ungate the clocks.
+	 */
+	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN,
+			  BIT(0) | BIT(1) | BIT(2));
+	regmap_set_bits(bc->regmap, BLK_CLK_EN,
+			BIT(0) | BIT(1) | BIT(2));
+
+	if (action == GENPD_NOTIFY_ON) {
+		/*
+		 * On power up we have no software backchannel to the GPC to
+		 * wait for the ADB handshake to happen, so we just delay for a
+		 * bit. On power down the GPC driver waits for the handshake.
+		 */
+		udelay(5);
+
+		/* set "fuse" bits to enable the VPUs */
+		regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0x14, 0xffffffff);
+	}
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8m_blk_ctrl_domain_data imx8m_vpu_blk_ctl_domain_data[] = {
+	[IMX8MM_VPUBLK_PD_G1] = {
+		.name = "vpublk-g1",
+		.clk_names = (const char *[]){ "g1", },
+		.num_clks = 1,
+		.gpc_name = "g1",
+		.rst_mask = BIT(1),
+		.clk_mask = BIT(1),
+	},
+	[IMX8MM_VPUBLK_PD_G2] = {
+		.name = "vpublk-g2",
+		.clk_names = (const char *[]){ "g2", },
+		.num_clks = 1,
+		.gpc_name = "g2",
+		.rst_mask = BIT(0),
+		.clk_mask = BIT(0),
+	},
+	[IMX8MM_VPUBLK_PD_H1] = {
+		.name = "vpublk-h1",
+		.clk_names = (const char *[]){ "h1", },
+		.num_clks = 1,
+		.gpc_name = "h1",
+		.rst_mask = BIT(2),
+		.clk_mask = BIT(2),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8m_vpu_blk_ctl_dev_data = {
+	.max_reg = 0x18,
+	.power_notifier_fn = imx8mm_vpu_power_notifier,
+	.domains = imx8m_vpu_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
+};
+
+static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
+	{
+		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
+		.data = &imx8m_vpu_blk_ctl_dev_data
+	}, {
+		/* Sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
+
+static struct platform_driver imx8m_blk_ctrl_driver = {
+	.probe = imx8m_blk_ctrl_probe,
+	.remove = imx8m_blk_ctrl_remove,
+	.driver = {
+		.name = "imx8m-blk-ctrl",
+		.pm = &imx8m_blk_ctrl_pm_ops,
+		.of_match_table = imx8m_blk_ctrl_of_match,
+	},
+};
+module_platform_driver(imx8m_blk_ctrl_driver);
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 10/18] soc: imx: add i.MX8M blk-ctrl driver
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds a driver for the blk-ctrl blocks found in the i.MX8M* line of
SoCs. The blk-ctrl is a top-level peripheral located in the various *MIX
power domains and interacts with the GPC power controller to provide the
peripherals in the power domain access to the NoC and ensures that those
peripherals are properly reset when their respective power domain is
brought back to life.

Software needs to do different things to make the bus handshake happen
after the the GPC *MIX domain is power up and before it is powered down.
As the requirements are quite different between the various blk-ctrls
there is a callback function provided to hook in the proper sequence.

The peripheral domains are quite uniform, they handle the soft clock
enables and resets in the blk-ctrl address space and sequencing with the
upstream GPC power domains.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
This commit includes the full code to drive the VPUMIX domain on the
i.MX8MM, as the skeleton driver would probably be harder to review
without the context provided by one blk-ctrl implementation. Other
blk-ctrl implementations will follow, based on this overall structure.
---
 drivers/soc/imx/Makefile         |   1 +
 drivers/soc/imx/imx8m-blk-ctrl.c | 455 +++++++++++++++++++++++++++++++
 2 files changed, 456 insertions(+)
 create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c

diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index 078dc918f4f3..8a707077914c 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -5,3 +5,4 @@ endif
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
 obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
+obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
new file mode 100644
index 000000000000..3dd17b903636
--- /dev/null
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2021 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/clk.h>
+
+#include <dt-bindings/power/imx8mm-power.h>
+
+#define BLK_SFT_RSTN	0x0
+#define BLK_CLK_EN	0x4
+
+struct imx8m_blk_ctrl_domain;
+
+struct imx8m_blk_ctrl {
+	struct device *dev;
+	struct notifier_block power_nb;
+	struct device *bus_power_dev;
+	struct regmap *regmap;
+	struct imx8m_blk_ctrl_domain *domains;
+	struct genpd_onecell_data onecell_data;
+};
+
+struct imx8m_blk_ctrl_domain_data {
+	const char *name;
+	const char **clk_names;
+	int num_clks;
+	const char *gpc_name;
+	u32 rst_mask;
+	u32 clk_mask;
+};
+
+#define DOMAIN_MAX_CLKS 3
+
+struct imx8m_blk_ctrl_domain {
+	struct generic_pm_domain genpd;
+	const struct imx8m_blk_ctrl_domain_data *data;
+	struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
+	struct device *power_dev;
+	struct imx8m_blk_ctrl *bc;
+};
+
+struct imx8m_blk_ctrl_data {
+	int max_reg;
+	notifier_fn_t power_notifier_fn;
+	const struct imx8m_blk_ctrl_domain_data *domains;
+	int num_domains;
+};
+
+static inline struct imx8m_blk_ctrl_domain *
+to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd)
+{
+	return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd);
+}
+
+static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd)
+{
+	struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);
+	const struct imx8m_blk_ctrl_domain_data *data = domain->data;
+	struct imx8m_blk_ctrl *bc = domain->bc;
+	int ret;
+
+	/* make sure bus domain is awake */
+	ret = pm_runtime_get_sync(bc->bus_power_dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(bc->bus_power_dev);
+		dev_err(bc->dev, "failed to power up bus domain\n");
+		return ret;
+	}
+
+	/* put devices into reset */
+	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
+
+	/* enable upstream and blk-ctrl clocks to allow reset to propagate */
+	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
+	if (ret) {
+		dev_err(bc->dev, "failed to enable clocks\n");
+		goto bus_put;
+	}
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
+
+	/* power up upstream GPC domain */
+	ret = pm_runtime_get_sync(domain->power_dev);
+	if (ret < 0) {
+		dev_err(bc->dev, "failed to power up peripheral domain\n");
+		goto clk_disable;
+	}
+
+	/* wait for reset to propagate */
+	udelay(5);
+
+	/* release reset */
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
+
+	/* disable upstream clocks */
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+
+	return 0;
+
+clk_disable:
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+bus_put:
+	pm_runtime_put(bc->bus_power_dev);
+
+	return ret;
+}
+
+static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd)
+{
+	struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);
+	const struct imx8m_blk_ctrl_domain_data *data = domain->data;
+	struct imx8m_blk_ctrl *bc = domain->bc;
+
+	/* put devices into reset and disable clocks */
+	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
+	regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
+
+	/* power down upstream GPC domain */
+	pm_runtime_put(domain->power_dev);
+
+	/* allow bus domain to suspend */
+	pm_runtime_put(bc->bus_power_dev);
+
+	return 0;
+}
+
+static struct generic_pm_domain *
+imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data)
+{
+	struct genpd_onecell_data *onecell_data = data;
+	unsigned int index = args->args[0];
+
+	if (args->args_count != 1 ||
+	    index > onecell_data->num_domains)
+		return ERR_PTR(-EINVAL);
+
+	return onecell_data->domains[index];
+}
+
+static struct lock_class_key blk_ctrl_genpd_lock_class;
+
+static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
+{
+	const struct imx8m_blk_ctrl_data *bc_data;
+	struct device *dev = &pdev->dev;
+	struct imx8m_blk_ctrl *bc;
+	void __iomem *base;
+	int i, ret;
+
+	struct regmap_config regmap_config = {
+		.reg_bits	= 32,
+		.val_bits	= 32,
+		.reg_stride	= 4,
+	};
+
+	bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
+	if (!bc)
+		return -ENOMEM;
+
+	bc->dev = dev;
+
+	bc_data = of_device_get_match_data(dev);
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	regmap_config.max_register = bc_data->max_reg;
+	bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
+	if (IS_ERR(bc->regmap))
+		return dev_err_probe(dev, PTR_ERR(bc->regmap),
+				     "failed to init regmap \n");
+
+	bc->domains = devm_kcalloc(dev, bc_data->num_domains,
+				    sizeof(struct imx8m_blk_ctrl_domain),
+				    GFP_KERNEL);
+	if (!bc->domains)
+		return -ENOMEM;
+
+	bc->onecell_data.num_domains = bc_data->num_domains;
+	bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
+	bc->onecell_data.domains =
+		devm_kcalloc(dev, bc_data->num_domains,
+			     sizeof(struct generic_pm_domain *), GFP_KERNEL);
+	if (!bc->onecell_data.domains)
+		return -ENOMEM;
+
+	bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
+	if (IS_ERR(bc->bus_power_dev))
+		return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
+				     "failed to attach power domain\n");
+
+	for (i = 0; i < bc_data->num_domains; i++) {
+		const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i];
+		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
+		int j;
+
+		domain->data = data;
+
+		for (j = 0; j < data->num_clks; j++)
+			domain->clks[j].id = data->clk_names[j];
+
+		ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
+		if (ret) {
+			dev_err_probe(dev, ret, "failed to get clock\n");
+			goto cleanup_pds;
+		}
+
+		domain->power_dev =
+			dev_pm_domain_attach_by_name(dev, data->gpc_name);
+		if (IS_ERR(domain->power_dev)) {
+			dev_err_probe(dev, PTR_ERR(domain->power_dev),
+				      "failed to attach power domain\n");
+			ret = PTR_ERR(domain->power_dev);
+			goto cleanup_pds;
+		}
+
+		domain->genpd.name = data->name;
+		domain->genpd.power_on = imx8m_blk_ctrl_power_on;
+		domain->genpd.power_off = imx8m_blk_ctrl_power_off;
+		domain->bc = bc;
+
+		ret = pm_genpd_init(&domain->genpd, NULL, true);
+		if (ret) {
+			dev_err_probe(dev, ret, "failed to init power domain\n");
+			dev_pm_domain_detach(domain->power_dev, true);
+			goto cleanup_pds;
+		}
+
+		/*
+		 * We use runtime PM to trigger power on/off of the upstream GPC
+		 * domain, as a strict hierarchical parent/child power domain
+		 * setup doesn't allow us to meet the sequencing requirements.
+		 * This means we have nested locking of genpd locks, without the
+		 * nesting being visible at the genpd level, so we need a
+		 * separate lock class to make lockdep aware of the fact that
+		 * this are separate domain locks that can be nested without a
+		 * self-deadlock.
+		 */
+		lockdep_set_class(&domain->genpd.mlock,
+				  &blk_ctrl_genpd_lock_class);
+
+		bc->onecell_data.domains[i] = &domain->genpd;
+	}
+
+	ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to add power domain provider\n");
+		goto cleanup_pds;
+	}
+
+	bc->power_nb.notifier_call = bc_data->power_notifier_fn;
+	ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to add power notifier\n");
+		goto cleanup_provider;
+	}
+
+	dev_set_drvdata(dev, bc);
+
+	return 0;
+
+cleanup_provider:
+	of_genpd_del_provider(dev->of_node);
+cleanup_pds:
+	for (i--; i >= 0; i--) {
+		pm_genpd_remove(&bc->domains[i].genpd);
+		dev_pm_domain_detach(bc->domains[i].power_dev, true);
+	}
+
+	dev_pm_domain_detach(bc->bus_power_dev, true);
+
+	return ret;
+}
+
+static int imx8m_blk_ctrl_remove(struct platform_device *pdev)
+{
+	struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
+	int i;
+
+	of_genpd_del_provider(pdev->dev.of_node);
+
+	for (i = 0; bc->onecell_data.num_domains; i++) {
+		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
+
+		pm_genpd_remove(&domain->genpd);
+		dev_pm_domain_detach(domain->power_dev, true);
+	}
+
+	dev_pm_genpd_remove_notifier(bc->bus_power_dev);
+
+	dev_pm_domain_detach(bc->bus_power_dev, true);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int imx8m_blk_ctrl_suspend(struct device *dev)
+{
+	struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);
+	int ret, i;
+
+	/*
+	 * This may look strange, but is done so the generic PM_SLEEP code
+	 * can power down our domains and more importantly power them up again
+	 * after resume, without tripping over our usage of runtime PM to
+	 * control the upstream GPC domains. Things happen in the right order
+	 * in the system suspend/resume paths due to the device parent/child
+	 * hierarchy.
+	 */
+	ret = pm_runtime_get_sync(bc->bus_power_dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(bc->bus_power_dev);
+		return ret;
+	}
+
+	for (i = 0; i < bc->onecell_data.num_domains; i++) {
+		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
+
+		ret = pm_runtime_get_sync(domain->power_dev);
+		if (ret < 0) {
+			pm_runtime_put_noidle(domain->power_dev);
+			goto out_fail;
+		}
+	}
+
+	return 0;
+
+out_fail:
+	for (i--; i >= 0; i--)
+		pm_runtime_put(bc->domains[i].power_dev);
+
+	pm_runtime_put(bc->bus_power_dev);
+
+	return ret;
+}
+
+static int imx8m_blk_ctrl_resume(struct device *dev)
+{
+	struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < bc->onecell_data.num_domains; i++)
+		pm_runtime_put(bc->domains[i].power_dev);
+
+	pm_runtime_put(bc->bus_power_dev);
+
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops imx8m_blk_ctrl_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(imx8m_blk_ctrl_suspend, imx8m_blk_ctrl_resume)
+};
+
+static int imx8mm_vpu_power_notifier(struct notifier_block *nb,
+				     unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/*
+	 * The ADB in the VPUMIX domain has no separate reset and clock
+	 * enable bits, but is ungated together with the VPU clocks. To
+	 * allow the handshake with the GPC to progress we put the VPUs
+	 * in reset and ungate the clocks.
+	 */
+	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN,
+			  BIT(0) | BIT(1) | BIT(2));
+	regmap_set_bits(bc->regmap, BLK_CLK_EN,
+			BIT(0) | BIT(1) | BIT(2));
+
+	if (action == GENPD_NOTIFY_ON) {
+		/*
+		 * On power up we have no software backchannel to the GPC to
+		 * wait for the ADB handshake to happen, so we just delay for a
+		 * bit. On power down the GPC driver waits for the handshake.
+		 */
+		udelay(5);
+
+		/* set "fuse" bits to enable the VPUs */
+		regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0x14, 0xffffffff);
+	}
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8m_blk_ctrl_domain_data imx8m_vpu_blk_ctl_domain_data[] = {
+	[IMX8MM_VPUBLK_PD_G1] = {
+		.name = "vpublk-g1",
+		.clk_names = (const char *[]){ "g1", },
+		.num_clks = 1,
+		.gpc_name = "g1",
+		.rst_mask = BIT(1),
+		.clk_mask = BIT(1),
+	},
+	[IMX8MM_VPUBLK_PD_G2] = {
+		.name = "vpublk-g2",
+		.clk_names = (const char *[]){ "g2", },
+		.num_clks = 1,
+		.gpc_name = "g2",
+		.rst_mask = BIT(0),
+		.clk_mask = BIT(0),
+	},
+	[IMX8MM_VPUBLK_PD_H1] = {
+		.name = "vpublk-h1",
+		.clk_names = (const char *[]){ "h1", },
+		.num_clks = 1,
+		.gpc_name = "h1",
+		.rst_mask = BIT(2),
+		.clk_mask = BIT(2),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8m_vpu_blk_ctl_dev_data = {
+	.max_reg = 0x18,
+	.power_notifier_fn = imx8mm_vpu_power_notifier,
+	.domains = imx8m_vpu_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
+};
+
+static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
+	{
+		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
+		.data = &imx8m_vpu_blk_ctl_dev_data
+	}, {
+		/* Sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
+
+static struct platform_driver imx8m_blk_ctrl_driver = {
+	.probe = imx8m_blk_ctrl_probe,
+	.remove = imx8m_blk_ctrl_remove,
+	.driver = {
+		.name = "imx8m-blk-ctrl",
+		.pm = &imx8m_blk_ctrl_pm_ops,
+		.of_match_table = imx8m_blk_ctrl_of_match,
+	},
+};
+module_platform_driver(imx8m_blk_ctrl_driver);
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 11/18] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the DT binding for the i.MX8MM VPU blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     | 94 +++++++++++++++++++
 1 file changed, 94 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
new file mode 100644
index 000000000000..84887909d01a
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MM DISP blk-ctrl
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+  The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
+  the NoC and ensuring proper power sequencing of the display and MIPI CSI
+  peripherals located in the DISP domain of the SoC.
+
+properties:
+  compatible:
+    items:
+      - const: fsl,imx8mm-disp-blk-ctrl
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#power-domains-cells':
+    const: 1
+
+  power-domains:
+    minItems: 5
+    maxItems: 5
+
+  power-domain-names:
+    items:
+      - const: bus
+      - const: csi-bridge
+      - const: lcdif
+      - const: mipi-dsi
+      - const: mipi-csi
+
+  clocks:
+    minItems: 10
+    maxItems: 10
+
+  clock-names:
+    items:
+      - const: csi-bridge-axi
+      - const: csi-bridge-apb
+      - const: csi-bridge-core
+      - const: lcdif-axi
+      - const: lcdif-apb
+      - const: lcdif-pix
+      - const: dsi-pclk
+      - const: dsi-ref
+      - const: csi-aclk
+      - const: csi-pclk
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mm-clock.h>
+    #include <dt-bindings/power/imx8mm-power.h>
+
+    disp_blk_ctl: blk_ctrl@32e28000 {
+      compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
+      reg = <0x32e28000 0x100>;
+      power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>,
+                      <&pgc_mipi>, <&pgc_mipi>;
+      power-domain-names = "bus", "csi-bridge", "lcdif",
+                           "mipi-dsi", "mipi-csi";
+      clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+               <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+               <&clk IMX8MM_CLK_CSI1_ROOT>,
+               <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+               <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+               <&clk IMX8MM_CLK_DISP_ROOT>,
+               <&clk IMX8MM_CLK_DSI_CORE>,
+               <&clk IMX8MM_CLK_DSI_PHY_REF>,
+               <&clk IMX8MM_CLK_CSI1_CORE>,
+               <&clk IMX8MM_CLK_CSI1_PHY_REF>;
+       clock-names = "csi-bridge-axi", "csi-bridge-apb", "csi-bridge-core",
+                     "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
+                     "dsi-ref", "csi-aclk", "csi-pclk";
+       #power-domain-cells = <1>;
+    };
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 11/18] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the DT binding for the i.MX8MM VPU blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     | 94 +++++++++++++++++++
 1 file changed, 94 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
new file mode 100644
index 000000000000..84887909d01a
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MM DISP blk-ctrl
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+  The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
+  the NoC and ensuring proper power sequencing of the display and MIPI CSI
+  peripherals located in the DISP domain of the SoC.
+
+properties:
+  compatible:
+    items:
+      - const: fsl,imx8mm-disp-blk-ctrl
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#power-domains-cells':
+    const: 1
+
+  power-domains:
+    minItems: 5
+    maxItems: 5
+
+  power-domain-names:
+    items:
+      - const: bus
+      - const: csi-bridge
+      - const: lcdif
+      - const: mipi-dsi
+      - const: mipi-csi
+
+  clocks:
+    minItems: 10
+    maxItems: 10
+
+  clock-names:
+    items:
+      - const: csi-bridge-axi
+      - const: csi-bridge-apb
+      - const: csi-bridge-core
+      - const: lcdif-axi
+      - const: lcdif-apb
+      - const: lcdif-pix
+      - const: dsi-pclk
+      - const: dsi-ref
+      - const: csi-aclk
+      - const: csi-pclk
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mm-clock.h>
+    #include <dt-bindings/power/imx8mm-power.h>
+
+    disp_blk_ctl: blk_ctrl@32e28000 {
+      compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
+      reg = <0x32e28000 0x100>;
+      power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>,
+                      <&pgc_mipi>, <&pgc_mipi>;
+      power-domain-names = "bus", "csi-bridge", "lcdif",
+                           "mipi-dsi", "mipi-csi";
+      clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+               <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+               <&clk IMX8MM_CLK_CSI1_ROOT>,
+               <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+               <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+               <&clk IMX8MM_CLK_DISP_ROOT>,
+               <&clk IMX8MM_CLK_DSI_CORE>,
+               <&clk IMX8MM_CLK_DSI_PHY_REF>,
+               <&clk IMX8MM_CLK_CSI1_CORE>,
+               <&clk IMX8MM_CLK_CSI1_PHY_REF>;
+       clock-names = "csi-bridge-axi", "csi-bridge-apb", "csi-bridge-core",
+                     "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
+                     "dsi-ref", "csi-aclk", "csi-pclk";
+       #power-domain-cells = <1>;
+    };
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 12/18] dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the defines for the power domains provided by the DISP
blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 include/dt-bindings/power/imx8mm-power.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
index 38b0a56fd7d0..d7f7cdb5200f 100644
--- a/include/dt-bindings/power/imx8mm-power.h
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -23,4 +23,9 @@
 #define IMX8MM_VPUBLK_PD_G2		1
 #define IMX8MM_VPUBLK_PD_H1		2
 
+#define IMX8MM_DISPBLK_CSI_BRIDGE	0
+#define IMX8MM_DISPBLK_LCDIF		1
+#define IMX8MM_DISPBLK_MIPI_DSI		2
+#define IMX8MM_DISPBLK_MIPI_CSI		3
+
 #endif
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 12/18] dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the defines for the power domains provided by the DISP
blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 include/dt-bindings/power/imx8mm-power.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
index 38b0a56fd7d0..d7f7cdb5200f 100644
--- a/include/dt-bindings/power/imx8mm-power.h
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -23,4 +23,9 @@
 #define IMX8MM_VPUBLK_PD_G2		1
 #define IMX8MM_VPUBLK_PD_H1		2
 
+#define IMX8MM_DISPBLK_CSI_BRIDGE	0
+#define IMX8MM_DISPBLK_LCDIF		1
+#define IMX8MM_DISPBLK_MIPI_DSI		2
+#define IMX8MM_DISPBLK_MIPI_CSI		3
+
 #endif
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 13/18] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the description for the i.MX8MM disp blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/imx8m-blk-ctrl.c | 70 ++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 3dd17b903636..32eab800a3c6 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -433,11 +433,81 @@ static const struct imx8m_blk_ctrl_data imx8m_vpu_blk_ctl_dev_data = {
 	.num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
 };
 
+static int imx8mm_disp_power_notifier(struct notifier_block *nb,
+				      unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/* Enable bus clock and deassert bus reset */
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12));
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6));
+
+	/*
+	 * On power up we have no software backchannel to the GPC to
+	 * wait for the ADB handshake to happen, so we just delay for a
+	 * bit. On power down the GPC driver waits for the handshake.
+	 */
+	if (action == GENPD_NOTIFY_ON)
+		udelay(5);
+
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8m_blk_ctrl_domain_data imx8m_disp_blk_ctl_domain_data[] = {
+	[IMX8MM_DISPBLK_CSI_BRIDGE] = {
+		.name = "dispblk-csi-bridge",
+		.clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb",
+					       "csi-bridge-core", },
+		.num_clks = 3,
+		.gpc_name = "csi-bridge",
+		.rst_mask = BIT(0) | BIT(1) | BIT(2),
+		.clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
+	},
+	[IMX8MM_DISPBLK_LCDIF] = {
+		.name = "dispblk-lcdif",
+		.clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
+		.num_clks = 3,
+		.gpc_name = "lcdif",
+		.clk_mask = BIT(6) | BIT(7),
+	},
+	[IMX8MM_DISPBLK_MIPI_DSI] = {
+		.name = "dispblk-mipi-dsi",
+		.clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
+		.num_clks = 2,
+		.gpc_name = "mipi-dsi",
+		.rst_mask = BIT(5),
+		.clk_mask = BIT(8) | BIT(9),
+	},
+	[IMX8MM_DISPBLK_MIPI_CSI] = {
+		.name = "dispblk-mipi-csi",
+		.clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
+		.num_clks = 2,
+		.gpc_name = "mipi-csi",
+		.rst_mask = BIT(3) | BIT(4),
+		.clk_mask = BIT(10) | BIT(11),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8m_disp_blk_ctl_dev_data = {
+	.max_reg = 0x2c,
+	.power_notifier_fn = imx8mm_disp_power_notifier,
+	.domains = imx8m_disp_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8m_disp_blk_ctl_domain_data),
+};
+
 static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
 	{
 		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
 		.data = &imx8m_vpu_blk_ctl_dev_data
 	}, {
+		.compatible = "fsl,imx8mm-disp-blk-ctrl",
+		.data = &imx8m_disp_blk_ctl_dev_data
+	} ,{
 		/* Sentinel */
 	}
 };
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 13/18] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

This adds the description for the i.MX8MM disp blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/imx8m-blk-ctrl.c | 70 ++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 3dd17b903636..32eab800a3c6 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -433,11 +433,81 @@ static const struct imx8m_blk_ctrl_data imx8m_vpu_blk_ctl_dev_data = {
 	.num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
 };
 
+static int imx8mm_disp_power_notifier(struct notifier_block *nb,
+				      unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/* Enable bus clock and deassert bus reset */
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12));
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6));
+
+	/*
+	 * On power up we have no software backchannel to the GPC to
+	 * wait for the ADB handshake to happen, so we just delay for a
+	 * bit. On power down the GPC driver waits for the handshake.
+	 */
+	if (action == GENPD_NOTIFY_ON)
+		udelay(5);
+
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8m_blk_ctrl_domain_data imx8m_disp_blk_ctl_domain_data[] = {
+	[IMX8MM_DISPBLK_CSI_BRIDGE] = {
+		.name = "dispblk-csi-bridge",
+		.clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb",
+					       "csi-bridge-core", },
+		.num_clks = 3,
+		.gpc_name = "csi-bridge",
+		.rst_mask = BIT(0) | BIT(1) | BIT(2),
+		.clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
+	},
+	[IMX8MM_DISPBLK_LCDIF] = {
+		.name = "dispblk-lcdif",
+		.clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
+		.num_clks = 3,
+		.gpc_name = "lcdif",
+		.clk_mask = BIT(6) | BIT(7),
+	},
+	[IMX8MM_DISPBLK_MIPI_DSI] = {
+		.name = "dispblk-mipi-dsi",
+		.clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
+		.num_clks = 2,
+		.gpc_name = "mipi-dsi",
+		.rst_mask = BIT(5),
+		.clk_mask = BIT(8) | BIT(9),
+	},
+	[IMX8MM_DISPBLK_MIPI_CSI] = {
+		.name = "dispblk-mipi-csi",
+		.clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
+		.num_clks = 2,
+		.gpc_name = "mipi-csi",
+		.rst_mask = BIT(3) | BIT(4),
+		.clk_mask = BIT(10) | BIT(11),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8m_disp_blk_ctl_dev_data = {
+	.max_reg = 0x2c,
+	.power_notifier_fn = imx8mm_disp_power_notifier,
+	.domains = imx8m_disp_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8m_disp_blk_ctl_domain_data),
+};
+
 static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
 	{
 		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
 		.data = &imx8m_vpu_blk_ctl_dev_data
 	}, {
+		.compatible = "fsl,imx8mm-disp-blk-ctrl",
+		.data = &imx8m_disp_blk_ctl_dev_data
+	} ,{
 		/* Sentinel */
 	}
 };
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 14/18] arm64: dts: imx8mm: add GPC node
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:46     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Add the DT node for the GPC, including all the PGC power domains,
some of them are not fully functional yet, as they require interaction
with the blk-ctrls to properly power up/down the peripherals.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 107 ++++++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a27e02bee6b4..1cdb475b5895 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -7,6 +7,8 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/imx8mm-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/thermal/thermal.h>
 
 #include "imx8mm-pinfunc.h"
@@ -600,6 +602,111 @@ src: reset-controller@30390000 {
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
+
+			gpc: gpc@303a0000 {
+				compatible = "fsl,imx8mm-gpc";
+				reg = <0x303a0000 0x10000>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&gic>;
+				interrupt-controller;
+				#interrupt-cells = <3>;
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pgc_hsiomix: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
+						clocks = <&clk IMX8MM_CLK_USB_BUS>;
+						assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
+					};
+
+					pgc_pcie: power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_PCIE>;
+						power-domains = <&pgc_hsiomix>;
+						clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
+					};
+
+					pgc_otg1: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_OTG1>;
+						power-domains = <&pgc_hsiomix>;
+					};
+
+					pgc_otg2: power-domain@3 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_OTG2>;
+						power-domains = <&pgc_hsiomix>;
+					};
+
+					pgc_gpumix: power-domain@4 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
+						clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+							 <&clk IMX8MM_CLK_GPU_AHB>;
+						assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
+								  <&clk IMX8MM_CLK_GPU_AHB>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
+									 <&clk IMX8MM_SYS_PLL1_800M>;
+						assigned-clock-rates = <800000000>, <400000000>;
+					};
+
+					pgc_gpu: power-domain@5 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_GPU>;
+						clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+							 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+							 <&clk IMX8MM_CLK_GPU2D_ROOT>,
+							 <&clk IMX8MM_CLK_GPU3D_ROOT>;
+						resets = <&src IMX8MQ_RESET_GPU_RESET>;
+						power-domains = <&pgc_gpumix>;
+					};
+
+					pgc_vpumix: power-domain@6 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
+						clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
+						assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
+						resets = <&src IMX8MQ_RESET_VPU_RESET>;
+					};
+
+					pgc_vpu_g1: power-domain@7 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
+					};
+
+					pgc_vpu_g2: power-domain@8 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
+					};
+
+					pgc_vpu_h1: power-domain@9 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
+					};
+
+					pgc_dispmix: power-domain@10 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
+						clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+							 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
+						assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
+								  <&clk IMX8MM_CLK_DISP_APB>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
+									 <&clk IMX8MM_SYS_PLL1_800M>;
+						assigned-clock-rates = <500000000>, <200000000>;
+					};
+
+					pgc_mipi: power-domain@11 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_MIPI>;
+					};
+				};
+			};
 		};
 
 		aips2: bus@30400000 {
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 14/18] arm64: dts: imx8mm: add GPC node
@ 2021-07-21 20:46     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:46 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Add the DT node for the GPC, including all the PGC power domains,
some of them are not fully functional yet, as they require interaction
with the blk-ctrls to properly power up/down the peripherals.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 107 ++++++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a27e02bee6b4..1cdb475b5895 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -7,6 +7,8 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/imx8mm-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/thermal/thermal.h>
 
 #include "imx8mm-pinfunc.h"
@@ -600,6 +602,111 @@ src: reset-controller@30390000 {
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
+
+			gpc: gpc@303a0000 {
+				compatible = "fsl,imx8mm-gpc";
+				reg = <0x303a0000 0x10000>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&gic>;
+				interrupt-controller;
+				#interrupt-cells = <3>;
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pgc_hsiomix: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
+						clocks = <&clk IMX8MM_CLK_USB_BUS>;
+						assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
+					};
+
+					pgc_pcie: power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_PCIE>;
+						power-domains = <&pgc_hsiomix>;
+						clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
+					};
+
+					pgc_otg1: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_OTG1>;
+						power-domains = <&pgc_hsiomix>;
+					};
+
+					pgc_otg2: power-domain@3 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_OTG2>;
+						power-domains = <&pgc_hsiomix>;
+					};
+
+					pgc_gpumix: power-domain@4 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
+						clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+							 <&clk IMX8MM_CLK_GPU_AHB>;
+						assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
+								  <&clk IMX8MM_CLK_GPU_AHB>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
+									 <&clk IMX8MM_SYS_PLL1_800M>;
+						assigned-clock-rates = <800000000>, <400000000>;
+					};
+
+					pgc_gpu: power-domain@5 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_GPU>;
+						clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+							 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+							 <&clk IMX8MM_CLK_GPU2D_ROOT>,
+							 <&clk IMX8MM_CLK_GPU3D_ROOT>;
+						resets = <&src IMX8MQ_RESET_GPU_RESET>;
+						power-domains = <&pgc_gpumix>;
+					};
+
+					pgc_vpumix: power-domain@6 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
+						clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
+						assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
+						resets = <&src IMX8MQ_RESET_VPU_RESET>;
+					};
+
+					pgc_vpu_g1: power-domain@7 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
+					};
+
+					pgc_vpu_g2: power-domain@8 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
+					};
+
+					pgc_vpu_h1: power-domain@9 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
+					};
+
+					pgc_dispmix: power-domain@10 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
+						clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+							 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
+						assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
+								  <&clk IMX8MM_CLK_DISP_APB>;
+						assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
+									 <&clk IMX8MM_SYS_PLL1_800M>;
+						assigned-clock-rates = <500000000>, <200000000>;
+					};
+
+					pgc_mipi: power-domain@11 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MM_POWER_DOMAIN_MIPI>;
+					};
+				};
+			};
 		};
 
 		aips2: bus@30400000 {
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 15/18] arm64: dts: imx8mm: put USB controllers into power-domains
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:47     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:47 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Now that we have support for the power domain controller on the i.MX8MM
we can put the USB controllers in their respective power domains to allow
them to power down the PHY when possible.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 1cdb475b5895..39d651612d0e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1060,6 +1060,7 @@ usbotg1: usb@32e40000 {
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				fsl,usbphy = <&usbphynop1>;
 				fsl,usbmisc = <&usbmisc1 0>;
+				power-domains = <&pgc_otg1>;
 				status = "disabled";
 			};
 
@@ -1079,6 +1080,7 @@ usbotg2: usb@32e50000 {
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				fsl,usbphy = <&usbphynop2>;
 				fsl,usbmisc = <&usbmisc2 0>;
+				power-domains = <&pgc_otg2>;
 				status = "disabled";
 			};
 
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 15/18] arm64: dts: imx8mm: put USB controllers into power-domains
@ 2021-07-21 20:47     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:47 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Now that we have support for the power domain controller on the i.MX8MM
we can put the USB controllers in their respective power domains to allow
them to power down the PHY when possible.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 1cdb475b5895..39d651612d0e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1060,6 +1060,7 @@ usbotg1: usb@32e40000 {
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				fsl,usbphy = <&usbphynop1>;
 				fsl,usbmisc = <&usbmisc1 0>;
+				power-domains = <&pgc_otg1>;
 				status = "disabled";
 			};
 
@@ -1079,6 +1080,7 @@ usbotg2: usb@32e50000 {
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				fsl,usbphy = <&usbphynop2>;
 				fsl,usbmisc = <&usbmisc2 0>;
+				power-domains = <&pgc_otg2>;
 				status = "disabled";
 			};
 
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 16/18] arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:47     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:47 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

From: Frieder Schrempf <frieder.schrempf@kontron.de>

According to the documents, the i.MX8M-Mini features a GC320 and a
GCNanoUltra GPU core. Etnaviv detects them as:

	etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653
	etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341

This seems to work fine more or less without any changes to the HWDB,
which still might be needed in the future to correct some features,
etc.

[lst]: Added power domains and switched clock assignments to the
       new clock defines used for the composite clocks, instead of
       relying on the backwards compat defines.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 31 +++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 39d651612d0e..a937018556a1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1121,6 +1121,37 @@ gpmi: nand-controller@33002000{
 			status = "disabled";
 		};
 
+		gpu_3d: gpu@38000000 {
+			compatible = "vivante,gc";
+			reg = <0x38000000 0x8000>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+				 <&clk IMX8MM_CLK_GPU3D_ROOT>,
+				 <&clk IMX8MM_CLK_GPU3D_ROOT>;
+			clock-names = "reg", "bus", "core", "shader";
+			assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
+					  <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-rates = <0>, <1000000000>;
+			power-domains = <&pgc_gpu>;
+		};
+
+		gpu_2d: gpu@38008000 {
+			compatible = "vivante,gc";
+			reg = <0x38008000 0x8000>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+				 <&clk IMX8MM_CLK_GPU2D_ROOT>;
+			clock-names = "reg", "bus", "core";
+			assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
+					  <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-rates = <0>, <1000000000>;
+			power-domains = <&pgc_gpu>;
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>, /* GIC Dist */
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 16/18] arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core
@ 2021-07-21 20:47     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:47 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

From: Frieder Schrempf <frieder.schrempf@kontron.de>

According to the documents, the i.MX8M-Mini features a GC320 and a
GCNanoUltra GPU core. Etnaviv detects them as:

	etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653
	etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341

This seems to work fine more or less without any changes to the HWDB,
which still might be needed in the future to correct some features,
etc.

[lst]: Added power domains and switched clock assignments to the
       new clock defines used for the composite clocks, instead of
       relying on the backwards compat defines.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 31 +++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 39d651612d0e..a937018556a1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1121,6 +1121,37 @@ gpmi: nand-controller@33002000{
 			status = "disabled";
 		};
 
+		gpu_3d: gpu@38000000 {
+			compatible = "vivante,gc";
+			reg = <0x38000000 0x8000>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+				 <&clk IMX8MM_CLK_GPU3D_ROOT>,
+				 <&clk IMX8MM_CLK_GPU3D_ROOT>;
+			clock-names = "reg", "bus", "core", "shader";
+			assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
+					  <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-rates = <0>, <1000000000>;
+			power-domains = <&pgc_gpu>;
+		};
+
+		gpu_2d: gpu@38008000 {
+			compatible = "vivante,gc";
+			reg = <0x38008000 0x8000>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+				 <&clk IMX8MM_CLK_GPU2D_ROOT>;
+			clock-names = "reg", "bus", "core";
+			assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
+					  <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
+			assigned-clock-rates = <0>, <1000000000>;
+			power-domains = <&pgc_gpu>;
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>, /* GIC Dist */
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 17/18] arm64: dts: imx8mm: add VPU blk-ctrl
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:47     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:47 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Add the DT node for the VPU blk-ctrl. With this in place the
VPU power domains are fully functional.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a937018556a1..fdca74ece767 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1152,6 +1152,19 @@ gpu_2d: gpu@38008000 {
 			power-domains = <&pgc_gpu>;
 		};
 
+		vpu_blk_ctrl: blk-ctrl@38330000 {
+			compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
+			reg = <0x38330000 0x100>;
+			power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
+					<&pgc_vpu_g2>, <&pgc_vpu_h1>;
+			power-domain-names = "bus", "g1", "g2", "h1";
+			clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
+				 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
+				 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
+			clock-names = "g1", "g2", "h1";
+			#power-domain-cells = <1>;
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>, /* GIC Dist */
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 17/18] arm64: dts: imx8mm: add VPU blk-ctrl
@ 2021-07-21 20:47     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:47 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Add the DT node for the VPU blk-ctrl. With this in place the
VPU power domains are fully functional.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a937018556a1..fdca74ece767 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1152,6 +1152,19 @@ gpu_2d: gpu@38008000 {
 			power-domains = <&pgc_gpu>;
 		};
 
+		vpu_blk_ctrl: blk-ctrl@38330000 {
+			compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
+			reg = <0x38330000 0x100>;
+			power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
+					<&pgc_vpu_g2>, <&pgc_vpu_h1>;
+			power-domain-names = "bus", "g1", "g2", "h1";
+			clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
+				 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
+				 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
+			clock-names = "g1", "g2", "h1";
+			#power-domain-cells = <1>;
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>, /* GIC Dist */
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 18/18] arm64: dts: imx8mm: add DISP blk-ctrl
  2021-07-21 20:46   ` Lucas Stach
@ 2021-07-21 20:47     ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:47 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Add the DT node for the DISP blk-ctrl. With this in place the
display/mipi power domains are fully functional.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 27 +++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index fdca74ece767..72688c578b3f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1050,6 +1050,33 @@ aips4: bus@32c00000 {
 			#size-cells = <1>;
 			ranges = <0x32c00000 0x32c00000 0x400000>;
 
+			disp_blk_ctrl: blk-ctrl@32e28000 {
+				compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
+				reg = <0x32e28000 0x100>;
+				power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
+						<&pgc_dispmix>, <&pgc_mipi>,
+						<&pgc_mipi>;
+				power-domain-names = "bus", "csi-bridge",
+						     "lcdif", "mipi-dsi",
+						     "mipi-csi";
+				clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MM_CLK_CSI1_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_ROOT>,
+					 <&clk IMX8MM_CLK_DSI_CORE>,
+					 <&clk IMX8MM_CLK_DSI_PHY_REF>,
+					 <&clk IMX8MM_CLK_CSI1_CORE>,
+					 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
+				clock-names = "csi-bridge-axi","csi-bridge-apb",
+					      "csi-bridge-core", "lcdif-axi",
+					      "lcdif-apb", "lcdif-pix",
+					      "dsi-pclk", "dsi-ref",
+					      "csi-aclk", "csi-pclk";
+				#power-domain-cells = <1>;
+			};
+
 			usbotg1: usb@32e40000 {
 				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
 				reg = <0x32e40000 0x200>;
-- 
2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* [PATCH v2 18/18] arm64: dts: imx8mm: add DISP blk-ctrl
@ 2021-07-21 20:47     ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-07-21 20:47 UTC (permalink / raw)
  To: Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Frieder Schrempf, Peng Fan,
	Marek Vasut, devicetree, linux-arm-kernel, kernel, patchwork-lst

Add the DT node for the DISP blk-ctrl. With this in place the
display/mipi power domains are fully functional.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 27 +++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index fdca74ece767..72688c578b3f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1050,6 +1050,33 @@ aips4: bus@32c00000 {
 			#size-cells = <1>;
 			ranges = <0x32c00000 0x32c00000 0x400000>;
 
+			disp_blk_ctrl: blk-ctrl@32e28000 {
+				compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
+				reg = <0x32e28000 0x100>;
+				power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
+						<&pgc_dispmix>, <&pgc_mipi>,
+						<&pgc_mipi>;
+				power-domain-names = "bus", "csi-bridge",
+						     "lcdif", "mipi-dsi",
+						     "mipi-csi";
+				clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MM_CLK_CSI1_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_ROOT>,
+					 <&clk IMX8MM_CLK_DSI_CORE>,
+					 <&clk IMX8MM_CLK_DSI_PHY_REF>,
+					 <&clk IMX8MM_CLK_CSI1_CORE>,
+					 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
+				clock-names = "csi-bridge-axi","csi-bridge-apb",
+					      "csi-bridge-core", "lcdif-axi",
+					      "lcdif-apb", "lcdif-pix",
+					      "dsi-pclk", "dsi-ref",
+					      "csi-aclk", "csi-pclk";
+				#power-domain-cells = <1>;
+			};
+
 			usbotg1: usb@32e40000 {
 				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
 				reg = <0x32e40000 0x200>;
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 08/18] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
  2021-07-21 20:46     ` Lucas Stach
@ 2021-07-22 14:37       ` Rob Herring
  -1 siblings, 0 replies; 136+ messages in thread
From: Rob Herring @ 2021-07-22 14:37 UTC (permalink / raw)
  To: Lucas Stach
  Cc: devicetree, Marek Vasut, kernel, Shawn Guo, patchwork-lst,
	linux-arm-kernel, Frieder Schrempf, Rob Herring, Peng Fan,
	NXP Linux Team, Adam Ford

On Wed, 21 Jul 2021 22:46:53 +0200, Lucas Stach wrote:
> This adds the DT binding for the i.MX8MM VPU blk-ctrl.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      | 76 +++++++++++++++++++
>  1 file changed, 76 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.example.dt.yaml: blk-ctrl@38330000: '#power-domain-cells' does not match any of the regexes: 'pinctrl-[0-9]+'
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1508454

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 11/18] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
  2021-07-21 20:46     ` Lucas Stach
@ 2021-07-22 14:37       ` Rob Herring
  -1 siblings, 0 replies; 136+ messages in thread
From: Rob Herring @ 2021-07-22 14:37 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Adam Ford, Rob Herring, linux-arm-kernel, Peng Fan, Shawn Guo,
	Marek Vasut, NXP Linux Team, devicetree, Frieder Schrempf,
	patchwork-lst, kernel

On Wed, 21 Jul 2021 22:46:56 +0200, Lucas Stach wrote:
> This adds the DT binding for the i.MX8MM VPU blk-ctrl.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     | 94 +++++++++++++++++++
>  1 file changed, 94 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.example.dt.yaml: blk_ctrl@32e28000: '#power-domain-cells' does not match any of the regexes: 'pinctrl-[0-9]+'
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1508456

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 08/18] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
@ 2021-07-22 14:37       ` Rob Herring
  0 siblings, 0 replies; 136+ messages in thread
From: Rob Herring @ 2021-07-22 14:37 UTC (permalink / raw)
  To: Lucas Stach
  Cc: devicetree, Marek Vasut, kernel, Shawn Guo, patchwork-lst,
	linux-arm-kernel, Frieder Schrempf, Rob Herring, Peng Fan,
	NXP Linux Team, Adam Ford

On Wed, 21 Jul 2021 22:46:53 +0200, Lucas Stach wrote:
> This adds the DT binding for the i.MX8MM VPU blk-ctrl.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      | 76 +++++++++++++++++++
>  1 file changed, 76 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.example.dt.yaml: blk-ctrl@38330000: '#power-domain-cells' does not match any of the regexes: 'pinctrl-[0-9]+'
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1508454

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 11/18] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
@ 2021-07-22 14:37       ` Rob Herring
  0 siblings, 0 replies; 136+ messages in thread
From: Rob Herring @ 2021-07-22 14:37 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Adam Ford, Rob Herring, linux-arm-kernel, Peng Fan, Shawn Guo,
	Marek Vasut, NXP Linux Team, devicetree, Frieder Schrempf,
	patchwork-lst, kernel

On Wed, 21 Jul 2021 22:46:56 +0200, Lucas Stach wrote:
> This adds the DT binding for the i.MX8MM VPU blk-ctrl.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     | 94 +++++++++++++++++++
>  1 file changed, 94 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.example.dt.yaml: blk_ctrl@32e28000: '#power-domain-cells' does not match any of the regexes: 'pinctrl-[0-9]+'
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1508456

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-07-21 20:46   ` Lucas Stach
@ 2021-08-05  9:35     ` Peng Fan (OSS)
  -1 siblings, 0 replies; 136+ messages in thread
From: Peng Fan (OSS) @ 2021-08-05  9:35 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
> 
> Hi all,
> 
> second revision of the GPC improvements and BLK_CTRL driver to make use
> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
> blurb from the v1 cover letter here, but if you are not familiar with i.MX8MM
> power domains, it may be worth a read.
> 
> This 2nd revision fixes the DT bindings to be valid yaml, some small failure
> path issues and most importantly the interaction with system
> suspend/resume. With the previous version some of the power domains
> would not come up correctly after a suspend/resume cycle.

Thanks for the work. I gave a test, boot and suspend/resume work with display.

Tested-by: Peng Fan <peng.fan@nxp.com>

> 
> Updated testing git trees here, disclaimer still applies:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pen
> gutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domai
> ns&amp;data=04%7C01%7Cpeng.fan%40nxp.com%7C3ef1698b8c53454da41
> 808d94c88b577%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63
> 7624972323848567%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD
> AiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata
> =PbhVVIqDcUMtMmurwpp2PoSYaAzXgRKVvBccd%2BL26oc%3D&amp;reserv
> ed=0
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pen
> gutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domai
> ns-testing&amp;data=04%7C01%7Cpeng.fan%40nxp.com%7C3ef1698b8c534
> 54da41808d94c88b577%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> 0%7C637624972323848567%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w
> LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a
> mp;sdata=rAuBbsQ5%2FpZJhuocWmapgNwERxat0IQsRfBiQpeJzuk%3D&amp;
> reserved=0
> 
> Regards,
> Lucas
> 
> Frieder Schrempf (1):
>   arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core
> 
> Lucas Stach (15):
>   Revert "soc: imx: gpcv2: move reset assert after requesting domain
>     power up"
>   soc: imx: gpcv2: add lockdep annotation
>   soc: imx: gpcv2: add domain option to keep domain clocks enabled
>   soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
>   soc: imx: gpcv2: support system suspend/resume
>   dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
>   dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains
>   soc: imx: add i.MX8M blk-ctrl driver
>   dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
>   dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains
>   soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
>   arm64: dts: imx8mm: add GPC node
>   arm64: dts: imx8mm: put USB controllers into power-domains
>   arm64: dts: imx8mm: add VPU blk-ctrl
>   arm64: dts: imx8mm: add DISP blk-ctrl
> 
> Marek Vasut (2):
>   soc: imx: gpcv2: Turn domain->pgc into bitfield
>   soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM
> GPU
>     domain
> 
>  .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     |  94 ++++
>  .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      |  76 +++
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 180 ++++++
>  drivers/soc/imx/Makefile                      |   1 +
>  drivers/soc/imx/gpcv2.c                       | 130 +++--
>  drivers/soc/imx/imx8m-blk-ctrl.c              | 525
> ++++++++++++++++++
>  include/dt-bindings/power/imx8mm-power.h      |   9 +
>  7 files changed, 974 insertions(+), 41 deletions(-)  create mode 100644
> Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
>  create mode 100644
> Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
>  create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c
> 
> --
> 2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-08-05  9:35     ` Peng Fan (OSS)
  0 siblings, 0 replies; 136+ messages in thread
From: Peng Fan (OSS) @ 2021-08-05  9:35 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
> 
> Hi all,
> 
> second revision of the GPC improvements and BLK_CTRL driver to make use
> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
> blurb from the v1 cover letter here, but if you are not familiar with i.MX8MM
> power domains, it may be worth a read.
> 
> This 2nd revision fixes the DT bindings to be valid yaml, some small failure
> path issues and most importantly the interaction with system
> suspend/resume. With the previous version some of the power domains
> would not come up correctly after a suspend/resume cycle.

Thanks for the work. I gave a test, boot and suspend/resume work with display.

Tested-by: Peng Fan <peng.fan@nxp.com>

> 
> Updated testing git trees here, disclaimer still applies:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pen
> gutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domai
> ns&amp;data=04%7C01%7Cpeng.fan%40nxp.com%7C3ef1698b8c53454da41
> 808d94c88b577%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63
> 7624972323848567%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD
> AiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata
> =PbhVVIqDcUMtMmurwpp2PoSYaAzXgRKVvBccd%2BL26oc%3D&amp;reserv
> ed=0
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pen
> gutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domai
> ns-testing&amp;data=04%7C01%7Cpeng.fan%40nxp.com%7C3ef1698b8c534
> 54da41808d94c88b577%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> 0%7C637624972323848567%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w
> LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a
> mp;sdata=rAuBbsQ5%2FpZJhuocWmapgNwERxat0IQsRfBiQpeJzuk%3D&amp;
> reserved=0
> 
> Regards,
> Lucas
> 
> Frieder Schrempf (1):
>   arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core
> 
> Lucas Stach (15):
>   Revert "soc: imx: gpcv2: move reset assert after requesting domain
>     power up"
>   soc: imx: gpcv2: add lockdep annotation
>   soc: imx: gpcv2: add domain option to keep domain clocks enabled
>   soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
>   soc: imx: gpcv2: support system suspend/resume
>   dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl
>   dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains
>   soc: imx: add i.MX8M blk-ctrl driver
>   dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl
>   dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains
>   soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
>   arm64: dts: imx8mm: add GPC node
>   arm64: dts: imx8mm: put USB controllers into power-domains
>   arm64: dts: imx8mm: add VPU blk-ctrl
>   arm64: dts: imx8mm: add DISP blk-ctrl
> 
> Marek Vasut (2):
>   soc: imx: gpcv2: Turn domain->pgc into bitfield
>   soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM
> GPU
>     domain
> 
>  .../soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml     |  94 ++++
>  .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      |  76 +++
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 180 ++++++
>  drivers/soc/imx/Makefile                      |   1 +
>  drivers/soc/imx/gpcv2.c                       | 130 +++--
>  drivers/soc/imx/imx8m-blk-ctrl.c              | 525
> ++++++++++++++++++
>  include/dt-bindings/power/imx8mm-power.h      |   9 +
>  7 files changed, 974 insertions(+), 41 deletions(-)  create mode 100644
> Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
>  create mode 100644
> Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
>  create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c
> 
> --
> 2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 01/18] Revert "soc: imx: gpcv2: move reset assert after requesting domain power up"
  2021-07-21 20:46     ` Lucas Stach
@ 2021-08-05  9:37       ` Peng Fan
  -1 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:37 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 01/18] Revert "soc: imx: gpcv2: move reset assert after
> requesting domain power up"
> 
> This reverts commit a77ebdd9f553. It turns out that the VPU domain has no
> different requirements, even though the downstream ATF implementation
> seems to suggest otherwise. Powering on the domain with the reset asserted
> works fine. As the changed sequence has caused sporadic issues with the GPU
> domains, just revert the change to go back to the working sequence.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Acked-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> 34a9ac1f2b9b..8b7a01773aec 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -244,6 +244,8 @@ static int imx_pgc_power_up(struct
> generic_pm_domain *genpd)
>  		goto out_regulator_disable;
>  	}
> 
> +	reset_control_assert(domain->reset);
> +
>  	if (domain->bits.pxx) {
>  		/* request the domain to power up */
>  		regmap_update_bits(domain->regmap,
> GPC_PU_PGC_SW_PUP_REQ, @@ -266,8 +268,6 @@ static int
> imx_pgc_power_up(struct generic_pm_domain *genpd)
>  				  GPC_PGC_CTRL_PCR);
>  	}
> 
> -	reset_control_assert(domain->reset);
> -
>  	/* delay for reset to propagate */
>  	udelay(5);
> 
> --
> 2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 01/18] Revert "soc: imx: gpcv2: move reset assert after requesting domain power up"
@ 2021-08-05  9:37       ` Peng Fan
  0 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:37 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 01/18] Revert "soc: imx: gpcv2: move reset assert after
> requesting domain power up"
> 
> This reverts commit a77ebdd9f553. It turns out that the VPU domain has no
> different requirements, even though the downstream ATF implementation
> seems to suggest otherwise. Powering on the domain with the reset asserted
> works fine. As the changed sequence has caused sporadic issues with the GPU
> domains, just revert the change to go back to the working sequence.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Acked-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> 34a9ac1f2b9b..8b7a01773aec 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -244,6 +244,8 @@ static int imx_pgc_power_up(struct
> generic_pm_domain *genpd)
>  		goto out_regulator_disable;
>  	}
> 
> +	reset_control_assert(domain->reset);
> +
>  	if (domain->bits.pxx) {
>  		/* request the domain to power up */
>  		regmap_update_bits(domain->regmap,
> GPC_PU_PGC_SW_PUP_REQ, @@ -266,8 +268,6 @@ static int
> imx_pgc_power_up(struct generic_pm_domain *genpd)
>  				  GPC_PGC_CTRL_PCR);
>  	}
> 
> -	reset_control_assert(domain->reset);
> -
>  	/* delay for reset to propagate */
>  	udelay(5);
> 
> --
> 2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 02/18] soc: imx: gpcv2: Turn domain->pgc into bitfield
  2021-07-21 20:46     ` Lucas Stach
@ 2021-08-05  9:37       ` Peng Fan
  -1 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:37 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 02/18] soc: imx: gpcv2: Turn domain->pgc into bitfield
> 
> From: Marek Vasut <marex@denx.de>
> 
> There is currently the MX8MM GPU domain, which is in fact a composite
> domain for both GPU2D and GPU3D. To correctly configure this domain, it is
> necessary to control both GPC_PGC_nCTRL(GPU_2D) and
> GPC_PGC_nCTRL(GPU_3D) at the same time. This is currently not possible.
> 
> Turn the domain->pgc from value into bitfield and use for_each_set_bit() to
> iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL
> register array. This way it is possible to configure all GPC_PGC_nCTRL registers
> required in a particular domain.
> 
> This is a preparatory patch, no functional change.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
> v2 (Lucas Stach):
> - rebase on top of reverted reset sequence change
> - also convert i.MX8MN domains
> ---
>  drivers/soc/imx/gpcv2.c | 72 ++++++++++++++++++++++-------------------
>  1 file changed, 38 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> 8b7a01773aec..c7826ce92f0d 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -192,7 +192,7 @@ struct imx_pgc_domain {
>  	struct clk_bulk_data *clks;
>  	int num_clks;
> 
> -	unsigned int pgc;
> +	unsigned long pgc;
> 
>  	const struct {
>  		u32 pxx;
> @@ -220,7 +220,7 @@ to_imx_pgc_domain(struct generic_pm_domain
> *genpd)  static int imx_pgc_power_up(struct generic_pm_domain *genpd)
> {
>  	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
> -	u32 reg_val;
> +	u32 reg_val, pgc;
>  	int ret;
> 
>  	ret = pm_runtime_get_sync(domain->dev); @@ -264,8 +264,10 @@
> static int imx_pgc_power_up(struct generic_pm_domain *genpd)
>  		}
> 
>  		/* disable power control */
> -		regmap_clear_bits(domain->regmap,
> GPC_PGC_CTRL(domain->pgc),
> -				  GPC_PGC_CTRL_PCR);
> +		for_each_set_bit(pgc, &domain->pgc, 32) {
> +			regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
> +					  GPC_PGC_CTRL_PCR);
> +		}
>  	}
> 
>  	/* delay for reset to propagate */
> @@ -311,7 +313,7 @@ static int imx_pgc_power_up(struct
> generic_pm_domain *genpd)  static int imx_pgc_power_down(struct
> generic_pm_domain *genpd)  {
>  	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
> -	u32 reg_val;
> +	u32 reg_val, pgc;
>  	int ret;
> 
>  	/* Enable reset clocks for all devices in the domain */ @@ -338,8
> +340,10 @@ static int imx_pgc_power_down(struct generic_pm_domain
> *genpd)
> 
>  	if (domain->bits.pxx) {
>  		/* enable power control */
> -		regmap_update_bits(domain->regmap,
> GPC_PGC_CTRL(domain->pgc),
> -				   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
> +		for_each_set_bit(pgc, &domain->pgc, 32) {
> +			regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
> +					   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
> +		}
> 
>  		/* request the domain to power down */
>  		regmap_update_bits(domain->regmap,
> GPC_PU_PGC_SW_PDN_REQ, @@ -389,7 +393,7 @@ static const struct
> imx_pgc_domain imx7_pgc_domains[] = {
>  			.map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
>  		},
>  		.voltage   = 1000000,
> -		.pgc	   = IMX7_PGC_MIPI,
> +		.pgc	   = BIT(IMX7_PGC_MIPI),
>  	},
> 
>  	[IMX7_POWER_DOMAIN_PCIE_PHY] = {
> @@ -401,7 +405,7 @@ static const struct imx_pgc_domain
> imx7_pgc_domains[] = {
>  			.map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
>  		},
>  		.voltage   = 1000000,
> -		.pgc	   = IMX7_PGC_PCIE,
> +		.pgc	   = BIT(IMX7_PGC_PCIE),
>  	},
> 
>  	[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
> @@ -413,7 +417,7 @@ static const struct imx_pgc_domain
> imx7_pgc_domains[] = {
>  			.map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
>  		},
>  		.voltage   = 1200000,
> -		.pgc	   = IMX7_PGC_USB_HSIC,
> +		.pgc	   = BIT(IMX7_PGC_USB_HSIC),
>  	},
>  };
> 
> @@ -448,7 +452,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_MIPI_SW_Pxx_REQ,
>  			.map = IMX8M_MIPI_A53_DOMAIN,
>  		},
> -		.pgc	   = IMX8M_PGC_MIPI,
> +		.pgc	   = BIT(IMX8M_PGC_MIPI),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_PCIE1] = {
> @@ -459,7 +463,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_PCIE1_SW_Pxx_REQ,
>  			.map = IMX8M_PCIE1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_PCIE1,
> +		.pgc   = BIT(IMX8M_PGC_PCIE1),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_USB_OTG1] = {
> @@ -470,7 +474,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_OTG1_SW_Pxx_REQ,
>  			.map = IMX8M_OTG1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_OTG1,
> +		.pgc   = BIT(IMX8M_PGC_OTG1),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_USB_OTG2] = {
> @@ -481,7 +485,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_OTG2_SW_Pxx_REQ,
>  			.map = IMX8M_OTG2_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_OTG2,
> +		.pgc   = BIT(IMX8M_PGC_OTG2),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_DDR1] = {
> @@ -492,7 +496,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_DDR1_SW_Pxx_REQ,
>  			.map = IMX8M_DDR2_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_DDR1,
> +		.pgc   = BIT(IMX8M_PGC_DDR1),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_GPU] = {
> @@ -505,7 +509,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.hskreq = IMX8M_GPU_HSK_PWRDNREQN,
>  			.hskack = IMX8M_GPU_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8M_PGC_GPU,
> +		.pgc   = BIT(IMX8M_PGC_GPU),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_VPU] = {
> @@ -518,7 +522,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.hskreq = IMX8M_VPU_HSK_PWRDNREQN,
>  			.hskack = IMX8M_VPU_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8M_PGC_VPU,
> +		.pgc   = BIT(IMX8M_PGC_VPU),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_DISP] = {
> @@ -531,7 +535,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.hskreq = IMX8M_DISP_HSK_PWRDNREQN,
>  			.hskack = IMX8M_DISP_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8M_PGC_DISP,
> +		.pgc   = BIT(IMX8M_PGC_DISP),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
> @@ -542,7 +546,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
>  			.map = IMX8M_MIPI_CSI1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_MIPI_CSI1,
> +		.pgc   = BIT(IMX8M_PGC_MIPI_CSI1),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
> @@ -553,7 +557,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
>  			.map = IMX8M_MIPI_CSI2_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_MIPI_CSI2,
> +		.pgc   = BIT(IMX8M_PGC_MIPI_CSI2),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_PCIE2] = {
> @@ -564,7 +568,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_PCIE2_SW_Pxx_REQ,
>  			.map = IMX8M_PCIE2_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_PCIE2,
> +		.pgc   = BIT(IMX8M_PGC_PCIE2),
>  	},
>  };
> 
> @@ -627,7 +631,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_PCIE_SW_Pxx_REQ,
>  			.map = IMX8MM_PCIE_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_PCIE,
> +		.pgc   = BIT(IMX8MM_PGC_PCIE),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_OTG1] = {
> @@ -638,7 +642,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_OTG1_SW_Pxx_REQ,
>  			.map = IMX8MM_OTG1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_OTG1,
> +		.pgc   = BIT(IMX8MM_PGC_OTG1),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_OTG2] = {
> @@ -649,7 +653,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_OTG2_SW_Pxx_REQ,
>  			.map = IMX8MM_OTG2_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_OTG2,
> +		.pgc   = BIT(IMX8MM_PGC_OTG2),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_GPUMIX] = {
> @@ -662,7 +666,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8MM_PGC_GPUMIX,
> +		.pgc   = BIT(IMX8MM_PGC_GPUMIX),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_GPU] = {
> @@ -675,7 +679,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8MM_PGC_GPU2D,
> +		.pgc   = BIT(IMX8MM_PGC_GPU2D),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
> @@ -688,7 +692,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8MM_PGC_VPUMIX,
> +		.pgc   = BIT(IMX8MM_PGC_VPUMIX),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUG1] = {
> @@ -699,7 +703,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
>  			.map = IMX8MM_VPUG1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_VPUG1,
> +		.pgc   = BIT(IMX8MM_PGC_VPUG1),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUG2] = {
> @@ -710,7 +714,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
>  			.map = IMX8MM_VPUG2_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_VPUG2,
> +		.pgc   = BIT(IMX8MM_PGC_VPUG2),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUH1] = {
> @@ -721,7 +725,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
>  			.map = IMX8MM_VPUH1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_VPUH1,
> +		.pgc   = BIT(IMX8MM_PGC_VPUH1),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_DISPMIX] = {
> @@ -734,7 +738,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8MM_PGC_DISPMIX,
> +		.pgc   = BIT(IMX8MM_PGC_DISPMIX),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_MIPI] = {
> @@ -745,7 +749,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_MIPI_SW_Pxx_REQ,
>  			.map = IMX8MM_MIPI_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_MIPI,
> +		.pgc   = BIT(IMX8MM_PGC_MIPI),
>  	},
>  };
> 
> @@ -812,7 +816,7 @@ static const struct imx_pgc_domain
> imx8mn_pgc_domains[] = {
>  			.pxx = IMX8MN_OTG1_SW_Pxx_REQ,
>  			.map = IMX8MN_OTG1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MN_PGC_OTG1,
> +		.pgc   = BIT(IMX8MN_PGC_OTG1),
>  	},
> 
>  	[IMX8MN_POWER_DOMAIN_GPUMIX] = {
> @@ -825,7 +829,7 @@ static const struct imx_pgc_domain
> imx8mn_pgc_domains[] = {
>  			.hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
>  			.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8MN_PGC_GPUMIX,
> +		.pgc   = BIT(IMX8MN_PGC_GPUMIX),
>  	},
>  };
> 
> --
> 2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 02/18] soc: imx: gpcv2: Turn domain->pgc into bitfield
@ 2021-08-05  9:37       ` Peng Fan
  0 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:37 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 02/18] soc: imx: gpcv2: Turn domain->pgc into bitfield
> 
> From: Marek Vasut <marex@denx.de>
> 
> There is currently the MX8MM GPU domain, which is in fact a composite
> domain for both GPU2D and GPU3D. To correctly configure this domain, it is
> necessary to control both GPC_PGC_nCTRL(GPU_2D) and
> GPC_PGC_nCTRL(GPU_3D) at the same time. This is currently not possible.
> 
> Turn the domain->pgc from value into bitfield and use for_each_set_bit() to
> iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL
> register array. This way it is possible to configure all GPC_PGC_nCTRL registers
> required in a particular domain.
> 
> This is a preparatory patch, no functional change.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
> v2 (Lucas Stach):
> - rebase on top of reverted reset sequence change
> - also convert i.MX8MN domains
> ---
>  drivers/soc/imx/gpcv2.c | 72 ++++++++++++++++++++++-------------------
>  1 file changed, 38 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> 8b7a01773aec..c7826ce92f0d 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -192,7 +192,7 @@ struct imx_pgc_domain {
>  	struct clk_bulk_data *clks;
>  	int num_clks;
> 
> -	unsigned int pgc;
> +	unsigned long pgc;
> 
>  	const struct {
>  		u32 pxx;
> @@ -220,7 +220,7 @@ to_imx_pgc_domain(struct generic_pm_domain
> *genpd)  static int imx_pgc_power_up(struct generic_pm_domain *genpd)
> {
>  	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
> -	u32 reg_val;
> +	u32 reg_val, pgc;
>  	int ret;
> 
>  	ret = pm_runtime_get_sync(domain->dev); @@ -264,8 +264,10 @@
> static int imx_pgc_power_up(struct generic_pm_domain *genpd)
>  		}
> 
>  		/* disable power control */
> -		regmap_clear_bits(domain->regmap,
> GPC_PGC_CTRL(domain->pgc),
> -				  GPC_PGC_CTRL_PCR);
> +		for_each_set_bit(pgc, &domain->pgc, 32) {
> +			regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
> +					  GPC_PGC_CTRL_PCR);
> +		}
>  	}
> 
>  	/* delay for reset to propagate */
> @@ -311,7 +313,7 @@ static int imx_pgc_power_up(struct
> generic_pm_domain *genpd)  static int imx_pgc_power_down(struct
> generic_pm_domain *genpd)  {
>  	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
> -	u32 reg_val;
> +	u32 reg_val, pgc;
>  	int ret;
> 
>  	/* Enable reset clocks for all devices in the domain */ @@ -338,8
> +340,10 @@ static int imx_pgc_power_down(struct generic_pm_domain
> *genpd)
> 
>  	if (domain->bits.pxx) {
>  		/* enable power control */
> -		regmap_update_bits(domain->regmap,
> GPC_PGC_CTRL(domain->pgc),
> -				   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
> +		for_each_set_bit(pgc, &domain->pgc, 32) {
> +			regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
> +					   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
> +		}
> 
>  		/* request the domain to power down */
>  		regmap_update_bits(domain->regmap,
> GPC_PU_PGC_SW_PDN_REQ, @@ -389,7 +393,7 @@ static const struct
> imx_pgc_domain imx7_pgc_domains[] = {
>  			.map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
>  		},
>  		.voltage   = 1000000,
> -		.pgc	   = IMX7_PGC_MIPI,
> +		.pgc	   = BIT(IMX7_PGC_MIPI),
>  	},
> 
>  	[IMX7_POWER_DOMAIN_PCIE_PHY] = {
> @@ -401,7 +405,7 @@ static const struct imx_pgc_domain
> imx7_pgc_domains[] = {
>  			.map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
>  		},
>  		.voltage   = 1000000,
> -		.pgc	   = IMX7_PGC_PCIE,
> +		.pgc	   = BIT(IMX7_PGC_PCIE),
>  	},
> 
>  	[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
> @@ -413,7 +417,7 @@ static const struct imx_pgc_domain
> imx7_pgc_domains[] = {
>  			.map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
>  		},
>  		.voltage   = 1200000,
> -		.pgc	   = IMX7_PGC_USB_HSIC,
> +		.pgc	   = BIT(IMX7_PGC_USB_HSIC),
>  	},
>  };
> 
> @@ -448,7 +452,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_MIPI_SW_Pxx_REQ,
>  			.map = IMX8M_MIPI_A53_DOMAIN,
>  		},
> -		.pgc	   = IMX8M_PGC_MIPI,
> +		.pgc	   = BIT(IMX8M_PGC_MIPI),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_PCIE1] = {
> @@ -459,7 +463,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_PCIE1_SW_Pxx_REQ,
>  			.map = IMX8M_PCIE1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_PCIE1,
> +		.pgc   = BIT(IMX8M_PGC_PCIE1),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_USB_OTG1] = {
> @@ -470,7 +474,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_OTG1_SW_Pxx_REQ,
>  			.map = IMX8M_OTG1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_OTG1,
> +		.pgc   = BIT(IMX8M_PGC_OTG1),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_USB_OTG2] = {
> @@ -481,7 +485,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_OTG2_SW_Pxx_REQ,
>  			.map = IMX8M_OTG2_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_OTG2,
> +		.pgc   = BIT(IMX8M_PGC_OTG2),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_DDR1] = {
> @@ -492,7 +496,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_DDR1_SW_Pxx_REQ,
>  			.map = IMX8M_DDR2_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_DDR1,
> +		.pgc   = BIT(IMX8M_PGC_DDR1),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_GPU] = {
> @@ -505,7 +509,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.hskreq = IMX8M_GPU_HSK_PWRDNREQN,
>  			.hskack = IMX8M_GPU_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8M_PGC_GPU,
> +		.pgc   = BIT(IMX8M_PGC_GPU),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_VPU] = {
> @@ -518,7 +522,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.hskreq = IMX8M_VPU_HSK_PWRDNREQN,
>  			.hskack = IMX8M_VPU_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8M_PGC_VPU,
> +		.pgc   = BIT(IMX8M_PGC_VPU),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_DISP] = {
> @@ -531,7 +535,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.hskreq = IMX8M_DISP_HSK_PWRDNREQN,
>  			.hskack = IMX8M_DISP_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8M_PGC_DISP,
> +		.pgc   = BIT(IMX8M_PGC_DISP),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
> @@ -542,7 +546,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
>  			.map = IMX8M_MIPI_CSI1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_MIPI_CSI1,
> +		.pgc   = BIT(IMX8M_PGC_MIPI_CSI1),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
> @@ -553,7 +557,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
>  			.map = IMX8M_MIPI_CSI2_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_MIPI_CSI2,
> +		.pgc   = BIT(IMX8M_PGC_MIPI_CSI2),
>  	},
> 
>  	[IMX8M_POWER_DOMAIN_PCIE2] = {
> @@ -564,7 +568,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
>  			.pxx = IMX8M_PCIE2_SW_Pxx_REQ,
>  			.map = IMX8M_PCIE2_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8M_PGC_PCIE2,
> +		.pgc   = BIT(IMX8M_PGC_PCIE2),
>  	},
>  };
> 
> @@ -627,7 +631,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_PCIE_SW_Pxx_REQ,
>  			.map = IMX8MM_PCIE_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_PCIE,
> +		.pgc   = BIT(IMX8MM_PGC_PCIE),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_OTG1] = {
> @@ -638,7 +642,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_OTG1_SW_Pxx_REQ,
>  			.map = IMX8MM_OTG1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_OTG1,
> +		.pgc   = BIT(IMX8MM_PGC_OTG1),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_OTG2] = {
> @@ -649,7 +653,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_OTG2_SW_Pxx_REQ,
>  			.map = IMX8MM_OTG2_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_OTG2,
> +		.pgc   = BIT(IMX8MM_PGC_OTG2),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_GPUMIX] = {
> @@ -662,7 +666,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8MM_PGC_GPUMIX,
> +		.pgc   = BIT(IMX8MM_PGC_GPUMIX),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_GPU] = {
> @@ -675,7 +679,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8MM_PGC_GPU2D,
> +		.pgc   = BIT(IMX8MM_PGC_GPU2D),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
> @@ -688,7 +692,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8MM_PGC_VPUMIX,
> +		.pgc   = BIT(IMX8MM_PGC_VPUMIX),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUG1] = {
> @@ -699,7 +703,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
>  			.map = IMX8MM_VPUG1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_VPUG1,
> +		.pgc   = BIT(IMX8MM_PGC_VPUG1),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUG2] = {
> @@ -710,7 +714,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
>  			.map = IMX8MM_VPUG2_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_VPUG2,
> +		.pgc   = BIT(IMX8MM_PGC_VPUG2),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUH1] = {
> @@ -721,7 +725,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
>  			.map = IMX8MM_VPUH1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_VPUH1,
> +		.pgc   = BIT(IMX8MM_PGC_VPUH1),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_DISPMIX] = {
> @@ -734,7 +738,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8MM_PGC_DISPMIX,
> +		.pgc   = BIT(IMX8MM_PGC_DISPMIX),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_MIPI] = {
> @@ -745,7 +749,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.pxx = IMX8MM_MIPI_SW_Pxx_REQ,
>  			.map = IMX8MM_MIPI_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MM_PGC_MIPI,
> +		.pgc   = BIT(IMX8MM_PGC_MIPI),
>  	},
>  };
> 
> @@ -812,7 +816,7 @@ static const struct imx_pgc_domain
> imx8mn_pgc_domains[] = {
>  			.pxx = IMX8MN_OTG1_SW_Pxx_REQ,
>  			.map = IMX8MN_OTG1_A53_DOMAIN,
>  		},
> -		.pgc   = IMX8MN_PGC_OTG1,
> +		.pgc   = BIT(IMX8MN_PGC_OTG1),
>  	},
> 
>  	[IMX8MN_POWER_DOMAIN_GPUMIX] = {
> @@ -825,7 +829,7 @@ static const struct imx_pgc_domain
> imx8mn_pgc_domains[] = {
>  			.hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
>  			.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
>  		},
> -		.pgc   = IMX8MN_PGC_GPUMIX,
> +		.pgc   = BIT(IMX8MN_PGC_GPUMIX),
>  	},
>  };
> 
> --
> 2.30.2


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 03/18] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
  2021-07-21 20:46     ` Lucas Stach
@ 2021-08-05  9:37       ` Peng Fan
  -1 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:37 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
> 
> From: Marek Vasut <marex@denx.de>
> 
> To bring up the MX8MM GPU domain, it is necessary to configure both
> GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
> this configuration, the system might hang on boot when bringing up the GPU
> power domain. This is sporadically observed on multiple disparate systems.
> 
> Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
> GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
> configured when bringing up the GPU domain. This fixes the sporadic hang.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> c7826ce92f0d..2c43e74db0be 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -679,7 +679,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
>  		},
> -		.pgc   = BIT(IMX8MM_PGC_GPU2D),
> +		.pgc   = BIT(IMX8MM_PGC_GPU2D) |
> BIT(IMX8MM_PGC_GPU3D),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
> --
> 2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 03/18] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
@ 2021-08-05  9:37       ` Peng Fan
  0 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:37 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
> 
> From: Marek Vasut <marex@denx.de>
> 
> To bring up the MX8MM GPU domain, it is necessary to configure both
> GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
> this configuration, the system might hang on boot when bringing up the GPU
> power domain. This is sporadically observed on multiple disparate systems.
> 
> Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
> GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
> configured when bringing up the GPU domain. This fixes the sporadic hang.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> c7826ce92f0d..2c43e74db0be 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -679,7 +679,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
>  		},
> -		.pgc   = BIT(IMX8MM_PGC_GPU2D),
> +		.pgc   = BIT(IMX8MM_PGC_GPU2D) |
> BIT(IMX8MM_PGC_GPU3D),
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUMIX] = {
> --
> 2.30.2


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 04/18] soc: imx: gpcv2: add lockdep annotation
  2021-07-21 20:46     ` Lucas Stach
@ 2021-08-05  9:38       ` Peng Fan
  -1 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:38 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 04/18] soc: imx: gpcv2: add lockdep annotation
> 
> Some of the GPCv2 power domains are nested inside each other without
> visibility to lockdep at the genpd level, as they are in separate driver instances
> and don't have a parent/child power-domain relationship.
> 
> Add a subclass annotation to the nested domains to let lockdep know that it is
> okay to take the genpd lock in a nested fashion.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> 2c43e74db0be..35f26f57d1ac 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -898,6 +898,10 @@ static int imx_pgc_domain_probe(struct
> platform_device *pdev)
>  		goto out_domain_unmap;
>  	}
> 
> +	if (IS_ENABLED(CONFIG_LOCKDEP) &&
> +	    of_property_read_bool(domain->dev->of_node, "power-domains"))
> +		lockdep_set_subclass(&domain->genpd.mlock, 1);
> +
>  	ret = of_genpd_add_provider_simple(domain->dev->of_node,
>  					   &domain->genpd);
>  	if (ret) {
> --
> 2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 04/18] soc: imx: gpcv2: add lockdep annotation
@ 2021-08-05  9:38       ` Peng Fan
  0 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:38 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 04/18] soc: imx: gpcv2: add lockdep annotation
> 
> Some of the GPCv2 power domains are nested inside each other without
> visibility to lockdep at the genpd level, as they are in separate driver instances
> and don't have a parent/child power-domain relationship.
> 
> Add a subclass annotation to the nested domains to let lockdep know that it is
> okay to take the genpd lock in a nested fashion.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> 2c43e74db0be..35f26f57d1ac 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -898,6 +898,10 @@ static int imx_pgc_domain_probe(struct
> platform_device *pdev)
>  		goto out_domain_unmap;
>  	}
> 
> +	if (IS_ENABLED(CONFIG_LOCKDEP) &&
> +	    of_property_read_bool(domain->dev->of_node, "power-domains"))
> +		lockdep_set_subclass(&domain->genpd.mlock, 1);
> +
>  	ret = of_genpd_add_provider_simple(domain->dev->of_node,
>  					   &domain->genpd);
>  	if (ret) {
> --
> 2.30.2


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 05/18] soc: imx: gpcv2: add domain option to keep domain clocks enabled
  2021-07-21 20:46     ` Lucas Stach
@ 2021-08-05  9:38       ` Peng Fan
  -1 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:38 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 05/18] soc: imx: gpcv2: add domain option to keep
> domain clocks enabled
> 
> Some of the MIX domains are using clocks to drive the bus bridges. Those
> must be enabled at all times, as long as the domain is powered up and they
> don't have any other consumer than the power domain. Add an option to
> keep the clocks attached to a domain enabled as long as the domain is power
> up and only disable them after the domain is powered down.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 14 +++++++++-----
>  1 file changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> 35f26f57d1ac..c3b1d2580963 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -202,6 +202,7 @@ struct imx_pgc_domain {
>  	} bits;
> 
>  	const int voltage;
> +	const bool keep_clocks;
>  	struct device *dev;
>  };
> 
> @@ -295,7 +296,8 @@ static int imx_pgc_power_up(struct
> generic_pm_domain *genpd)
>  	}
> 
>  	/* Disable reset clocks for all devices in the domain */
> -	clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
> +	if (!domain->keep_clocks)
> +		clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
> 
>  	return 0;
> 
> @@ -317,10 +319,12 @@ static int imx_pgc_power_down(struct
> generic_pm_domain *genpd)
>  	int ret;
> 
>  	/* Enable reset clocks for all devices in the domain */
> -	ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
> -	if (ret) {
> -		dev_err(domain->dev, "failed to enable reset clocks\n");
> -		return ret;
> +	if (!domain->keep_clocks) {
> +		ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
> +		if (ret) {
> +			dev_err(domain->dev, "failed to enable reset clocks\n");
> +			return ret;
> +		}
>  	}
> 
>  	/* request the ADB400 to power down */
> --
> 2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 05/18] soc: imx: gpcv2: add domain option to keep domain clocks enabled
@ 2021-08-05  9:38       ` Peng Fan
  0 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:38 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 05/18] soc: imx: gpcv2: add domain option to keep
> domain clocks enabled
> 
> Some of the MIX domains are using clocks to drive the bus bridges. Those
> must be enabled at all times, as long as the domain is powered up and they
> don't have any other consumer than the power domain. Add an option to
> keep the clocks attached to a domain enabled as long as the domain is power
> up and only disable them after the domain is powered down.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 14 +++++++++-----
>  1 file changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> 35f26f57d1ac..c3b1d2580963 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -202,6 +202,7 @@ struct imx_pgc_domain {
>  	} bits;
> 
>  	const int voltage;
> +	const bool keep_clocks;
>  	struct device *dev;
>  };
> 
> @@ -295,7 +296,8 @@ static int imx_pgc_power_up(struct
> generic_pm_domain *genpd)
>  	}
> 
>  	/* Disable reset clocks for all devices in the domain */
> -	clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
> +	if (!domain->keep_clocks)
> +		clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
> 
>  	return 0;
> 
> @@ -317,10 +319,12 @@ static int imx_pgc_power_down(struct
> generic_pm_domain *genpd)
>  	int ret;
> 
>  	/* Enable reset clocks for all devices in the domain */
> -	ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
> -	if (ret) {
> -		dev_err(domain->dev, "failed to enable reset clocks\n");
> -		return ret;
> +	if (!domain->keep_clocks) {
> +		ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
> +		if (ret) {
> +			dev_err(domain->dev, "failed to enable reset clocks\n");
> +			return ret;
> +		}
>  	}
> 
>  	/* request the ADB400 to power down */
> --
> 2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 06/18] soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
  2021-07-21 20:46     ` Lucas Stach
@ 2021-08-05  9:39       ` Peng Fan
  -1 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:39 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 06/18] soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
> 
> Annotate the domains with bus clocks to keep those clocks enabled as long as
> the domain is active.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> c3b1d2580963..c48f37f203ab 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -625,6 +625,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
>  		},
> +		.keep_clocks = true,
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_PCIE] = {
> @@ -671,6 +672,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
>  		},
>  		.pgc   = BIT(IMX8MM_PGC_GPUMIX),
> +		.keep_clocks = true,
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_GPU] = {
> @@ -697,6 +699,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
>  		},
>  		.pgc   = BIT(IMX8MM_PGC_VPUMIX),
> +		.keep_clocks = true,
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUG1] = {
> @@ -743,6 +746,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
>  		},
>  		.pgc   = BIT(IMX8MM_PGC_DISPMIX),
> +		.keep_clocks = true,
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_MIPI] = {
> @@ -810,6 +814,7 @@ static const struct imx_pgc_domain
> imx8mn_pgc_domains[] = {
>  			.hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
>  			.hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
>  		},
> +		.keep_clocks = true,
>  	},
> 
>  	[IMX8MN_POWER_DOMAIN_OTG1] = {
> --
> 2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 06/18] soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
@ 2021-08-05  9:39       ` Peng Fan
  0 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:39 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 06/18] soc: imx: gpcv2: keep i.MX8M* bus clocks enabled
> 
> Annotate the domains with bus clocks to keep those clocks enabled as long as
> the domain is active.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> c3b1d2580963..c48f37f203ab 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -625,6 +625,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
>  		},
> +		.keep_clocks = true,
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_PCIE] = {
> @@ -671,6 +672,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
>  		},
>  		.pgc   = BIT(IMX8MM_PGC_GPUMIX),
> +		.keep_clocks = true,
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_GPU] = {
> @@ -697,6 +699,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
>  		},
>  		.pgc   = BIT(IMX8MM_PGC_VPUMIX),
> +		.keep_clocks = true,
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_VPUG1] = {
> @@ -743,6 +746,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
>  		},
>  		.pgc   = BIT(IMX8MM_PGC_DISPMIX),
> +		.keep_clocks = true,
>  	},
> 
>  	[IMX8MM_POWER_DOMAIN_MIPI] = {
> @@ -810,6 +814,7 @@ static const struct imx_pgc_domain
> imx8mn_pgc_domains[] = {
>  			.hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
>  			.hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
>  		},
> +		.keep_clocks = true,
>  	},
> 
>  	[IMX8MN_POWER_DOMAIN_OTG1] = {
> --
> 2.30.2


_______________________________________________
linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 07/18] soc: imx: gpcv2: support system suspend/resume
  2021-07-21 20:46     ` Lucas Stach
@ 2021-08-05  9:47       ` Peng Fan
  -1 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:47 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 07/18] soc: imx: gpcv2: support system suspend/resume
> 
> Our usage of runtime PM to control the hierarchy of power domains is slightly
> unusual and means that powering up a domain may fail in early system
> resume, as runtime PM is still disallowed at this stage.
> 
> However the system suspend/resume path takes care of powering down/up
> the power domains in the order defined by the device parent/child and
> power-domain provider/consumer hierarachy. So we can just runtime resume
> all our power-domain devices to allow the power-up to work properly in the
> resume path. System suspend will still disable all domains as intended.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Acked-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> c48f37f203ab..57ed0a6bfb13 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -947,6 +947,36 @@ static int imx_pgc_domain_remove(struct
> platform_device *pdev)
>  	return 0;
>  }
> 
> +#ifdef CONFIG_PM_SLEEP
> +static int imx_pgc_domain_suspend(struct device *dev) {
> +	int ret;
> +
> +	/*
> +	 * This may look strange, but is done so the generic PM_SLEEP code
> +	 * can power down our domain and more importantly power it up again
> +	 * after resume, without tripping over our usage of runtime PM to
> +	 * power up/down the nested domains.
> +	 */
> +	ret = pm_runtime_get_sync(dev);
> +	if (ret < 0) {
> +		pm_runtime_put_noidle(dev);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int imx_pgc_domain_resume(struct device *dev) {
> +	return pm_runtime_put(dev);
> +}
> +#endif
> +
> +static const struct dev_pm_ops imx_pgc_domain_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(imx_pgc_domain_suspend,
> imx_pgc_domain_resume)
> +};
> +
>  static const struct platform_device_id imx_pgc_domain_id[] = {
>  	{ "imx-pgc-domain", },
>  	{ },
> @@ -955,6 +985,7 @@ static const struct platform_device_id
> imx_pgc_domain_id[] = {  static struct platform_driver
> imx_pgc_domain_driver = {
>  	.driver = {
>  		.name = "imx-pgc",
> +		.pm = &imx_pgc_domain_pm_ops,
>  	},
>  	.probe    = imx_pgc_domain_probe,
>  	.remove   = imx_pgc_domain_remove,
> --
> 2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 07/18] soc: imx: gpcv2: support system suspend/resume
@ 2021-08-05  9:47       ` Peng Fan
  0 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:47 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 07/18] soc: imx: gpcv2: support system suspend/resume
> 
> Our usage of runtime PM to control the hierarchy of power domains is slightly
> unusual and means that powering up a domain may fail in early system
> resume, as runtime PM is still disallowed at this stage.
> 
> However the system suspend/resume path takes care of powering down/up
> the power domains in the order defined by the device parent/child and
> power-domain provider/consumer hierarachy. So we can just runtime resume
> all our power-domain devices to allow the power-up to work properly in the
> resume path. System suspend will still disable all domains as intended.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Acked-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/gpcv2.c | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> c48f37f203ab..57ed0a6bfb13 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -947,6 +947,36 @@ static int imx_pgc_domain_remove(struct
> platform_device *pdev)
>  	return 0;
>  }
> 
> +#ifdef CONFIG_PM_SLEEP
> +static int imx_pgc_domain_suspend(struct device *dev) {
> +	int ret;
> +
> +	/*
> +	 * This may look strange, but is done so the generic PM_SLEEP code
> +	 * can power down our domain and more importantly power it up again
> +	 * after resume, without tripping over our usage of runtime PM to
> +	 * power up/down the nested domains.
> +	 */
> +	ret = pm_runtime_get_sync(dev);
> +	if (ret < 0) {
> +		pm_runtime_put_noidle(dev);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int imx_pgc_domain_resume(struct device *dev) {
> +	return pm_runtime_put(dev);
> +}
> +#endif
> +
> +static const struct dev_pm_ops imx_pgc_domain_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(imx_pgc_domain_suspend,
> imx_pgc_domain_resume)
> +};
> +
>  static const struct platform_device_id imx_pgc_domain_id[] = {
>  	{ "imx-pgc-domain", },
>  	{ },
> @@ -955,6 +985,7 @@ static const struct platform_device_id
> imx_pgc_domain_id[] = {  static struct platform_driver
> imx_pgc_domain_driver = {
>  	.driver = {
>  		.name = "imx-pgc",
> +		.pm = &imx_pgc_domain_pm_ops,
>  	},
>  	.probe    = imx_pgc_domain_probe,
>  	.remove   = imx_pgc_domain_remove,
> --
> 2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 13/18] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
  2021-07-21 20:46     ` Lucas Stach
@ 2021-08-05  9:53       ` Peng Fan
  -1 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:53 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 13/18] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
> 
> This adds the description for the i.MX8MM disp blk-ctrl.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/imx8m-blk-ctrl.c | 70
> ++++++++++++++++++++++++++++++++
>  1 file changed, 70 insertions(+)
> 
> diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c
> b/drivers/soc/imx/imx8m-blk-ctrl.c
> index 3dd17b903636..32eab800a3c6 100644
> --- a/drivers/soc/imx/imx8m-blk-ctrl.c
> +++ b/drivers/soc/imx/imx8m-blk-ctrl.c
> @@ -433,11 +433,81 @@ static const struct imx8m_blk_ctrl_data
> imx8m_vpu_blk_ctl_dev_data = {
>  	.num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
>  };
> 
> +static int imx8mm_disp_power_notifier(struct notifier_block *nb,
> +				      unsigned long action, void *data) {
> +	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
> +						 power_nb);
> +
> +	if (action != GENPD_NOTIFY_ON && action !=
> GENPD_NOTIFY_PRE_OFF)
> +		return NOTIFY_OK;
> +
> +	/* Enable bus clock and deassert bus reset */
> +	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12));
> +	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6));
> +
> +	/*
> +	 * On power up we have no software backchannel to the GPC to
> +	 * wait for the ADB handshake to happen, so we just delay for a
> +	 * bit. On power down the GPC driver waits for the handshake.
> +	 */
> +	if (action == GENPD_NOTIFY_ON)
> +		udelay(5);
> +
> +
> +	return NOTIFY_OK;
> +}
> +
> +static const struct imx8m_blk_ctrl_domain_data
> imx8m_disp_blk_ctl_domain_data[] = {
> +	[IMX8MM_DISPBLK_CSI_BRIDGE] = {
> +		.name = "dispblk-csi-bridge",
> +		.clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb",
> +					       "csi-bridge-core", },
> +		.num_clks = 3,
> +		.gpc_name = "csi-bridge",
> +		.rst_mask = BIT(0) | BIT(1) | BIT(2),
> +		.clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
> +	},
> +	[IMX8MM_DISPBLK_LCDIF] = {
> +		.name = "dispblk-lcdif",
> +		.clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
> +		.num_clks = 3,
> +		.gpc_name = "lcdif",
> +		.clk_mask = BIT(6) | BIT(7),
> +	},
> +	[IMX8MM_DISPBLK_MIPI_DSI] = {
> +		.name = "dispblk-mipi-dsi",
> +		.clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
> +		.num_clks = 2,
> +		.gpc_name = "mipi-dsi",
> +		.rst_mask = BIT(5),
> +		.clk_mask = BIT(8) | BIT(9),
> +	},
> +	[IMX8MM_DISPBLK_MIPI_CSI] = {
> +		.name = "dispblk-mipi-csi",
> +		.clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
> +		.num_clks = 2,
> +		.gpc_name = "mipi-csi",
> +		.rst_mask = BIT(3) | BIT(4),
> +		.clk_mask = BIT(10) | BIT(11),
> +	},
> +};
> +
> +static const struct imx8m_blk_ctrl_data imx8m_disp_blk_ctl_dev_data = {
> +	.max_reg = 0x2c,
> +	.power_notifier_fn = imx8mm_disp_power_notifier,
> +	.domains = imx8m_disp_blk_ctl_domain_data,
> +	.num_domains = ARRAY_SIZE(imx8m_disp_blk_ctl_domain_data),
> +};
> +
>  static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
>  	{
>  		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
>  		.data = &imx8m_vpu_blk_ctl_dev_data
>  	}, {
> +		.compatible = "fsl,imx8mm-disp-blk-ctrl",
> +		.data = &imx8m_disp_blk_ctl_dev_data
> +	} ,{
>  		/* Sentinel */
>  	}
>  };
> --
> 2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 13/18] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
@ 2021-08-05  9:53       ` Peng Fan
  0 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:53 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 13/18] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl
> 
> This adds the description for the i.MX8MM disp blk-ctrl.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/soc/imx/imx8m-blk-ctrl.c | 70
> ++++++++++++++++++++++++++++++++
>  1 file changed, 70 insertions(+)
> 
> diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c
> b/drivers/soc/imx/imx8m-blk-ctrl.c
> index 3dd17b903636..32eab800a3c6 100644
> --- a/drivers/soc/imx/imx8m-blk-ctrl.c
> +++ b/drivers/soc/imx/imx8m-blk-ctrl.c
> @@ -433,11 +433,81 @@ static const struct imx8m_blk_ctrl_data
> imx8m_vpu_blk_ctl_dev_data = {
>  	.num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
>  };
> 
> +static int imx8mm_disp_power_notifier(struct notifier_block *nb,
> +				      unsigned long action, void *data) {
> +	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
> +						 power_nb);
> +
> +	if (action != GENPD_NOTIFY_ON && action !=
> GENPD_NOTIFY_PRE_OFF)
> +		return NOTIFY_OK;
> +
> +	/* Enable bus clock and deassert bus reset */
> +	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12));
> +	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6));
> +
> +	/*
> +	 * On power up we have no software backchannel to the GPC to
> +	 * wait for the ADB handshake to happen, so we just delay for a
> +	 * bit. On power down the GPC driver waits for the handshake.
> +	 */
> +	if (action == GENPD_NOTIFY_ON)
> +		udelay(5);
> +
> +
> +	return NOTIFY_OK;
> +}
> +
> +static const struct imx8m_blk_ctrl_domain_data
> imx8m_disp_blk_ctl_domain_data[] = {
> +	[IMX8MM_DISPBLK_CSI_BRIDGE] = {
> +		.name = "dispblk-csi-bridge",
> +		.clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb",
> +					       "csi-bridge-core", },
> +		.num_clks = 3,
> +		.gpc_name = "csi-bridge",
> +		.rst_mask = BIT(0) | BIT(1) | BIT(2),
> +		.clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
> +	},
> +	[IMX8MM_DISPBLK_LCDIF] = {
> +		.name = "dispblk-lcdif",
> +		.clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
> +		.num_clks = 3,
> +		.gpc_name = "lcdif",
> +		.clk_mask = BIT(6) | BIT(7),
> +	},
> +	[IMX8MM_DISPBLK_MIPI_DSI] = {
> +		.name = "dispblk-mipi-dsi",
> +		.clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
> +		.num_clks = 2,
> +		.gpc_name = "mipi-dsi",
> +		.rst_mask = BIT(5),
> +		.clk_mask = BIT(8) | BIT(9),
> +	},
> +	[IMX8MM_DISPBLK_MIPI_CSI] = {
> +		.name = "dispblk-mipi-csi",
> +		.clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
> +		.num_clks = 2,
> +		.gpc_name = "mipi-csi",
> +		.rst_mask = BIT(3) | BIT(4),
> +		.clk_mask = BIT(10) | BIT(11),
> +	},
> +};
> +
> +static const struct imx8m_blk_ctrl_data imx8m_disp_blk_ctl_dev_data = {
> +	.max_reg = 0x2c,
> +	.power_notifier_fn = imx8mm_disp_power_notifier,
> +	.domains = imx8m_disp_blk_ctl_domain_data,
> +	.num_domains = ARRAY_SIZE(imx8m_disp_blk_ctl_domain_data),
> +};
> +
>  static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
>  	{
>  		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
>  		.data = &imx8m_vpu_blk_ctl_dev_data
>  	}, {
> +		.compatible = "fsl,imx8mm-disp-blk-ctrl",
> +		.data = &imx8m_disp_blk_ctl_dev_data
> +	} ,{
>  		/* Sentinel */
>  	}
>  };
> --
> 2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 14/18] arm64: dts: imx8mm: add GPC node
  2021-07-21 20:46     ` Lucas Stach
@ 2021-08-05  9:54       ` Peng Fan
  -1 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:54 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 14/18] arm64: dts: imx8mm: add GPC node
> 
> Add the DT node for the GPC, including all the PGC power domains, some of
> them are not fully functional yet, as they require interaction with the blk-ctrls
> to properly power up/down the peripherals.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 107
> ++++++++++++++++++++++
>  1 file changed, 107 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index a27e02bee6b4..1cdb475b5895 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -7,6 +7,8 @@
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/input/input.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/imx8mm-power.h>
> +#include <dt-bindings/reset/imx8mq-reset.h>
>  #include <dt-bindings/thermal/thermal.h>
> 
>  #include "imx8mm-pinfunc.h"
> @@ -600,6 +602,111 @@ src: reset-controller@30390000 {
>  				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>  				#reset-cells = <1>;
>  			};
> +
> +			gpc: gpc@303a0000 {
> +				compatible = "fsl,imx8mm-gpc";
> +				reg = <0x303a0000 0x10000>;
> +				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-parent = <&gic>;
> +				interrupt-controller;
> +				#interrupt-cells = <3>;
> +
> +				pgc {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					pgc_hsiomix: power-domain@0 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
> +						clocks = <&clk IMX8MM_CLK_USB_BUS>;
> +						assigned-clocks = <&clk
> IMX8MM_CLK_USB_BUS>;
> +						assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL2_500M>;
> +					};
> +
> +					pgc_pcie: power-domain@1 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_PCIE>;
> +						power-domains = <&pgc_hsiomix>;
> +						clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
> +					};
> +
> +					pgc_otg1: power-domain@2 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_OTG1>;
> +						power-domains = <&pgc_hsiomix>;
> +					};
> +
> +					pgc_otg2: power-domain@3 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_OTG2>;
> +						power-domains = <&pgc_hsiomix>;
> +					};
> +
> +					pgc_gpumix: power-domain@4 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
> +						clocks = <&clk
> IMX8MM_CLK_GPU_BUS_ROOT>,
> +							 <&clk IMX8MM_CLK_GPU_AHB>;
> +						assigned-clocks = <&clk
> IMX8MM_CLK_GPU_AXI>,
> +								  <&clk IMX8MM_CLK_GPU_AHB>;
> +						assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL1_800M>,
> +									 <&clk
> IMX8MM_SYS_PLL1_800M>;
> +						assigned-clock-rates = <800000000>,
> <400000000>;
> +					};
> +
> +					pgc_gpu: power-domain@5 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_GPU>;
> +						clocks = <&clk IMX8MM_CLK_GPU_AHB>,
> +							 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
> +							 <&clk IMX8MM_CLK_GPU2D_ROOT>,
> +							 <&clk IMX8MM_CLK_GPU3D_ROOT>;
> +						resets = <&src IMX8MQ_RESET_GPU_RESET>;
> +						power-domains = <&pgc_gpumix>;
> +					};
> +
> +					pgc_vpumix: power-domain@6 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
> +						clocks = <&clk
> IMX8MM_CLK_VPU_DEC_ROOT>;
> +						assigned-clocks = <&clk
> IMX8MM_CLK_VPU_BUS>;
> +						assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL1_800M>;
> +						resets = <&src IMX8MQ_RESET_VPU_RESET>;
> +					};
> +
> +					pgc_vpu_g1: power-domain@7 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
> +					};
> +
> +					pgc_vpu_g2: power-domain@8 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
> +					};
> +
> +					pgc_vpu_h1: power-domain@9 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
> +					};
> +
> +					pgc_dispmix: power-domain@10 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
> +						clocks = <&clk
> IMX8MM_CLK_DISP_APB_ROOT>,
> +							 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
> +						assigned-clocks = <&clk
> IMX8MM_CLK_DISP_AXI>,
> +								  <&clk IMX8MM_CLK_DISP_APB>;
> +						assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL2_1000M>,
> +									 <&clk
> IMX8MM_SYS_PLL1_800M>;
> +						assigned-clock-rates = <500000000>,
> <200000000>;
> +					};
> +
> +					pgc_mipi: power-domain@11 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_MIPI>;
> +					};
> +				};
> +			};
>  		};
> 
>  		aips2: bus@30400000 {
> --
> 2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 14/18] arm64: dts: imx8mm: add GPC node
@ 2021-08-05  9:54       ` Peng Fan
  0 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:54 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 14/18] arm64: dts: imx8mm: add GPC node
> 
> Add the DT node for the GPC, including all the PGC power domains, some of
> them are not fully functional yet, as they require interaction with the blk-ctrls
> to properly power up/down the peripherals.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 107
> ++++++++++++++++++++++
>  1 file changed, 107 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index a27e02bee6b4..1cdb475b5895 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -7,6 +7,8 @@
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/input/input.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/imx8mm-power.h>
> +#include <dt-bindings/reset/imx8mq-reset.h>
>  #include <dt-bindings/thermal/thermal.h>
> 
>  #include "imx8mm-pinfunc.h"
> @@ -600,6 +602,111 @@ src: reset-controller@30390000 {
>  				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>  				#reset-cells = <1>;
>  			};
> +
> +			gpc: gpc@303a0000 {
> +				compatible = "fsl,imx8mm-gpc";
> +				reg = <0x303a0000 0x10000>;
> +				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-parent = <&gic>;
> +				interrupt-controller;
> +				#interrupt-cells = <3>;
> +
> +				pgc {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					pgc_hsiomix: power-domain@0 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
> +						clocks = <&clk IMX8MM_CLK_USB_BUS>;
> +						assigned-clocks = <&clk
> IMX8MM_CLK_USB_BUS>;
> +						assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL2_500M>;
> +					};
> +
> +					pgc_pcie: power-domain@1 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_PCIE>;
> +						power-domains = <&pgc_hsiomix>;
> +						clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
> +					};
> +
> +					pgc_otg1: power-domain@2 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_OTG1>;
> +						power-domains = <&pgc_hsiomix>;
> +					};
> +
> +					pgc_otg2: power-domain@3 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_OTG2>;
> +						power-domains = <&pgc_hsiomix>;
> +					};
> +
> +					pgc_gpumix: power-domain@4 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
> +						clocks = <&clk
> IMX8MM_CLK_GPU_BUS_ROOT>,
> +							 <&clk IMX8MM_CLK_GPU_AHB>;
> +						assigned-clocks = <&clk
> IMX8MM_CLK_GPU_AXI>,
> +								  <&clk IMX8MM_CLK_GPU_AHB>;
> +						assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL1_800M>,
> +									 <&clk
> IMX8MM_SYS_PLL1_800M>;
> +						assigned-clock-rates = <800000000>,
> <400000000>;
> +					};
> +
> +					pgc_gpu: power-domain@5 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_GPU>;
> +						clocks = <&clk IMX8MM_CLK_GPU_AHB>,
> +							 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
> +							 <&clk IMX8MM_CLK_GPU2D_ROOT>,
> +							 <&clk IMX8MM_CLK_GPU3D_ROOT>;
> +						resets = <&src IMX8MQ_RESET_GPU_RESET>;
> +						power-domains = <&pgc_gpumix>;
> +					};
> +
> +					pgc_vpumix: power-domain@6 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
> +						clocks = <&clk
> IMX8MM_CLK_VPU_DEC_ROOT>;
> +						assigned-clocks = <&clk
> IMX8MM_CLK_VPU_BUS>;
> +						assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL1_800M>;
> +						resets = <&src IMX8MQ_RESET_VPU_RESET>;
> +					};
> +
> +					pgc_vpu_g1: power-domain@7 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
> +					};
> +
> +					pgc_vpu_g2: power-domain@8 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
> +					};
> +
> +					pgc_vpu_h1: power-domain@9 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
> +					};
> +
> +					pgc_dispmix: power-domain@10 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
> +						clocks = <&clk
> IMX8MM_CLK_DISP_APB_ROOT>,
> +							 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
> +						assigned-clocks = <&clk
> IMX8MM_CLK_DISP_AXI>,
> +								  <&clk IMX8MM_CLK_DISP_APB>;
> +						assigned-clock-parents = <&clk
> IMX8MM_SYS_PLL2_1000M>,
> +									 <&clk
> IMX8MM_SYS_PLL1_800M>;
> +						assigned-clock-rates = <500000000>,
> <200000000>;
> +					};
> +
> +					pgc_mipi: power-domain@11 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_MIPI>;
> +					};
> +				};
> +			};
>  		};
> 
>  		aips2: bus@30400000 {
> --
> 2.30.2


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^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 10/18] soc: imx: add i.MX8M blk-ctrl driver
  2021-07-21 20:46     ` Lucas Stach
@ 2021-08-05  9:54       ` Peng Fan
  -1 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:54 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 10/18] soc: imx: add i.MX8M blk-ctrl driver
> 
> This adds a driver for the blk-ctrl blocks found in the i.MX8M* line of SoCs.
> The blk-ctrl is a top-level peripheral located in the various *MIX power
> domains and interacts with the GPC power controller to provide the
> peripherals in the power domain access to the NoC and ensures that those
> peripherals are properly reset when their respective power domain is brought
> back to life.
> 
> Software needs to do different things to make the bus handshake happen
> after the the GPC *MIX domain is power up and before it is powered down.
> As the requirements are quite different between the various blk-ctrls there is
> a callback function provided to hook in the proper sequence.
> 
> The peripheral domains are quite uniform, they handle the soft clock enables
> and resets in the blk-ctrl address space and sequencing with the upstream
> GPC power domains.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
> This commit includes the full code to drive the VPUMIX domain on the
> i.MX8MM, as the skeleton driver would probably be harder to review without
> the context provided by one blk-ctrl implementation. Other blk-ctrl
> implementations will follow, based on this overall structure.
> ---
>  drivers/soc/imx/Makefile         |   1 +
>  drivers/soc/imx/imx8m-blk-ctrl.c | 455
> +++++++++++++++++++++++++++++++
>  2 files changed, 456 insertions(+)
>  create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c
> 
> diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile index
> 078dc918f4f3..8a707077914c 100644
> --- a/drivers/soc/imx/Makefile
> +++ b/drivers/soc/imx/Makefile
> @@ -5,3 +5,4 @@ endif
>  obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
>  obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
>  obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
> +obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
> diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c
> b/drivers/soc/imx/imx8m-blk-ctrl.c
> new file mode 100644
> index 000000000000..3dd17b903636
> --- /dev/null
> +++ b/drivers/soc/imx/imx8m-blk-ctrl.c
> @@ -0,0 +1,455 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/*
> + * Copyright 2021 Pengutronix, Lucas Stach <kernel@pengutronix.de>  */
> +
> +#include <linux/device.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/clk.h>
> +
> +#include <dt-bindings/power/imx8mm-power.h>
> +
> +#define BLK_SFT_RSTN	0x0
> +#define BLK_CLK_EN	0x4
> +
> +struct imx8m_blk_ctrl_domain;
> +
> +struct imx8m_blk_ctrl {
> +	struct device *dev;
> +	struct notifier_block power_nb;
> +	struct device *bus_power_dev;
> +	struct regmap *regmap;
> +	struct imx8m_blk_ctrl_domain *domains;
> +	struct genpd_onecell_data onecell_data; };
> +
> +struct imx8m_blk_ctrl_domain_data {
> +	const char *name;
> +	const char **clk_names;
> +	int num_clks;
> +	const char *gpc_name;
> +	u32 rst_mask;
> +	u32 clk_mask;
> +};
> +
> +#define DOMAIN_MAX_CLKS 3
> +
> +struct imx8m_blk_ctrl_domain {
> +	struct generic_pm_domain genpd;
> +	const struct imx8m_blk_ctrl_domain_data *data;
> +	struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
> +	struct device *power_dev;
> +	struct imx8m_blk_ctrl *bc;
> +};
> +
> +struct imx8m_blk_ctrl_data {
> +	int max_reg;
> +	notifier_fn_t power_notifier_fn;
> +	const struct imx8m_blk_ctrl_domain_data *domains;
> +	int num_domains;
> +};
> +
> +static inline struct imx8m_blk_ctrl_domain *
> +to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd) {
> +	return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd); }
> +
> +static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd) {
> +	struct imx8m_blk_ctrl_domain *domain =
> to_imx8m_blk_ctrl_domain(genpd);
> +	const struct imx8m_blk_ctrl_domain_data *data = domain->data;
> +	struct imx8m_blk_ctrl *bc = domain->bc;
> +	int ret;
> +
> +	/* make sure bus domain is awake */
> +	ret = pm_runtime_get_sync(bc->bus_power_dev);
> +	if (ret < 0) {
> +		pm_runtime_put_noidle(bc->bus_power_dev);
> +		dev_err(bc->dev, "failed to power up bus domain\n");
> +		return ret;
> +	}
> +
> +	/* put devices into reset */
> +	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
> +
> +	/* enable upstream and blk-ctrl clocks to allow reset to propagate */
> +	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
> +	if (ret) {
> +		dev_err(bc->dev, "failed to enable clocks\n");
> +		goto bus_put;
> +	}
> +	regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
> +
> +	/* power up upstream GPC domain */
> +	ret = pm_runtime_get_sync(domain->power_dev);
> +	if (ret < 0) {
> +		dev_err(bc->dev, "failed to power up peripheral domain\n");
> +		goto clk_disable;
> +	}
> +
> +	/* wait for reset to propagate */
> +	udelay(5);
> +
> +	/* release reset */
> +	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
> +
> +	/* disable upstream clocks */
> +	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
> +
> +	return 0;
> +
> +clk_disable:
> +	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
> +bus_put:
> +	pm_runtime_put(bc->bus_power_dev);
> +
> +	return ret;
> +}
> +
> +static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd) {
> +	struct imx8m_blk_ctrl_domain *domain =
> to_imx8m_blk_ctrl_domain(genpd);
> +	const struct imx8m_blk_ctrl_domain_data *data = domain->data;
> +	struct imx8m_blk_ctrl *bc = domain->bc;
> +
> +	/* put devices into reset and disable clocks */
> +	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
> +	regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
> +
> +	/* power down upstream GPC domain */
> +	pm_runtime_put(domain->power_dev);
> +
> +	/* allow bus domain to suspend */
> +	pm_runtime_put(bc->bus_power_dev);
> +
> +	return 0;
> +}
> +
> +static struct generic_pm_domain *
> +imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data) {
> +	struct genpd_onecell_data *onecell_data = data;
> +	unsigned int index = args->args[0];
> +
> +	if (args->args_count != 1 ||
> +	    index > onecell_data->num_domains)
> +		return ERR_PTR(-EINVAL);
> +
> +	return onecell_data->domains[index];
> +}
> +
> +static struct lock_class_key blk_ctrl_genpd_lock_class;
> +
> +static int imx8m_blk_ctrl_probe(struct platform_device *pdev) {
> +	const struct imx8m_blk_ctrl_data *bc_data;
> +	struct device *dev = &pdev->dev;
> +	struct imx8m_blk_ctrl *bc;
> +	void __iomem *base;
> +	int i, ret;
> +
> +	struct regmap_config regmap_config = {
> +		.reg_bits	= 32,
> +		.val_bits	= 32,
> +		.reg_stride	= 4,
> +	};
> +
> +	bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
> +	if (!bc)
> +		return -ENOMEM;
> +
> +	bc->dev = dev;
> +
> +	bc_data = of_device_get_match_data(dev);
> +
> +	base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(base))
> +		return PTR_ERR(base);
> +
> +	regmap_config.max_register = bc_data->max_reg;
> +	bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
> +	if (IS_ERR(bc->regmap))
> +		return dev_err_probe(dev, PTR_ERR(bc->regmap),
> +				     "failed to init regmap \n");
> +
> +	bc->domains = devm_kcalloc(dev, bc_data->num_domains,
> +				    sizeof(struct imx8m_blk_ctrl_domain),
> +				    GFP_KERNEL);
> +	if (!bc->domains)
> +		return -ENOMEM;
> +
> +	bc->onecell_data.num_domains = bc_data->num_domains;
> +	bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
> +	bc->onecell_data.domains =
> +		devm_kcalloc(dev, bc_data->num_domains,
> +			     sizeof(struct generic_pm_domain *), GFP_KERNEL);
> +	if (!bc->onecell_data.domains)
> +		return -ENOMEM;
> +
> +	bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
> +	if (IS_ERR(bc->bus_power_dev))
> +		return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
> +				     "failed to attach power domain\n");
> +
> +	for (i = 0; i < bc_data->num_domains; i++) {
> +		const struct imx8m_blk_ctrl_domain_data *data =
> &bc_data->domains[i];
> +		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
> +		int j;
> +
> +		domain->data = data;
> +
> +		for (j = 0; j < data->num_clks; j++)
> +			domain->clks[j].id = data->clk_names[j];
> +
> +		ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
> +		if (ret) {
> +			dev_err_probe(dev, ret, "failed to get clock\n");
> +			goto cleanup_pds;
> +		}
> +
> +		domain->power_dev =
> +			dev_pm_domain_attach_by_name(dev, data->gpc_name);
> +		if (IS_ERR(domain->power_dev)) {
> +			dev_err_probe(dev, PTR_ERR(domain->power_dev),
> +				      "failed to attach power domain\n");
> +			ret = PTR_ERR(domain->power_dev);
> +			goto cleanup_pds;
> +		}
> +
> +		domain->genpd.name = data->name;
> +		domain->genpd.power_on = imx8m_blk_ctrl_power_on;
> +		domain->genpd.power_off = imx8m_blk_ctrl_power_off;
> +		domain->bc = bc;
> +
> +		ret = pm_genpd_init(&domain->genpd, NULL, true);
> +		if (ret) {
> +			dev_err_probe(dev, ret, "failed to init power domain\n");
> +			dev_pm_domain_detach(domain->power_dev, true);
> +			goto cleanup_pds;
> +		}
> +
> +		/*
> +		 * We use runtime PM to trigger power on/off of the upstream GPC
> +		 * domain, as a strict hierarchical parent/child power domain
> +		 * setup doesn't allow us to meet the sequencing requirements.
> +		 * This means we have nested locking of genpd locks, without the
> +		 * nesting being visible at the genpd level, so we need a
> +		 * separate lock class to make lockdep aware of the fact that
> +		 * this are separate domain locks that can be nested without a
> +		 * self-deadlock.
> +		 */
> +		lockdep_set_class(&domain->genpd.mlock,
> +				  &blk_ctrl_genpd_lock_class);
> +
> +		bc->onecell_data.domains[i] = &domain->genpd;
> +	}
> +
> +	ret = of_genpd_add_provider_onecell(dev->of_node,
> &bc->onecell_data);
> +	if (ret) {
> +		dev_err_probe(dev, ret, "failed to add power domain provider\n");
> +		goto cleanup_pds;
> +	}
> +
> +	bc->power_nb.notifier_call = bc_data->power_notifier_fn;
> +	ret = dev_pm_genpd_add_notifier(bc->bus_power_dev,
> &bc->power_nb);
> +	if (ret) {
> +		dev_err_probe(dev, ret, "failed to add power notifier\n");
> +		goto cleanup_provider;
> +	}
> +
> +	dev_set_drvdata(dev, bc);
> +
> +	return 0;
> +
> +cleanup_provider:
> +	of_genpd_del_provider(dev->of_node);
> +cleanup_pds:
> +	for (i--; i >= 0; i--) {
> +		pm_genpd_remove(&bc->domains[i].genpd);
> +		dev_pm_domain_detach(bc->domains[i].power_dev, true);
> +	}
> +
> +	dev_pm_domain_detach(bc->bus_power_dev, true);
> +
> +	return ret;
> +}
> +
> +static int imx8m_blk_ctrl_remove(struct platform_device *pdev) {
> +	struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
> +	int i;
> +
> +	of_genpd_del_provider(pdev->dev.of_node);
> +
> +	for (i = 0; bc->onecell_data.num_domains; i++) {
> +		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
> +
> +		pm_genpd_remove(&domain->genpd);
> +		dev_pm_domain_detach(domain->power_dev, true);
> +	}
> +
> +	dev_pm_genpd_remove_notifier(bc->bus_power_dev);
> +
> +	dev_pm_domain_detach(bc->bus_power_dev, true);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int imx8m_blk_ctrl_suspend(struct device *dev) {
> +	struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);
> +	int ret, i;
> +
> +	/*
> +	 * This may look strange, but is done so the generic PM_SLEEP code
> +	 * can power down our domains and more importantly power them up
> again
> +	 * after resume, without tripping over our usage of runtime PM to
> +	 * control the upstream GPC domains. Things happen in the right order
> +	 * in the system suspend/resume paths due to the device parent/child
> +	 * hierarchy.
> +	 */
> +	ret = pm_runtime_get_sync(bc->bus_power_dev);
> +	if (ret < 0) {
> +		pm_runtime_put_noidle(bc->bus_power_dev);
> +		return ret;
> +	}
> +
> +	for (i = 0; i < bc->onecell_data.num_domains; i++) {
> +		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
> +
> +		ret = pm_runtime_get_sync(domain->power_dev);
> +		if (ret < 0) {
> +			pm_runtime_put_noidle(domain->power_dev);
> +			goto out_fail;
> +		}
> +	}
> +
> +	return 0;
> +
> +out_fail:
> +	for (i--; i >= 0; i--)
> +		pm_runtime_put(bc->domains[i].power_dev);
> +
> +	pm_runtime_put(bc->bus_power_dev);
> +
> +	return ret;
> +}
> +
> +static int imx8m_blk_ctrl_resume(struct device *dev) {
> +	struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);
> +	int i;
> +
> +	for (i = 0; i < bc->onecell_data.num_domains; i++)
> +		pm_runtime_put(bc->domains[i].power_dev);
> +
> +	pm_runtime_put(bc->bus_power_dev);
> +
> +	return 0;
> +}
> +#endif
> +
> +static const struct dev_pm_ops imx8m_blk_ctrl_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(imx8m_blk_ctrl_suspend,
> imx8m_blk_ctrl_resume)
> +};
> +
> +static int imx8mm_vpu_power_notifier(struct notifier_block *nb,
> +				     unsigned long action, void *data) {
> +	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
> +						 power_nb);
> +
> +	if (action != GENPD_NOTIFY_ON && action !=
> GENPD_NOTIFY_PRE_OFF)
> +		return NOTIFY_OK;
> +
> +	/*
> +	 * The ADB in the VPUMIX domain has no separate reset and clock
> +	 * enable bits, but is ungated together with the VPU clocks. To
> +	 * allow the handshake with the GPC to progress we put the VPUs
> +	 * in reset and ungate the clocks.
> +	 */
> +	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN,
> +			  BIT(0) | BIT(1) | BIT(2));
> +	regmap_set_bits(bc->regmap, BLK_CLK_EN,
> +			BIT(0) | BIT(1) | BIT(2));
> +
> +	if (action == GENPD_NOTIFY_ON) {
> +		/*
> +		 * On power up we have no software backchannel to the GPC to
> +		 * wait for the ADB handshake to happen, so we just delay for a
> +		 * bit. On power down the GPC driver waits for the handshake.
> +		 */
> +		udelay(5);
> +
> +		/* set "fuse" bits to enable the VPUs */
> +		regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
> +		regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
> +		regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
> +		regmap_set_bits(bc->regmap, 0x14, 0xffffffff);
> +	}
> +
> +	return NOTIFY_OK;
> +}
> +
> +static const struct imx8m_blk_ctrl_domain_data
> imx8m_vpu_blk_ctl_domain_data[] = {
> +	[IMX8MM_VPUBLK_PD_G1] = {
> +		.name = "vpublk-g1",
> +		.clk_names = (const char *[]){ "g1", },
> +		.num_clks = 1,
> +		.gpc_name = "g1",
> +		.rst_mask = BIT(1),
> +		.clk_mask = BIT(1),
> +	},
> +	[IMX8MM_VPUBLK_PD_G2] = {
> +		.name = "vpublk-g2",
> +		.clk_names = (const char *[]){ "g2", },
> +		.num_clks = 1,
> +		.gpc_name = "g2",
> +		.rst_mask = BIT(0),
> +		.clk_mask = BIT(0),
> +	},
> +	[IMX8MM_VPUBLK_PD_H1] = {
> +		.name = "vpublk-h1",
> +		.clk_names = (const char *[]){ "h1", },
> +		.num_clks = 1,
> +		.gpc_name = "h1",
> +		.rst_mask = BIT(2),
> +		.clk_mask = BIT(2),
> +	},
> +};
> +
> +static const struct imx8m_blk_ctrl_data imx8m_vpu_blk_ctl_dev_data = {
> +	.max_reg = 0x18,
> +	.power_notifier_fn = imx8mm_vpu_power_notifier,
> +	.domains = imx8m_vpu_blk_ctl_domain_data,
> +	.num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
> +};
> +
> +static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
> +	{
> +		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
> +		.data = &imx8m_vpu_blk_ctl_dev_data
> +	}, {
> +		/* Sentinel */
> +	}
> +};
> +MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
> +
> +static struct platform_driver imx8m_blk_ctrl_driver = {
> +	.probe = imx8m_blk_ctrl_probe,
> +	.remove = imx8m_blk_ctrl_remove,
> +	.driver = {
> +		.name = "imx8m-blk-ctrl",
> +		.pm = &imx8m_blk_ctrl_pm_ops,
> +		.of_match_table = imx8m_blk_ctrl_of_match,
> +	},
> +};
> +module_platform_driver(imx8m_blk_ctrl_driver);
> --
> 2.30.2


^ permalink raw reply	[flat|nested] 136+ messages in thread

* RE: [PATCH v2 10/18] soc: imx: add i.MX8M blk-ctrl driver
@ 2021-08-05  9:54       ` Peng Fan
  0 siblings, 0 replies; 136+ messages in thread
From: Peng Fan @ 2021-08-05  9:54 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: dl-linux-imx, Adam Ford, Frieder Schrempf, Marek Vasut,
	devicetree, linux-arm-kernel, kernel, patchwork-lst

> Subject: [PATCH v2 10/18] soc: imx: add i.MX8M blk-ctrl driver
> 
> This adds a driver for the blk-ctrl blocks found in the i.MX8M* line of SoCs.
> The blk-ctrl is a top-level peripheral located in the various *MIX power
> domains and interacts with the GPC power controller to provide the
> peripherals in the power domain access to the NoC and ensures that those
> peripherals are properly reset when their respective power domain is brought
> back to life.
> 
> Software needs to do different things to make the bus handshake happen
> after the the GPC *MIX domain is power up and before it is powered down.
> As the requirements are quite different between the various blk-ctrls there is
> a callback function provided to hook in the proper sequence.
> 
> The peripheral domains are quite uniform, they handle the soft clock enables
> and resets in the blk-ctrl address space and sequencing with the upstream
> GPC power domains.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
> This commit includes the full code to drive the VPUMIX domain on the
> i.MX8MM, as the skeleton driver would probably be harder to review without
> the context provided by one blk-ctrl implementation. Other blk-ctrl
> implementations will follow, based on this overall structure.
> ---
>  drivers/soc/imx/Makefile         |   1 +
>  drivers/soc/imx/imx8m-blk-ctrl.c | 455
> +++++++++++++++++++++++++++++++
>  2 files changed, 456 insertions(+)
>  create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c
> 
> diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile index
> 078dc918f4f3..8a707077914c 100644
> --- a/drivers/soc/imx/Makefile
> +++ b/drivers/soc/imx/Makefile
> @@ -5,3 +5,4 @@ endif
>  obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
>  obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
>  obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
> +obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
> diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c
> b/drivers/soc/imx/imx8m-blk-ctrl.c
> new file mode 100644
> index 000000000000..3dd17b903636
> --- /dev/null
> +++ b/drivers/soc/imx/imx8m-blk-ctrl.c
> @@ -0,0 +1,455 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/*
> + * Copyright 2021 Pengutronix, Lucas Stach <kernel@pengutronix.de>  */
> +
> +#include <linux/device.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/clk.h>
> +
> +#include <dt-bindings/power/imx8mm-power.h>
> +
> +#define BLK_SFT_RSTN	0x0
> +#define BLK_CLK_EN	0x4
> +
> +struct imx8m_blk_ctrl_domain;
> +
> +struct imx8m_blk_ctrl {
> +	struct device *dev;
> +	struct notifier_block power_nb;
> +	struct device *bus_power_dev;
> +	struct regmap *regmap;
> +	struct imx8m_blk_ctrl_domain *domains;
> +	struct genpd_onecell_data onecell_data; };
> +
> +struct imx8m_blk_ctrl_domain_data {
> +	const char *name;
> +	const char **clk_names;
> +	int num_clks;
> +	const char *gpc_name;
> +	u32 rst_mask;
> +	u32 clk_mask;
> +};
> +
> +#define DOMAIN_MAX_CLKS 3
> +
> +struct imx8m_blk_ctrl_domain {
> +	struct generic_pm_domain genpd;
> +	const struct imx8m_blk_ctrl_domain_data *data;
> +	struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
> +	struct device *power_dev;
> +	struct imx8m_blk_ctrl *bc;
> +};
> +
> +struct imx8m_blk_ctrl_data {
> +	int max_reg;
> +	notifier_fn_t power_notifier_fn;
> +	const struct imx8m_blk_ctrl_domain_data *domains;
> +	int num_domains;
> +};
> +
> +static inline struct imx8m_blk_ctrl_domain *
> +to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd) {
> +	return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd); }
> +
> +static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd) {
> +	struct imx8m_blk_ctrl_domain *domain =
> to_imx8m_blk_ctrl_domain(genpd);
> +	const struct imx8m_blk_ctrl_domain_data *data = domain->data;
> +	struct imx8m_blk_ctrl *bc = domain->bc;
> +	int ret;
> +
> +	/* make sure bus domain is awake */
> +	ret = pm_runtime_get_sync(bc->bus_power_dev);
> +	if (ret < 0) {
> +		pm_runtime_put_noidle(bc->bus_power_dev);
> +		dev_err(bc->dev, "failed to power up bus domain\n");
> +		return ret;
> +	}
> +
> +	/* put devices into reset */
> +	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
> +
> +	/* enable upstream and blk-ctrl clocks to allow reset to propagate */
> +	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
> +	if (ret) {
> +		dev_err(bc->dev, "failed to enable clocks\n");
> +		goto bus_put;
> +	}
> +	regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
> +
> +	/* power up upstream GPC domain */
> +	ret = pm_runtime_get_sync(domain->power_dev);
> +	if (ret < 0) {
> +		dev_err(bc->dev, "failed to power up peripheral domain\n");
> +		goto clk_disable;
> +	}
> +
> +	/* wait for reset to propagate */
> +	udelay(5);
> +
> +	/* release reset */
> +	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
> +
> +	/* disable upstream clocks */
> +	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
> +
> +	return 0;
> +
> +clk_disable:
> +	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
> +bus_put:
> +	pm_runtime_put(bc->bus_power_dev);
> +
> +	return ret;
> +}
> +
> +static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd) {
> +	struct imx8m_blk_ctrl_domain *domain =
> to_imx8m_blk_ctrl_domain(genpd);
> +	const struct imx8m_blk_ctrl_domain_data *data = domain->data;
> +	struct imx8m_blk_ctrl *bc = domain->bc;
> +
> +	/* put devices into reset and disable clocks */
> +	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
> +	regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
> +
> +	/* power down upstream GPC domain */
> +	pm_runtime_put(domain->power_dev);
> +
> +	/* allow bus domain to suspend */
> +	pm_runtime_put(bc->bus_power_dev);
> +
> +	return 0;
> +}
> +
> +static struct generic_pm_domain *
> +imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data) {
> +	struct genpd_onecell_data *onecell_data = data;
> +	unsigned int index = args->args[0];
> +
> +	if (args->args_count != 1 ||
> +	    index > onecell_data->num_domains)
> +		return ERR_PTR(-EINVAL);
> +
> +	return onecell_data->domains[index];
> +}
> +
> +static struct lock_class_key blk_ctrl_genpd_lock_class;
> +
> +static int imx8m_blk_ctrl_probe(struct platform_device *pdev) {
> +	const struct imx8m_blk_ctrl_data *bc_data;
> +	struct device *dev = &pdev->dev;
> +	struct imx8m_blk_ctrl *bc;
> +	void __iomem *base;
> +	int i, ret;
> +
> +	struct regmap_config regmap_config = {
> +		.reg_bits	= 32,
> +		.val_bits	= 32,
> +		.reg_stride	= 4,
> +	};
> +
> +	bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
> +	if (!bc)
> +		return -ENOMEM;
> +
> +	bc->dev = dev;
> +
> +	bc_data = of_device_get_match_data(dev);
> +
> +	base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(base))
> +		return PTR_ERR(base);
> +
> +	regmap_config.max_register = bc_data->max_reg;
> +	bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
> +	if (IS_ERR(bc->regmap))
> +		return dev_err_probe(dev, PTR_ERR(bc->regmap),
> +				     "failed to init regmap \n");
> +
> +	bc->domains = devm_kcalloc(dev, bc_data->num_domains,
> +				    sizeof(struct imx8m_blk_ctrl_domain),
> +				    GFP_KERNEL);
> +	if (!bc->domains)
> +		return -ENOMEM;
> +
> +	bc->onecell_data.num_domains = bc_data->num_domains;
> +	bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
> +	bc->onecell_data.domains =
> +		devm_kcalloc(dev, bc_data->num_domains,
> +			     sizeof(struct generic_pm_domain *), GFP_KERNEL);
> +	if (!bc->onecell_data.domains)
> +		return -ENOMEM;
> +
> +	bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
> +	if (IS_ERR(bc->bus_power_dev))
> +		return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
> +				     "failed to attach power domain\n");
> +
> +	for (i = 0; i < bc_data->num_domains; i++) {
> +		const struct imx8m_blk_ctrl_domain_data *data =
> &bc_data->domains[i];
> +		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
> +		int j;
> +
> +		domain->data = data;
> +
> +		for (j = 0; j < data->num_clks; j++)
> +			domain->clks[j].id = data->clk_names[j];
> +
> +		ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
> +		if (ret) {
> +			dev_err_probe(dev, ret, "failed to get clock\n");
> +			goto cleanup_pds;
> +		}
> +
> +		domain->power_dev =
> +			dev_pm_domain_attach_by_name(dev, data->gpc_name);
> +		if (IS_ERR(domain->power_dev)) {
> +			dev_err_probe(dev, PTR_ERR(domain->power_dev),
> +				      "failed to attach power domain\n");
> +			ret = PTR_ERR(domain->power_dev);
> +			goto cleanup_pds;
> +		}
> +
> +		domain->genpd.name = data->name;
> +		domain->genpd.power_on = imx8m_blk_ctrl_power_on;
> +		domain->genpd.power_off = imx8m_blk_ctrl_power_off;
> +		domain->bc = bc;
> +
> +		ret = pm_genpd_init(&domain->genpd, NULL, true);
> +		if (ret) {
> +			dev_err_probe(dev, ret, "failed to init power domain\n");
> +			dev_pm_domain_detach(domain->power_dev, true);
> +			goto cleanup_pds;
> +		}
> +
> +		/*
> +		 * We use runtime PM to trigger power on/off of the upstream GPC
> +		 * domain, as a strict hierarchical parent/child power domain
> +		 * setup doesn't allow us to meet the sequencing requirements.
> +		 * This means we have nested locking of genpd locks, without the
> +		 * nesting being visible at the genpd level, so we need a
> +		 * separate lock class to make lockdep aware of the fact that
> +		 * this are separate domain locks that can be nested without a
> +		 * self-deadlock.
> +		 */
> +		lockdep_set_class(&domain->genpd.mlock,
> +				  &blk_ctrl_genpd_lock_class);
> +
> +		bc->onecell_data.domains[i] = &domain->genpd;
> +	}
> +
> +	ret = of_genpd_add_provider_onecell(dev->of_node,
> &bc->onecell_data);
> +	if (ret) {
> +		dev_err_probe(dev, ret, "failed to add power domain provider\n");
> +		goto cleanup_pds;
> +	}
> +
> +	bc->power_nb.notifier_call = bc_data->power_notifier_fn;
> +	ret = dev_pm_genpd_add_notifier(bc->bus_power_dev,
> &bc->power_nb);
> +	if (ret) {
> +		dev_err_probe(dev, ret, "failed to add power notifier\n");
> +		goto cleanup_provider;
> +	}
> +
> +	dev_set_drvdata(dev, bc);
> +
> +	return 0;
> +
> +cleanup_provider:
> +	of_genpd_del_provider(dev->of_node);
> +cleanup_pds:
> +	for (i--; i >= 0; i--) {
> +		pm_genpd_remove(&bc->domains[i].genpd);
> +		dev_pm_domain_detach(bc->domains[i].power_dev, true);
> +	}
> +
> +	dev_pm_domain_detach(bc->bus_power_dev, true);
> +
> +	return ret;
> +}
> +
> +static int imx8m_blk_ctrl_remove(struct platform_device *pdev) {
> +	struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
> +	int i;
> +
> +	of_genpd_del_provider(pdev->dev.of_node);
> +
> +	for (i = 0; bc->onecell_data.num_domains; i++) {
> +		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
> +
> +		pm_genpd_remove(&domain->genpd);
> +		dev_pm_domain_detach(domain->power_dev, true);
> +	}
> +
> +	dev_pm_genpd_remove_notifier(bc->bus_power_dev);
> +
> +	dev_pm_domain_detach(bc->bus_power_dev, true);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int imx8m_blk_ctrl_suspend(struct device *dev) {
> +	struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);
> +	int ret, i;
> +
> +	/*
> +	 * This may look strange, but is done so the generic PM_SLEEP code
> +	 * can power down our domains and more importantly power them up
> again
> +	 * after resume, without tripping over our usage of runtime PM to
> +	 * control the upstream GPC domains. Things happen in the right order
> +	 * in the system suspend/resume paths due to the device parent/child
> +	 * hierarchy.
> +	 */
> +	ret = pm_runtime_get_sync(bc->bus_power_dev);
> +	if (ret < 0) {
> +		pm_runtime_put_noidle(bc->bus_power_dev);
> +		return ret;
> +	}
> +
> +	for (i = 0; i < bc->onecell_data.num_domains; i++) {
> +		struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
> +
> +		ret = pm_runtime_get_sync(domain->power_dev);
> +		if (ret < 0) {
> +			pm_runtime_put_noidle(domain->power_dev);
> +			goto out_fail;
> +		}
> +	}
> +
> +	return 0;
> +
> +out_fail:
> +	for (i--; i >= 0; i--)
> +		pm_runtime_put(bc->domains[i].power_dev);
> +
> +	pm_runtime_put(bc->bus_power_dev);
> +
> +	return ret;
> +}
> +
> +static int imx8m_blk_ctrl_resume(struct device *dev) {
> +	struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);
> +	int i;
> +
> +	for (i = 0; i < bc->onecell_data.num_domains; i++)
> +		pm_runtime_put(bc->domains[i].power_dev);
> +
> +	pm_runtime_put(bc->bus_power_dev);
> +
> +	return 0;
> +}
> +#endif
> +
> +static const struct dev_pm_ops imx8m_blk_ctrl_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(imx8m_blk_ctrl_suspend,
> imx8m_blk_ctrl_resume)
> +};
> +
> +static int imx8mm_vpu_power_notifier(struct notifier_block *nb,
> +				     unsigned long action, void *data) {
> +	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
> +						 power_nb);
> +
> +	if (action != GENPD_NOTIFY_ON && action !=
> GENPD_NOTIFY_PRE_OFF)
> +		return NOTIFY_OK;
> +
> +	/*
> +	 * The ADB in the VPUMIX domain has no separate reset and clock
> +	 * enable bits, but is ungated together with the VPU clocks. To
> +	 * allow the handshake with the GPC to progress we put the VPUs
> +	 * in reset and ungate the clocks.
> +	 */
> +	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN,
> +			  BIT(0) | BIT(1) | BIT(2));
> +	regmap_set_bits(bc->regmap, BLK_CLK_EN,
> +			BIT(0) | BIT(1) | BIT(2));
> +
> +	if (action == GENPD_NOTIFY_ON) {
> +		/*
> +		 * On power up we have no software backchannel to the GPC to
> +		 * wait for the ADB handshake to happen, so we just delay for a
> +		 * bit. On power down the GPC driver waits for the handshake.
> +		 */
> +		udelay(5);
> +
> +		/* set "fuse" bits to enable the VPUs */
> +		regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
> +		regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
> +		regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
> +		regmap_set_bits(bc->regmap, 0x14, 0xffffffff);
> +	}
> +
> +	return NOTIFY_OK;
> +}
> +
> +static const struct imx8m_blk_ctrl_domain_data
> imx8m_vpu_blk_ctl_domain_data[] = {
> +	[IMX8MM_VPUBLK_PD_G1] = {
> +		.name = "vpublk-g1",
> +		.clk_names = (const char *[]){ "g1", },
> +		.num_clks = 1,
> +		.gpc_name = "g1",
> +		.rst_mask = BIT(1),
> +		.clk_mask = BIT(1),
> +	},
> +	[IMX8MM_VPUBLK_PD_G2] = {
> +		.name = "vpublk-g2",
> +		.clk_names = (const char *[]){ "g2", },
> +		.num_clks = 1,
> +		.gpc_name = "g2",
> +		.rst_mask = BIT(0),
> +		.clk_mask = BIT(0),
> +	},
> +	[IMX8MM_VPUBLK_PD_H1] = {
> +		.name = "vpublk-h1",
> +		.clk_names = (const char *[]){ "h1", },
> +		.num_clks = 1,
> +		.gpc_name = "h1",
> +		.rst_mask = BIT(2),
> +		.clk_mask = BIT(2),
> +	},
> +};
> +
> +static const struct imx8m_blk_ctrl_data imx8m_vpu_blk_ctl_dev_data = {
> +	.max_reg = 0x18,
> +	.power_notifier_fn = imx8mm_vpu_power_notifier,
> +	.domains = imx8m_vpu_blk_ctl_domain_data,
> +	.num_domains = ARRAY_SIZE(imx8m_vpu_blk_ctl_domain_data),
> +};
> +
> +static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
> +	{
> +		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
> +		.data = &imx8m_vpu_blk_ctl_dev_data
> +	}, {
> +		/* Sentinel */
> +	}
> +};
> +MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
> +
> +static struct platform_driver imx8m_blk_ctrl_driver = {
> +	.probe = imx8m_blk_ctrl_probe,
> +	.remove = imx8m_blk_ctrl_remove,
> +	.driver = {
> +		.name = "imx8m-blk-ctrl",
> +		.pm = &imx8m_blk_ctrl_pm_ops,
> +		.of_match_table = imx8m_blk_ctrl_of_match,
> +	},
> +};
> +module_platform_driver(imx8m_blk_ctrl_driver);
> --
> 2.30.2


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^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-07-21 20:46   ` Lucas Stach
@ 2021-08-05 10:18     ` Frieder Schrempf
  -1 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-08-05 10:18 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst

On 21.07.21 22:46, Lucas Stach wrote:
> Hi all,
> 
> second revision of the GPC improvements and BLK_CTRL driver to make use
> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
> blurb from the v1 cover letter here, but if you are not familiar with
> i.MX8MM power domains, it may be worth a read.
> 
> This 2nd revision fixes the DT bindings to be valid yaml, some small
> failure path issues and most importantly the interaction with system
> suspend/resume. With the previous version some of the power domains
> would not come up correctly after a suspend/resume cycle.
> 
> Updated testing git trees here, disclaimer still applies:
> https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains
> https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing

I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!

I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-08-05 10:18     ` Frieder Schrempf
  0 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-08-05 10:18 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst

On 21.07.21 22:46, Lucas Stach wrote:
> Hi all,
> 
> second revision of the GPC improvements and BLK_CTRL driver to make use
> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
> blurb from the v1 cover letter here, but if you are not familiar with
> i.MX8MM power domains, it may be worth a read.
> 
> This 2nd revision fixes the DT bindings to be valid yaml, some small
> failure path issues and most importantly the interaction with system
> suspend/resume. With the previous version some of the power domains
> would not come up correctly after a suspend/resume cycle.
> 
> Updated testing git trees here, disclaimer still applies:
> https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains
> https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing

I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!

I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-08-05 10:18     ` Frieder Schrempf
@ 2021-08-05 18:56       ` Frieder Schrempf
  -1 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-08-05 18:56 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst

On 05.08.21 12:18, Frieder Schrempf wrote:
> On 21.07.21 22:46, Lucas Stach wrote:
>> Hi all,
>>
>> second revision of the GPC improvements and BLK_CTRL driver to make use
>> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
>> blurb from the v1 cover letter here, but if you are not familiar with
>> i.MX8MM power domains, it may be worth a read.
>>
>> This 2nd revision fixes the DT bindings to be valid yaml, some small
>> failure path issues and most importantly the interaction with system
>> suspend/resume. With the previous version some of the power domains
>> would not come up correctly after a suspend/resume cycle.
>>
>> Updated testing git trees here, disclaimer still applies:
>> https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains
>> https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing
> 
> I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
> 
> I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
> 

Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.

Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.

If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.

And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:

#!/bin/sh

glmark2-es2-drm &

while true;
do
    echo +10 > /sys/class/rtc/rtc0/wakealarm
    echo mem > /sys/power/state
    sleep 5
done;

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-08-05 18:56       ` Frieder Schrempf
  0 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-08-05 18:56 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst

On 05.08.21 12:18, Frieder Schrempf wrote:
> On 21.07.21 22:46, Lucas Stach wrote:
>> Hi all,
>>
>> second revision of the GPC improvements and BLK_CTRL driver to make use
>> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
>> blurb from the v1 cover letter here, but if you are not familiar with
>> i.MX8MM power domains, it may be worth a read.
>>
>> This 2nd revision fixes the DT bindings to be valid yaml, some small
>> failure path issues and most importantly the interaction with system
>> suspend/resume. With the previous version some of the power domains
>> would not come up correctly after a suspend/resume cycle.
>>
>> Updated testing git trees here, disclaimer still applies:
>> https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains
>> https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing
> 
> I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
> 
> I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
> 

Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.

Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.

If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.

And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:

#!/bin/sh

glmark2-es2-drm &

while true;
do
    echo +10 > /sys/class/rtc/rtc0/wakealarm
    echo mem > /sys/power/state
    sleep 5
done;

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-08-05 18:56       ` Frieder Schrempf
@ 2021-08-09 11:01         ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-08-09 11:01 UTC (permalink / raw)
  To: Frieder Schrempf, Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst

Hi Frieder,

Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
> On 05.08.21 12:18, Frieder Schrempf wrote:
> > On 21.07.21 22:46, Lucas Stach wrote:
> > > Hi all,
> > > 
> > > second revision of the GPC improvements and BLK_CTRL driver to make use
> > > of all the power-domains on the i.MX8MM. I'm not going to repeat the full
> > > blurb from the v1 cover letter here, but if you are not familiar with
> > > i.MX8MM power domains, it may be worth a read.
> > > 
> > > This 2nd revision fixes the DT bindings to be valid yaml, some small
> > > failure path issues and most importantly the interaction with system
> > > suspend/resume. With the previous version some of the power domains
> > > would not come up correctly after a suspend/resume cycle.
> > > 
> > > Updated testing git trees here, disclaimer still applies:
> > > https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains
> > > https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing
> > 
> > I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
> > 
> > I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
> > 
> 
> Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
> 
> Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
> 
> If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
> 
> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
> 
> #!/bin/sh
> 
> glmark2-es2-drm &
> 
> while true;
> do
>     echo +10 > /sys/class/rtc/rtc0/wakealarm
>     echo mem > /sys/power/state
>     sleep 5
> done;

Hm, that's unfortunate.

I'm back from a two week vacation, but it looks like I won't have much
time available to look into this issue soon. It would be very helpful
if you could try to pinpoint the hang a bit more.  If you can reproduce
the hang with no_console_suspend you might be able to extract a bit
more info in which stage the hang happens (suspend, resume, TF-A, etc.)
If the hang is in the kernel you might be able to add some prints to
the suspend/resume paths to be able to track down the exact point of
the hang.

I'm happy to look into the issue once it's better known where to look,
but I fear that I won't have time to do the above investigation myself
short term. Frieder, is this something you could help with over the
next few days?

Regards,
Lucas


^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-08-09 11:01         ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-08-09 11:01 UTC (permalink / raw)
  To: Frieder Schrempf, Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst

Hi Frieder,

Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
> On 05.08.21 12:18, Frieder Schrempf wrote:
> > On 21.07.21 22:46, Lucas Stach wrote:
> > > Hi all,
> > > 
> > > second revision of the GPC improvements and BLK_CTRL driver to make use
> > > of all the power-domains on the i.MX8MM. I'm not going to repeat the full
> > > blurb from the v1 cover letter here, but if you are not familiar with
> > > i.MX8MM power domains, it may be worth a read.
> > > 
> > > This 2nd revision fixes the DT bindings to be valid yaml, some small
> > > failure path issues and most importantly the interaction with system
> > > suspend/resume. With the previous version some of the power domains
> > > would not come up correctly after a suspend/resume cycle.
> > > 
> > > Updated testing git trees here, disclaimer still applies:
> > > https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains
> > > https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing
> > 
> > I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
> > 
> > I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
> > 
> 
> Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
> 
> Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
> 
> If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
> 
> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
> 
> #!/bin/sh
> 
> glmark2-es2-drm &
> 
> while true;
> do
>     echo +10 > /sys/class/rtc/rtc0/wakealarm
>     echo mem > /sys/power/state
>     sleep 5
> done;

Hm, that's unfortunate.

I'm back from a two week vacation, but it looks like I won't have much
time available to look into this issue soon. It would be very helpful
if you could try to pinpoint the hang a bit more.  If you can reproduce
the hang with no_console_suspend you might be able to extract a bit
more info in which stage the hang happens (suspend, resume, TF-A, etc.)
If the hang is in the kernel you might be able to add some prints to
the suspend/resume paths to be able to track down the exact point of
the hang.

I'm happy to look into the issue once it's better known where to look,
but I fear that I won't have time to do the above investigation myself
short term. Frieder, is this something you could help with over the
next few days?

Regards,
Lucas


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-08-09 11:01         ` Lucas Stach
@ 2021-08-09 11:50           ` Frieder Schrempf
  -1 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-08-09 11:50 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst

On 09.08.21 13:01, Lucas Stach wrote:
> Hi Frieder,
> 
> Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
>> On 05.08.21 12:18, Frieder Schrempf wrote:
>>> On 21.07.21 22:46, Lucas Stach wrote:
>>>> Hi all,
>>>>
>>>> second revision of the GPC improvements and BLK_CTRL driver to make use
>>>> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
>>>> blurb from the v1 cover letter here, but if you are not familiar with
>>>> i.MX8MM power domains, it may be worth a read.
>>>>
>>>> This 2nd revision fixes the DT bindings to be valid yaml, some small
>>>> failure path issues and most importantly the interaction with system
>>>> suspend/resume. With the previous version some of the power domains
>>>> would not come up correctly after a suspend/resume cycle.
>>>>
>>>> Updated testing git trees here, disclaimer still applies:
>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C189884f9332e40cd566a08d95b250a82%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637641036912506485%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=OlymcyF9VOt6nsb2E%2BpFLTBnmlpOIOxwzdBbggPu%2FHo%3D&amp;reserved=0
>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains-testing&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C189884f9332e40cd566a08d95b250a82%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637641036912506485%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=XSHl3JDKPFX%2FifXK5fcMQFOXbQXuHOJaNnJ3%2BtrMErk%3D&amp;reserved=0
>>>
>>> I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
>>>
>>> I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
>>>
>>
>> Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
>>
>> Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
>>
>> If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
>>
>> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
>>
>> #!/bin/sh
>>
>> glmark2-es2-drm &
>>
>> while true;
>> do
>>     echo +10 > /sys/class/rtc/rtc0/wakealarm
>>     echo mem > /sys/power/state
>>     sleep 5
>> done;
> 
> Hm, that's unfortunate.
> 
> I'm back from a two week vacation, but it looks like I won't have much
> time available to look into this issue soon. It would be very helpful
> if you could try to pinpoint the hang a bit more.  If you can reproduce
> the hang with no_console_suspend you might be able to extract a bit
> more info in which stage the hang happens (suspend, resume, TF-A, etc.)
> If the hang is in the kernel you might be able to add some prints to
> the suspend/resume paths to be able to track down the exact point of
> the hang.
> 
> I'm happy to look into the issue once it's better known where to look,
> but I fear that I won't have time to do the above investigation myself
> short term. Frieder, is this something you could help with over the
> next few days?

I will see if I can find some time to track down the issue at least a little bit more. But I imagine it could get quite tedious if it takes up to several hours to reproduce the issue and I don't have much time to spare.

@Peng, @Adam and everyone else: Any chance you could setup a similar test and try to reproduce this?

On the other hand reboot cycle testing didn't show any lockup problems over more than 24 hours, so it seems like the issue is limited to resume.

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-08-09 11:50           ` Frieder Schrempf
  0 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-08-09 11:50 UTC (permalink / raw)
  To: Lucas Stach, Shawn Guo, Rob Herring
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst

On 09.08.21 13:01, Lucas Stach wrote:
> Hi Frieder,
> 
> Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
>> On 05.08.21 12:18, Frieder Schrempf wrote:
>>> On 21.07.21 22:46, Lucas Stach wrote:
>>>> Hi all,
>>>>
>>>> second revision of the GPC improvements and BLK_CTRL driver to make use
>>>> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
>>>> blurb from the v1 cover letter here, but if you are not familiar with
>>>> i.MX8MM power domains, it may be worth a read.
>>>>
>>>> This 2nd revision fixes the DT bindings to be valid yaml, some small
>>>> failure path issues and most importantly the interaction with system
>>>> suspend/resume. With the previous version some of the power domains
>>>> would not come up correctly after a suspend/resume cycle.
>>>>
>>>> Updated testing git trees here, disclaimer still applies:
>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C189884f9332e40cd566a08d95b250a82%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637641036912506485%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=OlymcyF9VOt6nsb2E%2BpFLTBnmlpOIOxwzdBbggPu%2FHo%3D&amp;reserved=0
>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains-testing&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C189884f9332e40cd566a08d95b250a82%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637641036912506485%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=XSHl3JDKPFX%2FifXK5fcMQFOXbQXuHOJaNnJ3%2BtrMErk%3D&amp;reserved=0
>>>
>>> I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
>>>
>>> I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
>>>
>>
>> Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
>>
>> Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
>>
>> If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
>>
>> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
>>
>> #!/bin/sh
>>
>> glmark2-es2-drm &
>>
>> while true;
>> do
>>     echo +10 > /sys/class/rtc/rtc0/wakealarm
>>     echo mem > /sys/power/state
>>     sleep 5
>> done;
> 
> Hm, that's unfortunate.
> 
> I'm back from a two week vacation, but it looks like I won't have much
> time available to look into this issue soon. It would be very helpful
> if you could try to pinpoint the hang a bit more.  If you can reproduce
> the hang with no_console_suspend you might be able to extract a bit
> more info in which stage the hang happens (suspend, resume, TF-A, etc.)
> If the hang is in the kernel you might be able to add some prints to
> the suspend/resume paths to be able to track down the exact point of
> the hang.
> 
> I'm happy to look into the issue once it's better known where to look,
> but I fear that I won't have time to do the above investigation myself
> short term. Frieder, is this something you could help with over the
> next few days?

I will see if I can find some time to track down the issue at least a little bit more. But I imagine it could get quite tedious if it takes up to several hours to reproduce the issue and I don't have much time to spare.

@Peng, @Adam and everyone else: Any chance you could setup a similar test and try to reproduce this?

On the other hand reboot cycle testing didn't show any lockup problems over more than 24 hours, so it seems like the issue is limited to resume.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-08-09 11:50           ` Frieder Schrempf
@ 2021-08-09 18:51             ` Adam Ford
  -1 siblings, 0 replies; 136+ messages in thread
From: Adam Ford @ 2021-08-09 18:51 UTC (permalink / raw)
  To: Frieder Schrempf
  Cc: Lucas Stach, Shawn Guo, Rob Herring, NXP Linux Team, Peng Fan,
	Marek Vasut, devicetree, arm-soc, Sascha Hauer, patchwork-lst

On Mon, Aug 9, 2021 at 6:50 AM Frieder Schrempf
<frieder.schrempf@kontron.de> wrote:
>
> On 09.08.21 13:01, Lucas Stach wrote:
> > Hi Frieder,
> >
> > Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
> >> On 05.08.21 12:18, Frieder Schrempf wrote:
> >>> On 21.07.21 22:46, Lucas Stach wrote:
> >>>> Hi all,
> >>>>
> >>>> second revision of the GPC improvements and BLK_CTRL driver to make use
> >>>> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
> >>>> blurb from the v1 cover letter here, but if you are not familiar with
> >>>> i.MX8MM power domains, it may be worth a read.
> >>>>
> >>>> This 2nd revision fixes the DT bindings to be valid yaml, some small
> >>>> failure path issues and most importantly the interaction with system
> >>>> suspend/resume. With the previous version some of the power domains
> >>>> would not come up correctly after a suspend/resume cycle.
> >>>>
> >>>> Updated testing git trees here, disclaimer still applies:
> >>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C189884f9332e40cd566a08d95b250a82%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637641036912506485%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=OlymcyF9VOt6nsb2E%2BpFLTBnmlpOIOxwzdBbggPu%2FHo%3D&amp;reserved=0
> >>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains-testing&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C189884f9332e40cd566a08d95b250a82%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637641036912506485%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=XSHl3JDKPFX%2FifXK5fcMQFOXbQXuHOJaNnJ3%2BtrMErk%3D&amp;reserved=0
> >>>
> >>> I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
> >>>
> >>> I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
> >>>
> >>
> >> Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
> >>
> >> Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
> >>
> >> If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
> >>
> >> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
> >>
> >> #!/bin/sh
> >>
> >> glmark2-es2-drm &
> >>
> >> while true;
> >> do
> >>     echo +10 > /sys/class/rtc/rtc0/wakealarm
> >>     echo mem > /sys/power/state
> >>     sleep 5
> >> done;
> >
> > Hm, that's unfortunate.
> >
> > I'm back from a two week vacation, but it looks like I won't have much
> > time available to look into this issue soon. It would be very helpful
> > if you could try to pinpoint the hang a bit more.  If you can reproduce
> > the hang with no_console_suspend you might be able to extract a bit
> > more info in which stage the hang happens (suspend, resume, TF-A, etc.)
> > If the hang is in the kernel you might be able to add some prints to
> > the suspend/resume paths to be able to track down the exact point of
> > the hang.
> >
> > I'm happy to look into the issue once it's better known where to look,
> > but I fear that I won't have time to do the above investigation myself
> > short term. Frieder, is this something you could help with over the
> > next few days?
>
> I will see if I can find some time to track down the issue at least a little bit more. But I imagine it could get quite tedious if it takes up to several hours to reproduce the issue and I don't have much time to spare.
>
> @Peng, @Adam and everyone else: Any chance you could setup a similar test and try to reproduce this?

right now i am on medical leave due to a broken wrist, and i wont be
able to help until it heals.

sorry

adam
>
> On the other hand reboot cycle testing didn't show any lockup problems over more than 24 hours, so it seems like the issue is limited to resume.

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-08-09 18:51             ` Adam Ford
  0 siblings, 0 replies; 136+ messages in thread
From: Adam Ford @ 2021-08-09 18:51 UTC (permalink / raw)
  To: Frieder Schrempf
  Cc: Lucas Stach, Shawn Guo, Rob Herring, NXP Linux Team, Peng Fan,
	Marek Vasut, devicetree, arm-soc, Sascha Hauer, patchwork-lst

On Mon, Aug 9, 2021 at 6:50 AM Frieder Schrempf
<frieder.schrempf@kontron.de> wrote:
>
> On 09.08.21 13:01, Lucas Stach wrote:
> > Hi Frieder,
> >
> > Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
> >> On 05.08.21 12:18, Frieder Schrempf wrote:
> >>> On 21.07.21 22:46, Lucas Stach wrote:
> >>>> Hi all,
> >>>>
> >>>> second revision of the GPC improvements and BLK_CTRL driver to make use
> >>>> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
> >>>> blurb from the v1 cover letter here, but if you are not familiar with
> >>>> i.MX8MM power domains, it may be worth a read.
> >>>>
> >>>> This 2nd revision fixes the DT bindings to be valid yaml, some small
> >>>> failure path issues and most importantly the interaction with system
> >>>> suspend/resume. With the previous version some of the power domains
> >>>> would not come up correctly after a suspend/resume cycle.
> >>>>
> >>>> Updated testing git trees here, disclaimer still applies:
> >>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C189884f9332e40cd566a08d95b250a82%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637641036912506485%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=OlymcyF9VOt6nsb2E%2BpFLTBnmlpOIOxwzdBbggPu%2FHo%3D&amp;reserved=0
> >>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains-testing&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C189884f9332e40cd566a08d95b250a82%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637641036912506485%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=XSHl3JDKPFX%2FifXK5fcMQFOXbQXuHOJaNnJ3%2BtrMErk%3D&amp;reserved=0
> >>>
> >>> I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
> >>>
> >>> I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
> >>>
> >>
> >> Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
> >>
> >> Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
> >>
> >> If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
> >>
> >> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
> >>
> >> #!/bin/sh
> >>
> >> glmark2-es2-drm &
> >>
> >> while true;
> >> do
> >>     echo +10 > /sys/class/rtc/rtc0/wakealarm
> >>     echo mem > /sys/power/state
> >>     sleep 5
> >> done;
> >
> > Hm, that's unfortunate.
> >
> > I'm back from a two week vacation, but it looks like I won't have much
> > time available to look into this issue soon. It would be very helpful
> > if you could try to pinpoint the hang a bit more.  If you can reproduce
> > the hang with no_console_suspend you might be able to extract a bit
> > more info in which stage the hang happens (suspend, resume, TF-A, etc.)
> > If the hang is in the kernel you might be able to add some prints to
> > the suspend/resume paths to be able to track down the exact point of
> > the hang.
> >
> > I'm happy to look into the issue once it's better known where to look,
> > but I fear that I won't have time to do the above investigation myself
> > short term. Frieder, is this something you could help with over the
> > next few days?
>
> I will see if I can find some time to track down the issue at least a little bit more. But I imagine it could get quite tedious if it takes up to several hours to reproduce the issue and I don't have much time to spare.
>
> @Peng, @Adam and everyone else: Any chance you could setup a similar test and try to reproduce this?

right now i am on medical leave due to a broken wrist, and i wont be
able to help until it heals.

sorry

adam
>
> On the other hand reboot cycle testing didn't show any lockup problems over more than 24 hours, so it seems like the issue is limited to resume.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-08-09 11:01         ` Lucas Stach
@ 2021-08-30 22:06           ` Tim Harvey
  -1 siblings, 0 replies; 136+ messages in thread
From: Tim Harvey @ 2021-08-30 22:06 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Frieder Schrempf, Shawn Guo, Rob Herring, NXP Linux Team,
	Adam Ford, Peng Fan, Marek Vasut, Device Tree Mailing List,
	Linux ARM Mailing List, Sascha Hauer, patchwork-lst,
	Fabio Estevam

On Mon, Aug 9, 2021 at 4:01 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Hi Frieder,
>
> Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
> > On 05.08.21 12:18, Frieder Schrempf wrote:
> > > On 21.07.21 22:46, Lucas Stach wrote:
> > > > Hi all,
> > > >
> > > > second revision of the GPC improvements and BLK_CTRL driver to make use
> > > > of all the power-domains on the i.MX8MM. I'm not going to repeat the full
> > > > blurb from the v1 cover letter here, but if you are not familiar with
> > > > i.MX8MM power domains, it may be worth a read.
> > > >
> > > > This 2nd revision fixes the DT bindings to be valid yaml, some small
> > > > failure path issues and most importantly the interaction with system
> > > > suspend/resume. With the previous version some of the power domains
> > > > would not come up correctly after a suspend/resume cycle.
> > > >
> > > > Updated testing git trees here, disclaimer still applies:
> > > > https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains
> > > > https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing
> > >
> > > I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
> > >
> > > I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
> > >
> >
> > Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
> >
> > Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
> >
> > If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
> >
> > And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
> >
> > #!/bin/sh
> >
> > glmark2-es2-drm &
> >
> > while true;
> > do
> >     echo +10 > /sys/class/rtc/rtc0/wakealarm
> >     echo mem > /sys/power/state
> >     sleep 5
> > done;
>
> Hm, that's unfortunate.
>
> I'm back from a two week vacation, but it looks like I won't have much
> time available to look into this issue soon. It would be very helpful
> if you could try to pinpoint the hang a bit more.  If you can reproduce
> the hang with no_console_suspend you might be able to extract a bit
> more info in which stage the hang happens (suspend, resume, TF-A, etc.)
> If the hang is in the kernel you might be able to add some prints to
> the suspend/resume paths to be able to track down the exact point of
> the hang.
>
> I'm happy to look into the issue once it's better known where to look,
> but I fear that I won't have time to do the above investigation myself
> short term. Frieder, is this something you could help with over the
> next few days?
>

Lucas / Frieder,

Can you update us on where you are at with this patch series? I fear
we are going to go through another kernel release without IMX8MM
blk-ctl support and all the things that depend on it such as
USB/PCI/DSI/CSI/GPU/VPU. If there is some specific testing you need
please let me know what I can do to help. I have a variety of IMX8MM
hardware but not a lot of time or knowledge with regards to
troubleshooting suspend/resume issues.

Are the issues found a regression?

Best regards,

Tim

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-08-30 22:06           ` Tim Harvey
  0 siblings, 0 replies; 136+ messages in thread
From: Tim Harvey @ 2021-08-30 22:06 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Frieder Schrempf, Shawn Guo, Rob Herring, NXP Linux Team,
	Adam Ford, Peng Fan, Marek Vasut, Device Tree Mailing List,
	Linux ARM Mailing List, Sascha Hauer, patchwork-lst,
	Fabio Estevam

On Mon, Aug 9, 2021 at 4:01 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Hi Frieder,
>
> Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
> > On 05.08.21 12:18, Frieder Schrempf wrote:
> > > On 21.07.21 22:46, Lucas Stach wrote:
> > > > Hi all,
> > > >
> > > > second revision of the GPC improvements and BLK_CTRL driver to make use
> > > > of all the power-domains on the i.MX8MM. I'm not going to repeat the full
> > > > blurb from the v1 cover letter here, but if you are not familiar with
> > > > i.MX8MM power domains, it may be worth a read.
> > > >
> > > > This 2nd revision fixes the DT bindings to be valid yaml, some small
> > > > failure path issues and most importantly the interaction with system
> > > > suspend/resume. With the previous version some of the power domains
> > > > would not come up correctly after a suspend/resume cycle.
> > > >
> > > > Updated testing git trees here, disclaimer still applies:
> > > > https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains
> > > > https://git.pengutronix.de/cgit/lst/linux/log/?h=imx8m-power-domains-testing
> > >
> > > I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
> > >
> > > I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
> > >
> >
> > Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
> >
> > Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
> >
> > If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
> >
> > And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
> >
> > #!/bin/sh
> >
> > glmark2-es2-drm &
> >
> > while true;
> > do
> >     echo +10 > /sys/class/rtc/rtc0/wakealarm
> >     echo mem > /sys/power/state
> >     sleep 5
> > done;
>
> Hm, that's unfortunate.
>
> I'm back from a two week vacation, but it looks like I won't have much
> time available to look into this issue soon. It would be very helpful
> if you could try to pinpoint the hang a bit more.  If you can reproduce
> the hang with no_console_suspend you might be able to extract a bit
> more info in which stage the hang happens (suspend, resume, TF-A, etc.)
> If the hang is in the kernel you might be able to add some prints to
> the suspend/resume paths to be able to track down the exact point of
> the hang.
>
> I'm happy to look into the issue once it's better known where to look,
> but I fear that I won't have time to do the above investigation myself
> short term. Frieder, is this something you could help with over the
> next few days?
>

Lucas / Frieder,

Can you update us on where you are at with this patch series? I fear
we are going to go through another kernel release without IMX8MM
blk-ctl support and all the things that depend on it such as
USB/PCI/DSI/CSI/GPU/VPU. If there is some specific testing you need
please let me know what I can do to help. I have a variety of IMX8MM
hardware but not a lot of time or knowledge with regards to
troubleshooting suspend/resume issues.

Are the issues found a regression?

Best regards,

Tim

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-08-09 11:50           ` Frieder Schrempf
@ 2021-09-01 10:03             ` Frieder Schrempf
  -1 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-09-01 10:03 UTC (permalink / raw)
  To: Lucas Stach
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst, Shawn Guo, Rob Herring

Hi Lucas,

On 09.08.21 13:50, Frieder Schrempf wrote:
> On 09.08.21 13:01, Lucas Stach wrote:
>> Hi Frieder,
>>
>> Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
>>> On 05.08.21 12:18, Frieder Schrempf wrote:
>>>> On 21.07.21 22:46, Lucas Stach wrote:
>>>>> Hi all,
>>>>>
>>>>> second revision of the GPC improvements and BLK_CTRL driver to make use
>>>>> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
>>>>> blurb from the v1 cover letter here, but if you are not familiar with
>>>>> i.MX8MM power domains, it may be worth a read.
>>>>>
>>>>> This 2nd revision fixes the DT bindings to be valid yaml, some small
>>>>> failure path issues and most importantly the interaction with system
>>>>> suspend/resume. With the previous version some of the power domains
>>>>> would not come up correctly after a suspend/resume cycle.
>>>>>
>>>>> Updated testing git trees here, disclaimer still applies:
>>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7Cfc19fab094dd483e753708d95b2c3f0a%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637641067865828503%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=raKaop3FUcsfKMyu13qCeyRKCgkObRuTAc73iQ4BYSI%3D&amp;reserved=0
>>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains-testing&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7Cfc19fab094dd483e753708d95b2c3f0a%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637641067865828503%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=bmtM%2FxJ3Y9QpGkMhTDHLrLQ2AD0X7DqbspUMdkS%2B7MY%3D&amp;reserved=0
>>>>
>>>> I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
>>>>
>>>> I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
>>>>
>>>
>>> Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
>>>
>>> Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
>>>
>>> If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
>>>
>>> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
>>>
>>> #!/bin/sh
>>>
>>> glmark2-es2-drm &
>>>
>>> while true;
>>> do
>>>     echo +10 > /sys/class/rtc/rtc0/wakealarm
>>>     echo mem > /sys/power/state
>>>     sleep 5
>>> done;
>>
>> Hm, that's unfortunate.
>>
>> I'm back from a two week vacation, but it looks like I won't have much
>> time available to look into this issue soon. It would be very helpful
>> if you could try to pinpoint the hang a bit more.  If you can reproduce
>> the hang with no_console_suspend you might be able to extract a bit
>> more info in which stage the hang happens (suspend, resume, TF-A, etc.)
>> If the hang is in the kernel you might be able to add some prints to
>> the suspend/resume paths to be able to track down the exact point of
>> the hang.
>>
>> I'm happy to look into the issue once it's better known where to look,
>> but I fear that I won't have time to do the above investigation myself
>> short term. Frieder, is this something you could help with over the
>> next few days?
> 
> I will see if I can find some time to track down the issue at least a little bit more. But I imagine it could get quite tedious if it takes up to several hours to reproduce the issue and I don't have much time to spare.
> 
> @Peng, @Adam and everyone else: Any chance you could setup a similar test and try to reproduce this?
> 
> On the other hand reboot cycle testing didn't show any lockup problems over more than 24 hours, so it seems like the issue is limited to resume.

I ran a few more suspend/resume cycles and watched the log. The first
2.5 hours nothing noteworthy happened, except that glmark2 crashed again
at some point.

Then suddenly the following lines were printed while suspending:

  imx-pgc imx-pgc-domain.6: failed to command PGC
  PM: dpm_run_callback(): platform_pm_suspend+0x0/0x78 returns -110
  imx8m-blk-ctrl 38330000.blk-ctrl: PM: failed to suspend: error -110
  PM: Some devices failed to suspend, or early wake event detected

After that, the suspending continues to fail with the following on each try:

  PM: dpm_run_callback(): platform_pm_suspend+0x0/0x78 returns -22
  imx8m-blk-ctrl 38330000.blk-ctrl: PM: failed to suspend: error -22
  PM: Some devices failed to suspend, or early wake event detected

So far I didn't run into a lockup again with this test, but I will
continue trying to reproduce it and retrieve more information.

Best regards
Frieder

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-09-01 10:03             ` Frieder Schrempf
  0 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-09-01 10:03 UTC (permalink / raw)
  To: Lucas Stach
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst, Shawn Guo, Rob Herring

Hi Lucas,

On 09.08.21 13:50, Frieder Schrempf wrote:
> On 09.08.21 13:01, Lucas Stach wrote:
>> Hi Frieder,
>>
>> Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
>>> On 05.08.21 12:18, Frieder Schrempf wrote:
>>>> On 21.07.21 22:46, Lucas Stach wrote:
>>>>> Hi all,
>>>>>
>>>>> second revision of the GPC improvements and BLK_CTRL driver to make use
>>>>> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
>>>>> blurb from the v1 cover letter here, but if you are not familiar with
>>>>> i.MX8MM power domains, it may be worth a read.
>>>>>
>>>>> This 2nd revision fixes the DT bindings to be valid yaml, some small
>>>>> failure path issues and most importantly the interaction with system
>>>>> suspend/resume. With the previous version some of the power domains
>>>>> would not come up correctly after a suspend/resume cycle.
>>>>>
>>>>> Updated testing git trees here, disclaimer still applies:
>>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7Cfc19fab094dd483e753708d95b2c3f0a%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637641067865828503%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=raKaop3FUcsfKMyu13qCeyRKCgkObRuTAc73iQ4BYSI%3D&amp;reserved=0
>>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains-testing&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7Cfc19fab094dd483e753708d95b2c3f0a%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637641067865828503%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=bmtM%2FxJ3Y9QpGkMhTDHLrLQ2AD0X7DqbspUMdkS%2B7MY%3D&amp;reserved=0
>>>>
>>>> I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
>>>>
>>>> I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
>>>>
>>>
>>> Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
>>>
>>> Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
>>>
>>> If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
>>>
>>> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
>>>
>>> #!/bin/sh
>>>
>>> glmark2-es2-drm &
>>>
>>> while true;
>>> do
>>>     echo +10 > /sys/class/rtc/rtc0/wakealarm
>>>     echo mem > /sys/power/state
>>>     sleep 5
>>> done;
>>
>> Hm, that's unfortunate.
>>
>> I'm back from a two week vacation, but it looks like I won't have much
>> time available to look into this issue soon. It would be very helpful
>> if you could try to pinpoint the hang a bit more.  If you can reproduce
>> the hang with no_console_suspend you might be able to extract a bit
>> more info in which stage the hang happens (suspend, resume, TF-A, etc.)
>> If the hang is in the kernel you might be able to add some prints to
>> the suspend/resume paths to be able to track down the exact point of
>> the hang.
>>
>> I'm happy to look into the issue once it's better known where to look,
>> but I fear that I won't have time to do the above investigation myself
>> short term. Frieder, is this something you could help with over the
>> next few days?
> 
> I will see if I can find some time to track down the issue at least a little bit more. But I imagine it could get quite tedious if it takes up to several hours to reproduce the issue and I don't have much time to spare.
> 
> @Peng, @Adam and everyone else: Any chance you could setup a similar test and try to reproduce this?
> 
> On the other hand reboot cycle testing didn't show any lockup problems over more than 24 hours, so it seems like the issue is limited to resume.

I ran a few more suspend/resume cycles and watched the log. The first
2.5 hours nothing noteworthy happened, except that glmark2 crashed again
at some point.

Then suddenly the following lines were printed while suspending:

  imx-pgc imx-pgc-domain.6: failed to command PGC
  PM: dpm_run_callback(): platform_pm_suspend+0x0/0x78 returns -110
  imx8m-blk-ctrl 38330000.blk-ctrl: PM: failed to suspend: error -110
  PM: Some devices failed to suspend, or early wake event detected

After that, the suspending continues to fail with the following on each try:

  PM: dpm_run_callback(): platform_pm_suspend+0x0/0x78 returns -22
  imx8m-blk-ctrl 38330000.blk-ctrl: PM: failed to suspend: error -22
  PM: Some devices failed to suspend, or early wake event detected

So far I didn't run into a lockup again with this test, but I will
continue trying to reproduce it and retrieve more information.

Best regards
Frieder

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-08-30 22:06           ` Tim Harvey
@ 2021-09-01 10:30             ` Frieder Schrempf
  -1 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-09-01 10:30 UTC (permalink / raw)
  To: Tim Harvey, Lucas Stach
  Cc: Shawn Guo, Rob Herring, NXP Linux Team, Adam Ford, Peng Fan,
	Marek Vasut, Device Tree Mailing List, Linux ARM Mailing List,
	Sascha Hauer, patchwork-lst, Fabio Estevam

Hi Tim,

On 31.08.21 00:06, Tim Harvey wrote:
> On Mon, Aug 9, 2021 at 4:01 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>>
>> Hi Frieder,
>>
>> Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
>>> On 05.08.21 12:18, Frieder Schrempf wrote:
>>>> On 21.07.21 22:46, Lucas Stach wrote:
>>>>> Hi all,
>>>>>
>>>>> second revision of the GPC improvements and BLK_CTRL driver to make use
>>>>> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
>>>>> blurb from the v1 cover letter here, but if you are not familiar with
>>>>> i.MX8MM power domains, it may be worth a read.
>>>>>
>>>>> This 2nd revision fixes the DT bindings to be valid yaml, some small
>>>>> failure path issues and most importantly the interaction with system
>>>>> suspend/resume. With the previous version some of the power domains
>>>>> would not come up correctly after a suspend/resume cycle.
>>>>>
>>>>> Updated testing git trees here, disclaimer still applies:
>>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C35d8c33691eb4355196c08d96c0281b5%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637659580288796439%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=XrDOPLcL5D6PYt8ihbhURkuD9bzABOOfP6hJ5x341lM%3D&amp;reserved=0
>>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains-testing&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C35d8c33691eb4355196c08d96c0281b5%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637659580288796439%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=9J016OR46KgfdlM4pG%2F5rkO6pT%2FOBwgLTMRqF10it%2Fg%3D&amp;reserved=0
>>>>
>>>> I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
>>>>
>>>> I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
>>>>
>>>
>>> Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
>>>
>>> Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
>>>
>>> If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
>>>
>>> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
>>>
>>> #!/bin/sh
>>>
>>> glmark2-es2-drm &
>>>
>>> while true;
>>> do
>>>     echo +10 > /sys/class/rtc/rtc0/wakealarm
>>>     echo mem > /sys/power/state
>>>     sleep 5
>>> done;
>>
>> Hm, that's unfortunate.
>>
>> I'm back from a two week vacation, but it looks like I won't have much
>> time available to look into this issue soon. It would be very helpful
>> if you could try to pinpoint the hang a bit more.  If you can reproduce
>> the hang with no_console_suspend you might be able to extract a bit
>> more info in which stage the hang happens (suspend, resume, TF-A, etc.)
>> If the hang is in the kernel you might be able to add some prints to
>> the suspend/resume paths to be able to track down the exact point of
>> the hang.
>>
>> I'm happy to look into the issue once it's better known where to look,
>> but I fear that I won't have time to do the above investigation myself
>> short term. Frieder, is this something you could help with over the
>> next few days?
>>
> 
> Lucas / Frieder,
> 
> Can you update us on where you are at with this patch series? I fear
> we are going to go through another kernel release without IMX8MM
> blk-ctl support and all the things that depend on it such as
> USB/PCI/DSI/CSI/GPU/VPU. If there is some specific testing you need
> please let me know what I can do to help. I have a variety of IMX8MM
> hardware but not a lot of time or knowledge with regards to
> troubleshooting suspend/resume issues.

I try to help as good as I can, but unfortunately my time is very
limited and I didn't make much progress in investigating the issue(s) so
far.

If you could do some testing on your side, this would be very
appreciated. It would be good if you could setup a recent kernel with
Lucas' patchset applied and do some supsend/resume cycle testing as
described above. Use 'no_console_suspend' in the cmdline and look for
any error messages in the log or lockups of the device.

You probably also need some users for the PD or BLK-CTRL, like GPU, DSI,
USB, etc. (that's what I currently have enabled). You can find the tree
I'm currently using here:
https://github.com/fschrempf/linux/tree/next-ktn-pd-blk-ctl-lucas.

> Are the issues found a regression?

Regression compared to what? To the v1 patches? I don't think so.

We didn't have any stable solution for BLK-CTRL support so far and what
we have is probably not tested extensively, yet. So I guess it's not
really unexpected that there are still issues, but it's very frustrating
that after all the efforts, there maybe is still something in the HW
that doesn't behave as expected.

Best regards,
Frieder


^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-09-01 10:30             ` Frieder Schrempf
  0 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-09-01 10:30 UTC (permalink / raw)
  To: Tim Harvey, Lucas Stach
  Cc: Shawn Guo, Rob Herring, NXP Linux Team, Adam Ford, Peng Fan,
	Marek Vasut, Device Tree Mailing List, Linux ARM Mailing List,
	Sascha Hauer, patchwork-lst, Fabio Estevam

Hi Tim,

On 31.08.21 00:06, Tim Harvey wrote:
> On Mon, Aug 9, 2021 at 4:01 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>>
>> Hi Frieder,
>>
>> Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
>>> On 05.08.21 12:18, Frieder Schrempf wrote:
>>>> On 21.07.21 22:46, Lucas Stach wrote:
>>>>> Hi all,
>>>>>
>>>>> second revision of the GPC improvements and BLK_CTRL driver to make use
>>>>> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
>>>>> blurb from the v1 cover letter here, but if you are not familiar with
>>>>> i.MX8MM power domains, it may be worth a read.
>>>>>
>>>>> This 2nd revision fixes the DT bindings to be valid yaml, some small
>>>>> failure path issues and most importantly the interaction with system
>>>>> suspend/resume. With the previous version some of the power domains
>>>>> would not come up correctly after a suspend/resume cycle.
>>>>>
>>>>> Updated testing git trees here, disclaimer still applies:
>>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C35d8c33691eb4355196c08d96c0281b5%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637659580288796439%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=XrDOPLcL5D6PYt8ihbhURkuD9bzABOOfP6hJ5x341lM%3D&amp;reserved=0
>>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains-testing&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7C35d8c33691eb4355196c08d96c0281b5%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637659580288796439%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=9J016OR46KgfdlM4pG%2F5rkO6pT%2FOBwgLTMRqF10it%2Fg%3D&amp;reserved=0
>>>>
>>>> I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
>>>>
>>>> I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
>>>>
>>>
>>> Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
>>>
>>> Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
>>>
>>> If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
>>>
>>> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
>>>
>>> #!/bin/sh
>>>
>>> glmark2-es2-drm &
>>>
>>> while true;
>>> do
>>>     echo +10 > /sys/class/rtc/rtc0/wakealarm
>>>     echo mem > /sys/power/state
>>>     sleep 5
>>> done;
>>
>> Hm, that's unfortunate.
>>
>> I'm back from a two week vacation, but it looks like I won't have much
>> time available to look into this issue soon. It would be very helpful
>> if you could try to pinpoint the hang a bit more.  If you can reproduce
>> the hang with no_console_suspend you might be able to extract a bit
>> more info in which stage the hang happens (suspend, resume, TF-A, etc.)
>> If the hang is in the kernel you might be able to add some prints to
>> the suspend/resume paths to be able to track down the exact point of
>> the hang.
>>
>> I'm happy to look into the issue once it's better known where to look,
>> but I fear that I won't have time to do the above investigation myself
>> short term. Frieder, is this something you could help with over the
>> next few days?
>>
> 
> Lucas / Frieder,
> 
> Can you update us on where you are at with this patch series? I fear
> we are going to go through another kernel release without IMX8MM
> blk-ctl support and all the things that depend on it such as
> USB/PCI/DSI/CSI/GPU/VPU. If there is some specific testing you need
> please let me know what I can do to help. I have a variety of IMX8MM
> hardware but not a lot of time or knowledge with regards to
> troubleshooting suspend/resume issues.

I try to help as good as I can, but unfortunately my time is very
limited and I didn't make much progress in investigating the issue(s) so
far.

If you could do some testing on your side, this would be very
appreciated. It would be good if you could setup a recent kernel with
Lucas' patchset applied and do some supsend/resume cycle testing as
described above. Use 'no_console_suspend' in the cmdline and look for
any error messages in the log or lockups of the device.

You probably also need some users for the PD or BLK-CTRL, like GPU, DSI,
USB, etc. (that's what I currently have enabled). You can find the tree
I'm currently using here:
https://github.com/fschrempf/linux/tree/next-ktn-pd-blk-ctl-lucas.

> Are the issues found a regression?

Regression compared to what? To the v1 patches? I don't think so.

We didn't have any stable solution for BLK-CTRL support so far and what
we have is probably not tested extensively, yet. So I guess it's not
really unexpected that there are still issues, but it's very frustrating
that after all the efforts, there maybe is still something in the HW
that doesn't behave as expected.

Best regards,
Frieder


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-09-01 10:03             ` Frieder Schrempf
@ 2021-09-01 12:16               ` Frieder Schrempf
  -1 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-09-01 12:16 UTC (permalink / raw)
  To: Lucas Stach
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst, Shawn Guo, Rob Herring

On 01.09.21 12:03, Frieder Schrempf wrote:
> Hi Lucas,
> 
> On 09.08.21 13:50, Frieder Schrempf wrote:
>> On 09.08.21 13:01, Lucas Stach wrote:
>>> Hi Frieder,
>>>
>>> Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
>>>> On 05.08.21 12:18, Frieder Schrempf wrote:
>>>>> On 21.07.21 22:46, Lucas Stach wrote:
>>>>>> Hi all,
>>>>>>
>>>>>> second revision of the GPC improvements and BLK_CTRL driver to make use
>>>>>> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
>>>>>> blurb from the v1 cover letter here, but if you are not familiar with
>>>>>> i.MX8MM power domains, it may be worth a read.
>>>>>>
>>>>>> This 2nd revision fixes the DT bindings to be valid yaml, some small
>>>>>> failure path issues and most importantly the interaction with system
>>>>>> suspend/resume. With the previous version some of the power domains
>>>>>> would not come up correctly after a suspend/resume cycle.
>>>>>>
>>>>>> Updated testing git trees here, disclaimer still applies:
>>>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7Cbf3a4cacd1e047be747b08d96d39e713%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637660917728575954%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=0A7jRJH16d3T1S868RHg57csVuDUtgB3lNl2A3QZdus%3D&amp;reserved=0
>>>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains-testing&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7Cbf3a4cacd1e047be747b08d96d39e713%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637660917728575954%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=gC5jcC0w3VP4HiJYQMBWD%2FHQzU2rr7KjtGG82Snh4X0%3D&amp;reserved=0
>>>>>
>>>>> I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
>>>>>
>>>>> I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
>>>>>
>>>>
>>>> Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
>>>>
>>>> Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
>>>>
>>>> If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
>>>>
>>>> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
>>>>
>>>> #!/bin/sh
>>>>
>>>> glmark2-es2-drm &
>>>>
>>>> while true;
>>>> do
>>>>     echo +10 > /sys/class/rtc/rtc0/wakealarm
>>>>     echo mem > /sys/power/state
>>>>     sleep 5
>>>> done;
>>>
>>> Hm, that's unfortunate.
>>>
>>> I'm back from a two week vacation, but it looks like I won't have much
>>> time available to look into this issue soon. It would be very helpful
>>> if you could try to pinpoint the hang a bit more.  If you can reproduce
>>> the hang with no_console_suspend you might be able to extract a bit
>>> more info in which stage the hang happens (suspend, resume, TF-A, etc.)
>>> If the hang is in the kernel you might be able to add some prints to
>>> the suspend/resume paths to be able to track down the exact point of
>>> the hang.
>>>
>>> I'm happy to look into the issue once it's better known where to look,
>>> but I fear that I won't have time to do the above investigation myself
>>> short term. Frieder, is this something you could help with over the
>>> next few days?
>>
>> I will see if I can find some time to track down the issue at least a little bit more. But I imagine it could get quite tedious if it takes up to several hours to reproduce the issue and I don't have much time to spare.
>>
>> @Peng, @Adam and everyone else: Any chance you could setup a similar test and try to reproduce this?
>>
>> On the other hand reboot cycle testing didn't show any lockup problems over more than 24 hours, so it seems like the issue is limited to resume.
> 
> I ran a few more suspend/resume cycles and watched the log. The first
> 2.5 hours nothing noteworthy happened, except that glmark2 crashed again
> at some point.

Facepalm! Of course glmark2 didn't crash, it just doesn't loop endlessly
as I expected it to do, which totally makes sense for a benchmark. Using
--run-forever should do the trick.

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-09-01 12:16               ` Frieder Schrempf
  0 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-09-01 12:16 UTC (permalink / raw)
  To: Lucas Stach
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst, Shawn Guo, Rob Herring

On 01.09.21 12:03, Frieder Schrempf wrote:
> Hi Lucas,
> 
> On 09.08.21 13:50, Frieder Schrempf wrote:
>> On 09.08.21 13:01, Lucas Stach wrote:
>>> Hi Frieder,
>>>
>>> Am Donnerstag, dem 05.08.2021 um 20:56 +0200 schrieb Frieder Schrempf:
>>>> On 05.08.21 12:18, Frieder Schrempf wrote:
>>>>> On 21.07.21 22:46, Lucas Stach wrote:
>>>>>> Hi all,
>>>>>>
>>>>>> second revision of the GPC improvements and BLK_CTRL driver to make use
>>>>>> of all the power-domains on the i.MX8MM. I'm not going to repeat the full
>>>>>> blurb from the v1 cover letter here, but if you are not familiar with
>>>>>> i.MX8MM power domains, it may be worth a read.
>>>>>>
>>>>>> This 2nd revision fixes the DT bindings to be valid yaml, some small
>>>>>> failure path issues and most importantly the interaction with system
>>>>>> suspend/resume. With the previous version some of the power domains
>>>>>> would not come up correctly after a suspend/resume cycle.
>>>>>>
>>>>>> Updated testing git trees here, disclaimer still applies:
>>>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7Cbf3a4cacd1e047be747b08d96d39e713%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637660917728575954%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=0A7jRJH16d3T1S868RHg57csVuDUtgB3lNl2A3QZdus%3D&amp;reserved=0
>>>>>> https://eur04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Flst%2Flinux%2Flog%2F%3Fh%3Dimx8m-power-domains-testing&amp;data=04%7C01%7Cfrieder.schrempf%40kontron.de%7Cbf3a4cacd1e047be747b08d96d39e713%7C8c9d3c973fd941c8a2b1646f3942daf1%7C0%7C0%7C637660917728575954%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=gC5jcC0w3VP4HiJYQMBWD%2FHQzU2rr7KjtGG82Snh4X0%3D&amp;reserved=0
>>>>>
>>>>> I finally did some tests on my side using USB, GPU and DSI (no PCIe, VPU, CSI so far) and the results are promising. Thanks for the effort!
>>>>>
>>>>> I will try to run some more automated suspend/resume and reboot test cycles over the weekend and report the results here afterwards.
>>>>>
>>>>
>>>> Unfortunately I got some results sooner than I had hoped. I set up a simple loop to suspend/resume every few seconds and on the first run it took around 2-3 hours for the device to lock up on resume. On the second run it took less than half an hour. I had glmark2-es2-drm running in the background, but it looks like it crashed at some point before the lockup occurred.
>>>>
>>>> Of course this could also be unrelated and caused by some peripheral driver or something but the first suspicion is definitely the power domains.
>>>>
>>>> If you have any suggestions for which debug options to enable or where to add some printks, please let me know. If I do another run I would like to make sure that the resulting logs are helpful for debugging.
>>>>
>>>> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
>>>>
>>>> #!/bin/sh
>>>>
>>>> glmark2-es2-drm &
>>>>
>>>> while true;
>>>> do
>>>>     echo +10 > /sys/class/rtc/rtc0/wakealarm
>>>>     echo mem > /sys/power/state
>>>>     sleep 5
>>>> done;
>>>
>>> Hm, that's unfortunate.
>>>
>>> I'm back from a two week vacation, but it looks like I won't have much
>>> time available to look into this issue soon. It would be very helpful
>>> if you could try to pinpoint the hang a bit more.  If you can reproduce
>>> the hang with no_console_suspend you might be able to extract a bit
>>> more info in which stage the hang happens (suspend, resume, TF-A, etc.)
>>> If the hang is in the kernel you might be able to add some prints to
>>> the suspend/resume paths to be able to track down the exact point of
>>> the hang.
>>>
>>> I'm happy to look into the issue once it's better known where to look,
>>> but I fear that I won't have time to do the above investigation myself
>>> short term. Frieder, is this something you could help with over the
>>> next few days?
>>
>> I will see if I can find some time to track down the issue at least a little bit more. But I imagine it could get quite tedious if it takes up to several hours to reproduce the issue and I don't have much time to spare.
>>
>> @Peng, @Adam and everyone else: Any chance you could setup a similar test and try to reproduce this?
>>
>> On the other hand reboot cycle testing didn't show any lockup problems over more than 24 hours, so it seems like the issue is limited to resume.
> 
> I ran a few more suspend/resume cycles and watched the log. The first
> 2.5 hours nothing noteworthy happened, except that glmark2 crashed again
> at some point.

Facepalm! Of course glmark2 didn't crash, it just doesn't loop endlessly
as I expected it to do, which totally makes sense for a benchmark. Using
--run-forever should do the trick.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-09-01 10:03             ` Frieder Schrempf
@ 2021-09-02 10:25               ` Lucas Stach
  -1 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-09-02 10:25 UTC (permalink / raw)
  To: Frieder Schrempf
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst, Shawn Guo, Rob Herring

Hi Frieder,

Am Mittwoch, dem 01.09.2021 um 12:03 +0200 schrieb Frieder Schrempf:
[...]
> > > 
> > > > 
> > > > And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
> > > > 
> > > > #!/bin/sh
> > > > 
> > > > glmark2-es2-drm &
> > > > 
> > > > while true;
> > > > do
> > > >     echo +10 > /sys/class/rtc/rtc0/wakealarm
> > > >     echo mem > /sys/power/state
> > > >     sleep 5
> > > > done;
> > > 
> > > Hm, that's unfortunate.
> > > 
> > > I'm back from a two week vacation, but it looks like I won't have much
> > > time available to look into this issue soon. It would be very helpful
> > > if you could try to pinpoint the hang a bit more.  If you can reproduce
> > > the hang with no_console_suspend you might be able to extract a bit
> > > more info in which stage the hang happens (suspend, resume, TF-A, etc.)
> > > If the hang is in the kernel you might be able to add some prints to
> > > the suspend/resume paths to be able to track down the exact point of
> > > the hang.
> > > 
> > > I'm happy to look into the issue once it's better known where to look,
> > > but I fear that I won't have time to do the above investigation myself
> > > short term. Frieder, is this something you could help with over the
> > > next few days?
> > 
> > I will see if I can find some time to track down the issue at least a little bit more. But I imagine it could get quite tedious if it takes up to several hours to reproduce the issue and I don't have much time to spare.
> > 
> > @Peng, @Adam and everyone else: Any chance you could setup a similar test and try to reproduce this?
> > 
> > On the other hand reboot cycle testing didn't show any lockup problems over more than 24 hours, so it seems like the issue is limited to resume.
> 
> I ran a few more suspend/resume cycles and watched the log. The first
> 2.5 hours nothing noteworthy happened, except that glmark2 crashed again
> at some point.
> 
> Then suddenly the following lines were printed while suspending:
> 
>   imx-pgc imx-pgc-domain.6: failed to command PGC
>   PM: dpm_run_callback(): platform_pm_suspend+0x0/0x78 returns -110
>   imx8m-blk-ctrl 38330000.blk-ctrl: PM: failed to suspend: error -110
>   PM: Some devices failed to suspend, or early wake event detected
> 
> After that, the suspending continues to fail with the following on each try:
> 
>   PM: dpm_run_callback(): platform_pm_suspend+0x0/0x78 returns -22
>   imx8m-blk-ctrl 38330000.blk-ctrl: PM: failed to suspend: error -22
>   PM: Some devices failed to suspend, or early wake event detected
> 
> So far I didn't run into a lockup again with this test, but I will
> continue trying to reproduce it and retrieve more information.

If you run into this "failed to command PGC" state again, I would be
very interested in the GPC state there. You should be able to dump the
full register state from the GPC regmap in debugfs.

Regards,
Lucas


^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-09-02 10:25               ` Lucas Stach
  0 siblings, 0 replies; 136+ messages in thread
From: Lucas Stach @ 2021-09-02 10:25 UTC (permalink / raw)
  To: Frieder Schrempf
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst, Shawn Guo, Rob Herring

Hi Frieder,

Am Mittwoch, dem 01.09.2021 um 12:03 +0200 schrieb Frieder Schrempf:
[...]
> > > 
> > > > 
> > > > And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
> > > > 
> > > > #!/bin/sh
> > > > 
> > > > glmark2-es2-drm &
> > > > 
> > > > while true;
> > > > do
> > > >     echo +10 > /sys/class/rtc/rtc0/wakealarm
> > > >     echo mem > /sys/power/state
> > > >     sleep 5
> > > > done;
> > > 
> > > Hm, that's unfortunate.
> > > 
> > > I'm back from a two week vacation, but it looks like I won't have much
> > > time available to look into this issue soon. It would be very helpful
> > > if you could try to pinpoint the hang a bit more.  If you can reproduce
> > > the hang with no_console_suspend you might be able to extract a bit
> > > more info in which stage the hang happens (suspend, resume, TF-A, etc.)
> > > If the hang is in the kernel you might be able to add some prints to
> > > the suspend/resume paths to be able to track down the exact point of
> > > the hang.
> > > 
> > > I'm happy to look into the issue once it's better known where to look,
> > > but I fear that I won't have time to do the above investigation myself
> > > short term. Frieder, is this something you could help with over the
> > > next few days?
> > 
> > I will see if I can find some time to track down the issue at least a little bit more. But I imagine it could get quite tedious if it takes up to several hours to reproduce the issue and I don't have much time to spare.
> > 
> > @Peng, @Adam and everyone else: Any chance you could setup a similar test and try to reproduce this?
> > 
> > On the other hand reboot cycle testing didn't show any lockup problems over more than 24 hours, so it seems like the issue is limited to resume.
> 
> I ran a few more suspend/resume cycles and watched the log. The first
> 2.5 hours nothing noteworthy happened, except that glmark2 crashed again
> at some point.
> 
> Then suddenly the following lines were printed while suspending:
> 
>   imx-pgc imx-pgc-domain.6: failed to command PGC
>   PM: dpm_run_callback(): platform_pm_suspend+0x0/0x78 returns -110
>   imx8m-blk-ctrl 38330000.blk-ctrl: PM: failed to suspend: error -110
>   PM: Some devices failed to suspend, or early wake event detected
> 
> After that, the suspending continues to fail with the following on each try:
> 
>   PM: dpm_run_callback(): platform_pm_suspend+0x0/0x78 returns -22
>   imx8m-blk-ctrl 38330000.blk-ctrl: PM: failed to suspend: error -22
>   PM: Some devices failed to suspend, or early wake event detected
> 
> So far I didn't run into a lockup again with this test, but I will
> continue trying to reproduce it and retrieve more information.

If you run into this "failed to command PGC" state again, I would be
very interested in the GPC state there. You should be able to dump the
full register state from the GPC regmap in debugfs.

Regards,
Lucas


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
  2021-09-02 10:25               ` Lucas Stach
@ 2021-09-06  7:49                 ` Frieder Schrempf
  -1 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-09-06  7:49 UTC (permalink / raw)
  To: Lucas Stach
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst, Shawn Guo, Rob Herring

On 02.09.21 12:25, Lucas Stach wrote:
> Hi Frieder,
> 
> Am Mittwoch, dem 01.09.2021 um 12:03 +0200 schrieb Frieder Schrempf:
> [...]
>>>>
>>>>>
>>>>> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
>>>>>
>>>>> #!/bin/sh
>>>>>
>>>>> glmark2-es2-drm &
>>>>>
>>>>> while true;
>>>>> do
>>>>>     echo +10 > /sys/class/rtc/rtc0/wakealarm
>>>>>     echo mem > /sys/power/state
>>>>>     sleep 5
>>>>> done;
>>>>
>>>> Hm, that's unfortunate.
>>>>
>>>> I'm back from a two week vacation, but it looks like I won't have much
>>>> time available to look into this issue soon. It would be very helpful
>>>> if you could try to pinpoint the hang a bit more.  If you can reproduce
>>>> the hang with no_console_suspend you might be able to extract a bit
>>>> more info in which stage the hang happens (suspend, resume, TF-A, etc.)
>>>> If the hang is in the kernel you might be able to add some prints to
>>>> the suspend/resume paths to be able to track down the exact point of
>>>> the hang.
>>>>
>>>> I'm happy to look into the issue once it's better known where to look,
>>>> but I fear that I won't have time to do the above investigation myself
>>>> short term. Frieder, is this something you could help with over the
>>>> next few days?
>>>
>>> I will see if I can find some time to track down the issue at least a little bit more. But I imagine it could get quite tedious if it takes up to several hours to reproduce the issue and I don't have much time to spare.
>>>
>>> @Peng, @Adam and everyone else: Any chance you could setup a similar test and try to reproduce this?
>>>
>>> On the other hand reboot cycle testing didn't show any lockup problems over more than 24 hours, so it seems like the issue is limited to resume.
>>
>> I ran a few more suspend/resume cycles and watched the log. The first
>> 2.5 hours nothing noteworthy happened, except that glmark2 crashed again
>> at some point.
>>
>> Then suddenly the following lines were printed while suspending:
>>
>>   imx-pgc imx-pgc-domain.6: failed to command PGC
>>   PM: dpm_run_callback(): platform_pm_suspend+0x0/0x78 returns -110
>>   imx8m-blk-ctrl 38330000.blk-ctrl: PM: failed to suspend: error -110
>>   PM: Some devices failed to suspend, or early wake event detected
>>
>> After that, the suspending continues to fail with the following on each try:
>>
>>   PM: dpm_run_callback(): platform_pm_suspend+0x0/0x78 returns -22
>>   imx8m-blk-ctrl 38330000.blk-ctrl: PM: failed to suspend: error -22
>>   PM: Some devices failed to suspend, or early wake event detected
>>
>> So far I didn't run into a lockup again with this test, but I will
>> continue trying to reproduce it and retrieve more information.
> 
> If you run into this "failed to command PGC" state again, I would be
> very interested in the GPC state there. You should be able to dump the
> full register state from the GPC regmap in debugfs.

I tried to reproduce this with the same setup for several days now, but
I didn't run into this error again so far. It seems to be something that
occurs only very rarely.

I also got only a single lockup with this board and something like ~40 h
testing in total. On the other hand I have a different board (same
design) that shows the lockups much more often.

I hope I can provide more data soon, but I can't promise anything.

^ permalink raw reply	[flat|nested] 136+ messages in thread

* Re: [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver
@ 2021-09-06  7:49                 ` Frieder Schrempf
  0 siblings, 0 replies; 136+ messages in thread
From: Frieder Schrempf @ 2021-09-06  7:49 UTC (permalink / raw)
  To: Lucas Stach
  Cc: NXP Linux Team, Adam Ford, Peng Fan, Marek Vasut, devicetree,
	linux-arm-kernel, kernel, patchwork-lst, Shawn Guo, Rob Herring

On 02.09.21 12:25, Lucas Stach wrote:
> Hi Frieder,
> 
> Am Mittwoch, dem 01.09.2021 um 12:03 +0200 schrieb Frieder Schrempf:
> [...]
>>>>
>>>>>
>>>>> And I would appreciate if someone else could try to reproduce this problem on his/her side. I use this simple script for testing:
>>>>>
>>>>> #!/bin/sh
>>>>>
>>>>> glmark2-es2-drm &
>>>>>
>>>>> while true;
>>>>> do
>>>>>     echo +10 > /sys/class/rtc/rtc0/wakealarm
>>>>>     echo mem > /sys/power/state
>>>>>     sleep 5
>>>>> done;
>>>>
>>>> Hm, that's unfortunate.
>>>>
>>>> I'm back from a two week vacation, but it looks like I won't have much
>>>> time available to look into this issue soon. It would be very helpful
>>>> if you could try to pinpoint the hang a bit more.  If you can reproduce
>>>> the hang with no_console_suspend you might be able to extract a bit
>>>> more info in which stage the hang happens (suspend, resume, TF-A, etc.)
>>>> If the hang is in the kernel you might be able to add some prints to
>>>> the suspend/resume paths to be able to track down the exact point of
>>>> the hang.
>>>>
>>>> I'm happy to look into the issue once it's better known where to look,
>>>> but I fear that I won't have time to do the above investigation myself
>>>> short term. Frieder, is this something you could help with over the
>>>> next few days?
>>>
>>> I will see if I can find some time to track down the issue at least a little bit more. But I imagine it could get quite tedious if it takes up to several hours to reproduce the issue and I don't have much time to spare.
>>>
>>> @Peng, @Adam and everyone else: Any chance you could setup a similar test and try to reproduce this?
>>>
>>> On the other hand reboot cycle testing didn't show any lockup problems over more than 24 hours, so it seems like the issue is limited to resume.
>>
>> I ran a few more suspend/resume cycles and watched the log. The first
>> 2.5 hours nothing noteworthy happened, except that glmark2 crashed again
>> at some point.
>>
>> Then suddenly the following lines were printed while suspending:
>>
>>   imx-pgc imx-pgc-domain.6: failed to command PGC
>>   PM: dpm_run_callback(): platform_pm_suspend+0x0/0x78 returns -110
>>   imx8m-blk-ctrl 38330000.blk-ctrl: PM: failed to suspend: error -110
>>   PM: Some devices failed to suspend, or early wake event detected
>>
>> After that, the suspending continues to fail with the following on each try:
>>
>>   PM: dpm_run_callback(): platform_pm_suspend+0x0/0x78 returns -22
>>   imx8m-blk-ctrl 38330000.blk-ctrl: PM: failed to suspend: error -22
>>   PM: Some devices failed to suspend, or early wake event detected
>>
>> So far I didn't run into a lockup again with this test, but I will
>> continue trying to reproduce it and retrieve more information.
> 
> If you run into this "failed to command PGC" state again, I would be
> very interested in the GPC state there. You should be able to dump the
> full register state from the GPC regmap in debugfs.

I tried to reproduce this with the same setup for several days now, but
I didn't run into this error again so far. It seems to be something that
occurs only very rarely.

I also got only a single lockup with this board and something like ~40 h
testing in total. On the other hand I have a different board (same
design) that shows the lockups much more often.

I hope I can provide more data soon, but I can't promise anything.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 136+ messages in thread

end of thread, other threads:[~2021-09-06  7:53 UTC | newest]

Thread overview: 136+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-16 23:28 [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver Lucas Stach
2021-07-16 23:28 ` Lucas Stach
2021-07-16 23:29 ` [PATCH 01/17] Revert "soc: imx: gpcv2: move reset assert after requesting domain power up" Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 02/17] soc: imx: gpcv2: Turn domain->pgc into bitfield Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 03/17] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 04/17] soc: imx: gpcv2: add lockdep annotation Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 05/17] soc: imx: gpcv2: add domain option to keep domain clocks enabled Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 06/17] soc: imx: gpcv2: keep i.MX8M* bus " Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 07/17] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-19 13:47   ` Rob Herring
2021-07-19 13:47     ` Rob Herring
2021-07-16 23:29 ` [PATCH 08/17] dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 09/17] soc: imx: add i.MX8M blk-ctrl driver Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-19  6:12   ` Dan Carpenter
2021-07-19  6:12     ` Dan Carpenter
2021-07-19  9:11     ` Lucas Stach
2021-07-19  9:11       ` Lucas Stach
2021-07-16 23:29 ` [PATCH 10/17] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-19 13:47   ` Rob Herring
2021-07-19 13:47     ` Rob Herring
2021-07-16 23:29 ` [PATCH 11/17] dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 12/17] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 13/17] arm64: dts: imx8mm: add GPC node Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 14/17] arm64: dts: imx8mm: put USB controllers into power-domains Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 15/17] arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 16/17] arm64: dts: imx8mm: add VPU blk-ctrl Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-16 23:29 ` [PATCH 17/17] arm64: dts: imx8mm: add DISP blk-ctrl Lucas Stach
2021-07-16 23:29   ` Lucas Stach
2021-07-19 12:53 ` [PATCH 00/17] i.MX8MM GPC improvements and BLK_CTRL driver Peng Fan
2021-07-19 12:53   ` Peng Fan
2021-07-19 16:56   ` Lucas Stach
2021-07-19 16:56     ` Lucas Stach
2021-07-21 11:21     ` Lucas Stach
2021-07-21 11:21       ` Lucas Stach
2021-07-21 20:46 ` [PATCH v2 00/18] " Lucas Stach
2021-07-21 20:46   ` Lucas Stach
2021-07-21 20:46   ` [PATCH v2 01/18] Revert "soc: imx: gpcv2: move reset assert after requesting domain power up" Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-08-05  9:37     ` Peng Fan
2021-08-05  9:37       ` Peng Fan
2021-07-21 20:46   ` [PATCH v2 02/18] soc: imx: gpcv2: Turn domain->pgc into bitfield Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-08-05  9:37     ` Peng Fan
2021-08-05  9:37       ` Peng Fan
2021-07-21 20:46   ` [PATCH v2 03/18] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-08-05  9:37     ` Peng Fan
2021-08-05  9:37       ` Peng Fan
2021-07-21 20:46   ` [PATCH v2 04/18] soc: imx: gpcv2: add lockdep annotation Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-08-05  9:38     ` Peng Fan
2021-08-05  9:38       ` Peng Fan
2021-07-21 20:46   ` [PATCH v2 05/18] soc: imx: gpcv2: add domain option to keep domain clocks enabled Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-08-05  9:38     ` Peng Fan
2021-08-05  9:38       ` Peng Fan
2021-07-21 20:46   ` [PATCH v2 06/18] soc: imx: gpcv2: keep i.MX8M* bus " Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-08-05  9:39     ` Peng Fan
2021-08-05  9:39       ` Peng Fan
2021-07-21 20:46   ` [PATCH v2 07/18] soc: imx: gpcv2: support system suspend/resume Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-08-05  9:47     ` Peng Fan
2021-08-05  9:47       ` Peng Fan
2021-07-21 20:46   ` [PATCH v2 08/18] dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrl Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-07-22 14:37     ` Rob Herring
2021-07-22 14:37       ` Rob Herring
2021-07-21 20:46   ` [PATCH v2 09/18] dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-07-21 20:46   ` [PATCH v2 10/18] soc: imx: add i.MX8M blk-ctrl driver Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-08-05  9:54     ` Peng Fan
2021-08-05  9:54       ` Peng Fan
2021-07-21 20:46   ` [PATCH v2 11/18] dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrl Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-07-22 14:37     ` Rob Herring
2021-07-22 14:37       ` Rob Herring
2021-07-21 20:46   ` [PATCH v2 12/18] dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-07-21 20:46   ` [PATCH v2 13/18] soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-08-05  9:53     ` Peng Fan
2021-08-05  9:53       ` Peng Fan
2021-07-21 20:46   ` [PATCH v2 14/18] arm64: dts: imx8mm: add GPC node Lucas Stach
2021-07-21 20:46     ` Lucas Stach
2021-08-05  9:54     ` Peng Fan
2021-08-05  9:54       ` Peng Fan
2021-07-21 20:47   ` [PATCH v2 15/18] arm64: dts: imx8mm: put USB controllers into power-domains Lucas Stach
2021-07-21 20:47     ` Lucas Stach
2021-07-21 20:47   ` [PATCH v2 16/18] arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core Lucas Stach
2021-07-21 20:47     ` Lucas Stach
2021-07-21 20:47   ` [PATCH v2 17/18] arm64: dts: imx8mm: add VPU blk-ctrl Lucas Stach
2021-07-21 20:47     ` Lucas Stach
2021-07-21 20:47   ` [PATCH v2 18/18] arm64: dts: imx8mm: add DISP blk-ctrl Lucas Stach
2021-07-21 20:47     ` Lucas Stach
2021-08-05  9:35   ` [PATCH v2 00/18] i.MX8MM GPC improvements and BLK_CTRL driver Peng Fan (OSS)
2021-08-05  9:35     ` Peng Fan (OSS)
2021-08-05 10:18   ` Frieder Schrempf
2021-08-05 10:18     ` Frieder Schrempf
2021-08-05 18:56     ` Frieder Schrempf
2021-08-05 18:56       ` Frieder Schrempf
2021-08-09 11:01       ` Lucas Stach
2021-08-09 11:01         ` Lucas Stach
2021-08-09 11:50         ` Frieder Schrempf
2021-08-09 11:50           ` Frieder Schrempf
2021-08-09 18:51           ` Adam Ford
2021-08-09 18:51             ` Adam Ford
2021-09-01 10:03           ` Frieder Schrempf
2021-09-01 10:03             ` Frieder Schrempf
2021-09-01 12:16             ` Frieder Schrempf
2021-09-01 12:16               ` Frieder Schrempf
2021-09-02 10:25             ` Lucas Stach
2021-09-02 10:25               ` Lucas Stach
2021-09-06  7:49               ` Frieder Schrempf
2021-09-06  7:49                 ` Frieder Schrempf
2021-08-30 22:06         ` Tim Harvey
2021-08-30 22:06           ` Tim Harvey
2021-09-01 10:30           ` Frieder Schrempf
2021-09-01 10:30             ` Frieder Schrempf

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