* [PATCH] x86/cpuid: Advertise no-lmsle unilaterally to hvm guests
@ 2021-04-12 10:22 Andrew Cooper
2021-04-12 10:48 ` Jan Beulich
0 siblings, 1 reply; 4+ messages in thread
From: Andrew Cooper @ 2021-04-12 10:22 UTC (permalink / raw)
To: Xen-devel; +Cc: Andrew Cooper, Jan Beulich, Roger Pau Monné, Wei Liu
While part of the original AMD64 spec, Long Mode Segment Limit Enable was a
feature not picked up by Intel, and therefore didn't see much adoption in
software. AMD have finally dropped the feature from hardware, and allocated a
CPUID bit to indicate its absence.
Xen has never supported the feature for guests, even when running on capable
hardware, so advertise the feature's absence unilaterally.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Roger Pau Monné <roger.pau@citrix.com>
CC: Wei Liu <wl@xen.org>
There is nothing specifically wrong with exposing this bit to PV guests, but
the PV ABI doesn't include a working concept of MSR_EFER in the first place,
so exposing it to PV guests seems somewhat out-of-place.
---
tools/libs/light/libxl_cpuid.c | 1 +
tools/misc/xen-cpuid.c | 1 +
xen/arch/x86/cpuid.c | 6 ++++++
xen/include/public/arch-x86/cpufeatureset.h | 1 +
4 files changed, 9 insertions(+)
diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c
index 289c59c742..be0bd81a9b 100644
--- a/tools/libs/light/libxl_cpuid.c
+++ b/tools/libs/light/libxl_cpuid.c
@@ -270,6 +270,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
{"rstr-fp-err-ptrs", 0x80000008, NA, CPUID_REG_EBX, 2, 1},
{"wbnoinvd", 0x80000008, NA, CPUID_REG_EBX, 9, 1},
{"ibpb", 0x80000008, NA, CPUID_REG_EBX, 12, 1},
+ {"no-lmsle", 0x80000008, NA, CPUID_REG_EBX, 20, 1},
{"ppin", 0x80000008, NA, CPUID_REG_EBX, 23, 1},
{"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8},
diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index 2d04162d8d..1a82089463 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -152,6 +152,7 @@ static const char *const str_e8b[32] =
[12] = "ibpb",
+ [20] = "no-lmsle",
/* [22] */ [23] = "ppin",
};
diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index 18b08d9b87..3ed0feac4a 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -456,6 +456,12 @@ static void __init calculate_hvm_max_policy(void)
__set_bit(X86_FEATURE_X2APIC, hvm_featureset);
/*
+ * We don't support EFER.LMSLE at all. AMD has dropped the feature from
+ * hardware and allocated a CPUID bit to indicate its absence.
+ */
+ __set_bit(X86_FEATURE_NO_LMSLE, hvm_featureset);
+
+ /*
* On AMD, PV guests are entirely unable to use SYSENTER as Xen runs in
* long mode (and init_amd() has cleared it out of host capabilities), but
* HVM guests are able if running in protected mode.
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index a501479820..0a4690decc 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -255,6 +255,7 @@ XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */
XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always saves/restores FPU Error pointers */
XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */
XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */
+XEN_CPUFEATURE(NO_LMSLE, 8*32+20) /*S EFER.LMSLE no longer supported. */
XEN_CPUFEATURE(AMD_PPIN, 8*32+23) /* Protected Processor Inventory Number */
/* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
--
2.11.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] x86/cpuid: Advertise no-lmsle unilaterally to hvm guests
2021-04-12 10:22 [PATCH] x86/cpuid: Advertise no-lmsle unilaterally to hvm guests Andrew Cooper
@ 2021-04-12 10:48 ` Jan Beulich
2021-04-12 11:39 ` Andrew Cooper
0 siblings, 1 reply; 4+ messages in thread
From: Jan Beulich @ 2021-04-12 10:48 UTC (permalink / raw)
To: Andrew Cooper; +Cc: Roger Pau Monné, Wei Liu, Xen-devel
On 12.04.2021 12:22, Andrew Cooper wrote:
> --- a/xen/arch/x86/cpuid.c
> +++ b/xen/arch/x86/cpuid.c
> @@ -456,6 +456,12 @@ static void __init calculate_hvm_max_policy(void)
> __set_bit(X86_FEATURE_X2APIC, hvm_featureset);
>
> /*
> + * We don't support EFER.LMSLE at all. AMD has dropped the feature from
> + * hardware and allocated a CPUID bit to indicate its absence.
> + */
> + __set_bit(X86_FEATURE_NO_LMSLE, hvm_featureset);
Why only for HVM? And shouldn't the LM: entry in the dependencies
table be adjusted such that !LM implies this bit clear?
Jan
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] x86/cpuid: Advertise no-lmsle unilaterally to hvm guests
2021-04-12 10:48 ` Jan Beulich
@ 2021-04-12 11:39 ` Andrew Cooper
2021-04-12 11:52 ` Jan Beulich
0 siblings, 1 reply; 4+ messages in thread
From: Andrew Cooper @ 2021-04-12 11:39 UTC (permalink / raw)
To: Jan Beulich; +Cc: Roger Pau Monné, Wei Liu, Xen-devel
On 12/04/2021 11:48, Jan Beulich wrote:
> On 12.04.2021 12:22, Andrew Cooper wrote:
>> --- a/xen/arch/x86/cpuid.c
>> +++ b/xen/arch/x86/cpuid.c
>> @@ -456,6 +456,12 @@ static void __init calculate_hvm_max_policy(void)
>> __set_bit(X86_FEATURE_X2APIC, hvm_featureset);
>>
>> /*
>> + * We don't support EFER.LMSLE at all. AMD has dropped the feature from
>> + * hardware and allocated a CPUID bit to indicate its absence.
>> + */
>> + __set_bit(X86_FEATURE_NO_LMSLE, hvm_featureset);
> Why only for HVM?
That was discussed.
> And shouldn't the LM: entry in the dependencies
> table be adjusted such that !LM implies this bit clear?
Probably.
~Andrew
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] x86/cpuid: Advertise no-lmsle unilaterally to hvm guests
2021-04-12 11:39 ` Andrew Cooper
@ 2021-04-12 11:52 ` Jan Beulich
0 siblings, 0 replies; 4+ messages in thread
From: Jan Beulich @ 2021-04-12 11:52 UTC (permalink / raw)
To: Andrew Cooper; +Cc: Roger Pau Monné, Wei Liu, Xen-devel
On 12.04.2021 13:39, Andrew Cooper wrote:
> On 12/04/2021 11:48, Jan Beulich wrote:
>> On 12.04.2021 12:22, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/cpuid.c
>>> +++ b/xen/arch/x86/cpuid.c
>>> @@ -456,6 +456,12 @@ static void __init calculate_hvm_max_policy(void)
>>> __set_bit(X86_FEATURE_X2APIC, hvm_featureset);
>>>
>>> /*
>>> + * We don't support EFER.LMSLE at all. AMD has dropped the feature from
>>> + * hardware and allocated a CPUID bit to indicate its absence.
>>> + */
>>> + __set_bit(X86_FEATURE_NO_LMSLE, hvm_featureset);
>> Why only for HVM?
>
> That was discussed.
Oh, in a post-commit-message remark which I did manage to skip over.
Would you mind making this part of the commit message?
Jan
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-04-12 11:52 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2021-04-12 10:22 [PATCH] x86/cpuid: Advertise no-lmsle unilaterally to hvm guests Andrew Cooper
2021-04-12 10:48 ` Jan Beulich
2021-04-12 11:39 ` Andrew Cooper
2021-04-12 11:52 ` Jan Beulich
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