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([2607:fb90:806a:923e:f0df:3e3a:c73f:64e4]) by smtp.gmail.com with ESMTPSA id 12-20020a63010c000000b003c14af50624sm284337pgb.60.2022.05.10.16.56.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 May 2022 16:56:56 -0700 (PDT) Message-ID: Date: Tue, 10 May 2022 16:56:52 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH v2 1/3] target/ppc: Fix FPSCR.FI bit being cleared when it shouldn't Content-Language: en-US To: =?UTF-8?Q?V=c3=adctor_Colombo?= , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org References: <20220510204610.100867-1-victor.colombo@eldorado.org.br> <20220510204610.100867-2-victor.colombo@eldorado.org.br> From: Richard Henderson In-Reply-To: <20220510204610.100867-2-victor.colombo@eldorado.org.br> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/10/22 13:46, Víctor Colombo wrote: > The FI bit in FPSCR is said to be a non-sticky bit on Power ISA. > One could think this means that, if an instruction is said to modify > the FPSCR register, the bit FI should be cleared. This is what QEMU > does today. > > However, the following inconsistency was found when comparing results > from the hardware (tested on both a Power 9 processor and in > Power 10 Mambo): > > (FI bit is set before the execution of the instruction) > Hardware: xscmpeqdp(0xff..ff, 0xff..ff) = FI: SET -> SET > QEMU: xscmpeqdp(0xff..ff, 0xff..ff) = FI: SET -> CLEARED > > This is happening to multiple instructions in the vsx > implementations. As the FI bit is non-sticky, one could think that > xscmpeqdp, a instruction the ISA states doesn't change FI bit, should > result in a cleared FI. However, this is not happening on hardware. > > An investigation resulted in the following conclusion: > If the ISA does not list the FI bit as altered for a particular > instruction, then it should be kept as it was before the instruction. > > QEMU is not following this behavior. Affected instructions include: > - xv* (all vsx-vector instructions); > - xscmp*, xsmax*, xsmin*; > - xstdivdp and similars; > (to identify the affected instructions, just search in the ISA for > the instructions that does not list FI in "Special Registers Altered") > > Most instructions use the function do_float_check_status() to commit > changes in the inexact flag. So the fix is to add a parameter to it > that will control if the bit FI should be changed or not. > All users of do_float_check_status() are then modified to provide this > argument, controlling if that specific instruction changes bit FI or > not. > Some macro helpers are responsible for both instructions that change > and instructions that aren't suposed to change FI. This seems to always > overlap with the sfprf flag. So, reuse this flag for this purpose when > applicable. > > Signed-off-by: Víctor Colombo > > --- > > v2: > - move the FI change from float_inexact_excp to do_float_check_status > - sfprf will be renamed to sfifprf in another patch, as suggested by > Richard > --- > target/ppc/cpu.h | 2 + > target/ppc/fpu_helper.c | 122 +++++++++++++++++++++------------------- > 2 files changed, 66 insertions(+), 58 deletions(-) Reviewed-by: Richard Henderson r~