From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Fri, 8 May 2020 13:57:07 +0200
Subject: [PATCH] imx8mp_evk: Make SPL binary size smaller
In-Reply-To: <CAOMZO5BybinT-mz_KKZ-XsVn72Li5gjGqGnDQiiCR3AYZEKxdQ@mail.gmail.com>
References: <20200507120029.3172-1-festevam@gmail.com>
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 <CAOMZO5DwG6=MPUpuxB6uXGyudMUukRUp8z8WLjhZH=BkaaEUnQ@mail.gmail.com>
 <CAOMZO5B+dGKbO0hABH3oDX-VamngbA18LHJYDP6iG4fGti=yNw@mail.gmail.com>
 <CAOMZO5BybinT-mz_KKZ-XsVn72Li5gjGqGnDQiiCR3AYZEKxdQ@mail.gmail.com>
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On 5/8/20 1:49 PM, Fabio Estevam wrote:
> On Fri, May 8, 2020 at 1:53 AM Fabio Estevam <festevam@gmail.com> wrote:
>>
>> Hi Marek,
>>
>> On Thu, May 7, 2020 at 11:56 PM Fabio Estevam <festevam@gmail.com> wrote:
>>
>>> I will activate them on SPL tomorrow.
>>
>> After activating the SPL clocks I see:
>>
>>  clk          69  [   ]   imx_clk_gate2         |   |
>> `-- dram1_root_clk
>>
>> The dram1_root_clk is not getting turned on.
> 
> Looks at the iMX8MM EVK log:
> https://pastebin.com/raw/XVc6AAvr
> 
> It also has:
> 
> [   ]   clk_gate              |   |       `-- dram_pll_out
> 
> So it seems the problem is somewhere else.

Maybe you also need entries like
126dcc925d ("ARM: imx: imx8mm: Add missing clock entries for FEC clock")
for MX8MP ?