From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id C56FAC433F5 for ; Tue, 25 Jan 2022 10:57:55 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 1080041173; Tue, 25 Jan 2022 05:57:55 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CEl-IrJtU4Vc; Tue, 25 Jan 2022 05:57:53 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id B9CC349AF7; Tue, 25 Jan 2022 05:57:53 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 0F68141173 for ; Tue, 25 Jan 2022 05:57:53 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id c-50uwPP1C5Y for ; Tue, 25 Jan 2022 05:57:51 -0500 (EST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id A2AE340B85 for ; Tue, 25 Jan 2022 05:57:51 -0500 (EST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1E2551FB; Tue, 25 Jan 2022 02:57:51 -0800 (PST) Received: from [10.57.86.86] (unknown [10.57.86.86]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A2A303F7D8; Tue, 25 Jan 2022 02:57:48 -0800 (PST) Message-ID: Date: Tue, 25 Jan 2022 10:57:47 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v8 01/38] arm64: cpufeature: Always specify and use a field width for capabilities To: Mark Brown , Catalin Marinas , Will Deacon , Marc Zyngier , Shuah Khan , Shuah Khan References: <20220125001114.193425-1-broonie@kernel.org> <20220125001114.193425-2-broonie@kernel.org> From: Suzuki K Poulose In-Reply-To: <20220125001114.193425-2-broonie@kernel.org> Cc: Basant Kumar Dwivedi , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Alan Hayward , kvmarm@lists.cs.columbia.edu, Salil Akerkar X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On 25/01/2022 00:10, Mark Brown wrote: > Since all the fields in the main ID registers are 4 bits wide we have up > until now not bothered specifying the width in the code. Since we now > wish to use this mechanism to enumerate features from the floating point > feature registers which do not follow this pattern add a width to the > table. This means updating all the existing table entries but makes it > less likely that we run into issues in future due to implicitly assuming > a 4 bit width. > > Signed-off-by: Mark Brown > Cc: Suzuki K Poulose > --- > arch/arm64/include/asm/cpufeature.h | 1 + > arch/arm64/kernel/cpufeature.c | 167 +++++++++++++++++----------- > 2 files changed, 102 insertions(+), 66 deletions(-) > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index ef6be92b1921..2728abd9cae4 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -356,6 +356,7 @@ struct arm64_cpu_capabilities { > struct { /* Feature register checking */ > u32 sys_reg; > u8 field_pos; > + u8 field_width; > u8 min_field_value; > u8 hwcap_type; > bool sign; > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index a46ab3b1c4d5..d9f09e40aaf6 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1307,7 +1307,9 @@ u64 __read_sysreg_by_encoding(u32 sys_id) > static bool > feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) > { > - int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); > + int val = cpuid_feature_extract_field_width(reg, entry->field_pos, > + entry->field_width, > + entry->sign); > Could we do something like : + int val = cpuid_feature_extract_field_width(reg, entry->field_pos, entry->field_width ? : 4, .. ); and leave the existing structures as they are ? > return val >= entry->min_field_value; > } > @@ -1952,6 +1954,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { There is arm64_errata[] array in cpu_errata.c. So, if we use the above proposal we could leave things unchanged for all existing uses. > .matches = has_cpuid_feature, > .sys_reg = SYS_ID_AA64MMFR0_EL1, > .field_pos = ID_AA64MMFR0_ECV_SHIFT, > + .field_width = 4, > .sign = FTR_UNSIGNED, > .min_field_value = 1, > }, ... > -#define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ > +#define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ > .matches = has_cpuid_feature, \ > .sys_reg = reg, \ > .field_pos = field, \ > + .field_width = width, \ > .sign = s, \ > .min_field_value = min_value, And that could avoid these changes too. We could add : #define HWCAP_CPUID_MATCH_WIDTH(...) when/if we need one, which sets the width. Cheers Suzuki _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2B5BBC433EF for ; Tue, 25 Jan 2022 10:59:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XJXHzHIoezlWXFRFlaVFGYiLxr280aRVVBESVZGfric=; b=Pn8Z4NmbjSfZdX E/Bq6wpFxL6qYaOkD0t52JCTk6udMnhh05MDNWJXiBFe22IkKCWGSAFParHen9SIdNr8Jh7jIktTC zQ3CVjI0nKU/13OlN81J9EMCyfQ+CXJ0F8yTR2OBJ9FlRtVKnMaNTAJ6BAJF2FJgncPO3DoGMeLTu 8UR7zP3wXYwjSOdjrOJrrRNm7ncNq2X/AhWovVngr8K0Zip5Ll27756u0mDWebf0O0Su0ijQ45MA/ tHokeA5TRtGHmGS/oD+0CPO3EFrHWnJyi/I+JzqWXGjiLTpx44M3gCgzls1h65N/9nfQuUqq4Lfag zotgqRstQ0iOQykbl1RA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCJWR-007YAp-QQ; Tue, 25 Jan 2022 10:58:00 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCJWM-007Y8a-Lf for linux-arm-kernel@lists.infradead.org; Tue, 25 Jan 2022 10:57:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1E2551FB; Tue, 25 Jan 2022 02:57:51 -0800 (PST) Received: from [10.57.86.86] (unknown [10.57.86.86]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A2A303F7D8; Tue, 25 Jan 2022 02:57:48 -0800 (PST) Message-ID: Date: Tue, 25 Jan 2022 10:57:47 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v8 01/38] arm64: cpufeature: Always specify and use a field width for capabilities To: Mark Brown , Catalin Marinas , Will Deacon , Marc Zyngier , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Salil Akerkar , Basant Kumar Dwivedi , Szabolcs Nagy , James Morse , Alexandru Elisei , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, kvmarm@lists.cs.columbia.edu References: <20220125001114.193425-1-broonie@kernel.org> <20220125001114.193425-2-broonie@kernel.org> From: Suzuki K Poulose In-Reply-To: <20220125001114.193425-2-broonie@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_025754_882622_9E43C0B9 X-CRM114-Status: GOOD ( 21.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 25/01/2022 00:10, Mark Brown wrote: > Since all the fields in the main ID registers are 4 bits wide we have up > until now not bothered specifying the width in the code. Since we now > wish to use this mechanism to enumerate features from the floating point > feature registers which do not follow this pattern add a width to the > table. This means updating all the existing table entries but makes it > less likely that we run into issues in future due to implicitly assuming > a 4 bit width. > > Signed-off-by: Mark Brown > Cc: Suzuki K Poulose > --- > arch/arm64/include/asm/cpufeature.h | 1 + > arch/arm64/kernel/cpufeature.c | 167 +++++++++++++++++----------- > 2 files changed, 102 insertions(+), 66 deletions(-) > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index ef6be92b1921..2728abd9cae4 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -356,6 +356,7 @@ struct arm64_cpu_capabilities { > struct { /* Feature register checking */ > u32 sys_reg; > u8 field_pos; > + u8 field_width; > u8 min_field_value; > u8 hwcap_type; > bool sign; > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index a46ab3b1c4d5..d9f09e40aaf6 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1307,7 +1307,9 @@ u64 __read_sysreg_by_encoding(u32 sys_id) > static bool > feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) > { > - int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); > + int val = cpuid_feature_extract_field_width(reg, entry->field_pos, > + entry->field_width, > + entry->sign); > Could we do something like : + int val = cpuid_feature_extract_field_width(reg, entry->field_pos, entry->field_width ? : 4, .. ); and leave the existing structures as they are ? > return val >= entry->min_field_value; > } > @@ -1952,6 +1954,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { There is arm64_errata[] array in cpu_errata.c. So, if we use the above proposal we could leave things unchanged for all existing uses. > .matches = has_cpuid_feature, > .sys_reg = SYS_ID_AA64MMFR0_EL1, > .field_pos = ID_AA64MMFR0_ECV_SHIFT, > + .field_width = 4, > .sign = FTR_UNSIGNED, > .min_field_value = 1, > }, ... > -#define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ > +#define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ > .matches = has_cpuid_feature, \ > .sys_reg = reg, \ > .field_pos = field, \ > + .field_width = width, \ > .sign = s, \ > .min_field_value = min_value, And that could avoid these changes too. We could add : #define HWCAP_CPUID_MATCH_WIDTH(...) when/if we need one, which sets the width. Cheers Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFD4FC433F5 for ; Tue, 25 Jan 2022 11:00:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379664AbiAYK74 (ORCPT ); Tue, 25 Jan 2022 05:59:56 -0500 Received: from foss.arm.com ([217.140.110.172]:34830 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379826AbiAYK5y (ORCPT ); Tue, 25 Jan 2022 05:57:54 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1E2551FB; Tue, 25 Jan 2022 02:57:51 -0800 (PST) Received: from [10.57.86.86] (unknown [10.57.86.86]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A2A303F7D8; Tue, 25 Jan 2022 02:57:48 -0800 (PST) Message-ID: Date: Tue, 25 Jan 2022 10:57:47 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v8 01/38] arm64: cpufeature: Always specify and use a field width for capabilities To: Mark Brown , Catalin Marinas , Will Deacon , Marc Zyngier , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Salil Akerkar , Basant Kumar Dwivedi , Szabolcs Nagy , James Morse , Alexandru Elisei , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, kvmarm@lists.cs.columbia.edu References: <20220125001114.193425-1-broonie@kernel.org> <20220125001114.193425-2-broonie@kernel.org> From: Suzuki K Poulose In-Reply-To: <20220125001114.193425-2-broonie@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org On 25/01/2022 00:10, Mark Brown wrote: > Since all the fields in the main ID registers are 4 bits wide we have up > until now not bothered specifying the width in the code. Since we now > wish to use this mechanism to enumerate features from the floating point > feature registers which do not follow this pattern add a width to the > table. This means updating all the existing table entries but makes it > less likely that we run into issues in future due to implicitly assuming > a 4 bit width. > > Signed-off-by: Mark Brown > Cc: Suzuki K Poulose > --- > arch/arm64/include/asm/cpufeature.h | 1 + > arch/arm64/kernel/cpufeature.c | 167 +++++++++++++++++----------- > 2 files changed, 102 insertions(+), 66 deletions(-) > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index ef6be92b1921..2728abd9cae4 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -356,6 +356,7 @@ struct arm64_cpu_capabilities { > struct { /* Feature register checking */ > u32 sys_reg; > u8 field_pos; > + u8 field_width; > u8 min_field_value; > u8 hwcap_type; > bool sign; > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index a46ab3b1c4d5..d9f09e40aaf6 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1307,7 +1307,9 @@ u64 __read_sysreg_by_encoding(u32 sys_id) > static bool > feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) > { > - int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); > + int val = cpuid_feature_extract_field_width(reg, entry->field_pos, > + entry->field_width, > + entry->sign); > Could we do something like : + int val = cpuid_feature_extract_field_width(reg, entry->field_pos, entry->field_width ? : 4, .. ); and leave the existing structures as they are ? > return val >= entry->min_field_value; > } > @@ -1952,6 +1954,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { There is arm64_errata[] array in cpu_errata.c. So, if we use the above proposal we could leave things unchanged for all existing uses. > .matches = has_cpuid_feature, > .sys_reg = SYS_ID_AA64MMFR0_EL1, > .field_pos = ID_AA64MMFR0_ECV_SHIFT, > + .field_width = 4, > .sign = FTR_UNSIGNED, > .min_field_value = 1, > }, ... > -#define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ > +#define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ > .matches = has_cpuid_feature, \ > .sys_reg = reg, \ > .field_pos = field, \ > + .field_width = width, \ > .sign = s, \ > .min_field_value = min_value, And that could avoid these changes too. We could add : #define HWCAP_CPUID_MATCH_WIDTH(...) when/if we need one, which sets the width. Cheers Suzuki