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From: Luca Ceresoli <luca@lucaceresoli.net>
To: Stephen Boyd <sboyd@kernel.org>, linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>,
	linux-kernel@vger.kernel.org, Adam Ford <aford173@gmail.com>
Subject: Re: [PATCH RESEND] clk: vc5: fix output disabling when enabling a FOD
Date: Thu, 3 Jun 2021 23:06:30 +0200	[thread overview]
Message-ID: <ee4ff8b3-ee57-3b45-7e9c-46fb67cd0305@lucaceresoli.net> (raw)
In-Reply-To: <162275083380.1835121.17366140869706759167@swboyd.mtv.corp.google.com>

Hi,

On 03/06/21 22:07, Stephen Boyd wrote:
> Quoting Luca Ceresoli (2021-06-03 01:44:57)
>> Hi Stephen,
>>
>> On 02/06/21 10:00, Stephen Boyd wrote:
>>> Quoting Luca Ceresoli (2021-05-27 14:16:47)
>>>> On 5P49V6965, when an output is enabled we enable the corresponding
>>>> FOD. When this happens for the first time, and specifically when writing
>>>> register VC5_OUT_DIV_CONTROL in vc5_clk_out_prepare(), all other outputs
>>>> are stopped for a short time and then restarted.
>>>>
>>>> According to Renesas support this is intended: "The reason for that is VC6E
>>>> has synced up all output function".
>>>>
>>>> This behaviour can be disabled at least on VersaClock 6E devices, of which
>>>> only the 5P49V6965 is currently implemented by this driver. This requires
>>>> writing bit 7 (bypass_sync{1..4}) in register 0x20..0x50.  Those registers
>>>> are named "Unused Factory Reserved Register", and the bits are documented
>>>> as "Skip VDDO<N> verification", which does not clearly explain the relation
>>>> to FOD sync. However according to Renesas support as well as my testing
>>>> setting this bit does prevent disabling of all clock outputs when enabling
>>>> a FOD.
>>>>
>>>> See "VersaClock ® 6E Family Register Descriptions and Programming Guide"
>>>> (August 30, 2018), Table 116 "Power Up VDD check", page 58:
>>>> https://www.renesas.com/us/en/document/mau/versaclock-6e-family-register-descriptions-and-programming-guide
>>>>
>>>> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
>>>> Reviewed-by: Adam Ford <aford173@gmail.com>
>>>>
>>>> ---
>>>
>>> Any Fixes tag for this patch?
>>
>> I didn't add any as there is no commit that is clearly introducing the
>> problem. This patch fixes a behavior of the chip, which is there by
>> design by causes problems in some use cases.
>>
>> If a Fixes tag is required than I guess it should be the commit adding
>> support for the 5P49V6965, which is the only supported variant of VC[56]
>> having having the problematic behavior _and_ the reserved register bits
>> to prevent it. However I hardly could blame the author of that code for
>> such a "peculiar" chip behaviour. Do you still want me to add such a tag?
> 
> I tend to liberally apply the Fixes tag if something is being fixed. It
> helps understand that the patch is not introducing a new feature and
> when the incorrect code was introduced. I can slap on a Fixes tag
> myself, just not sure what to do.
> 

If you're OK in adding it while applying, here it is:

Fixes: 2bda748e6ad8 ("clk: vc5: Add support for IDT VersaClock 5P49V6965")

Thanks.
-- 
Luca


  reply	other threads:[~2021-06-03 21:06 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-27 21:16 Luca Ceresoli
2021-06-02  8:00 ` Stephen Boyd
2021-06-03  8:44   ` Luca Ceresoli
2021-06-03 20:07     ` Stephen Boyd
2021-06-03 21:06       ` Luca Ceresoli [this message]
2021-06-09  0:53 ` Stephen Boyd

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