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From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH 6/6] riscv: Update SiFive device tree for new CLINT driver
Date: Thu, 23 Jul 2020 09:57:18 -0400	[thread overview]
Message-ID: <ee666a09-1377-a26d-a243-4a6b7a2b2212@gmail.com> (raw)
In-Reply-To: <CAEUhbmUhdQvP4oeLH4fi=nU7C87Z8cM-OB6jKUCYg6XOYg0kyA@mail.gmail.com>

On 7/23/20 9:50 AM, Bin Meng wrote:
> Hi Sean,
> 
> On Wed, Jul 22, 2020 at 11:51 PM Sean Anderson <seanga2@gmail.com> wrote:
>>
>> We may need to add a clock-frequency binding like for the K210.
>>
>> Signed-off-by: Sean Anderson <seanga2@gmail.com>
>> ---
>> This patch builds but has NOT been tested.
>>
>>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 7 ++++++-
>>  1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> index afdb4f4402..e56bfc7595 100644
>> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> @@ -55,8 +55,13 @@
>>                 };
>>                 clint at 2000000 {
>>                         compatible = "riscv,clint0";
>> -                       interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>;
>> +                       interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
>> +                                              &cpu1_intc 3 &cpu1_intc 7
>> +                                              &cpu2_intc 3 &cpu2_intc 7
>> +                                              &cpu3_intc 3 &cpu3_intc 7
>> +                                              &cpu4_intc 3 &cpu4_intc 7>;
>>                         reg = <0x0 0x2000000 0x0 0xc0000>;
>> +                       clocks = <&prci PRCI_CLK_COREPLL>;
> 
> This looks wrong to me. The CLINT timer frequency should come from the RTC node.
> 
> +Pragnesh Patel
> 
> +Sagar Kadam

On further review, I think you are right that this should be RTCCLK_FREQ.

Perhaps the clocks part should be moved into
arch/riscv/dts/hifive-unleashed-a00-u-boot.dts and changed to something
like

clocks = <&rtcclk>;

--Sean

  reply	other threads:[~2020-07-23 13:57 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-22 15:51 [PATCH 0/6] riscv: Clean up timer drivers Sean Anderson
2020-07-22 15:51 ` [PATCH 1/6] riscv: Rework riscv timer driver to only support S-mode Sean Anderson
2020-07-28  9:11   ` Rick Chen
2020-07-28  9:27     ` Sean Anderson
2020-07-22 15:51 ` [PATCH 2/6] riscv: Rework Andes PLMT as a UCLASS_TIMER driver Sean Anderson
2020-07-23 13:51   ` Bin Meng
2020-07-23 13:54     ` Sean Anderson
2020-07-22 15:51 ` [PATCH 3/6] riscv: Clean up initialization in Andes PLIC Sean Anderson
2020-07-22 15:51 ` [PATCH 4/6] riscv: Rework Sifive CLINT as UCLASS_TIMER driver Sean Anderson
2020-07-22 15:51 ` [PATCH 5/6] riscv: Update Kendryte device tree for new CLINT driver Sean Anderson
2020-07-23 11:49   ` Sagar Kadam
2020-07-23 11:56     ` Sean Anderson
2020-07-23 13:49       ` Bin Meng
2020-07-23 13:59         ` Sean Anderson
2020-07-24  4:22           ` Sagar Kadam
2020-07-22 15:51 ` [PATCH 6/6] riscv: Update SiFive " Sean Anderson
2020-07-23 13:50   ` Bin Meng
2020-07-23 13:57     ` Sean Anderson [this message]
2020-07-23 14:22       ` Pragnesh Patel
2020-07-23 14:47       ` Bin Meng
2020-07-23 14:52         ` Sean Anderson
2020-07-23 16:51           ` Sagar Kadam
2020-07-23 20:27             ` Sean Anderson
2020-07-24  8:03               ` Sagar Kadam
2020-07-24  1:46           ` Bin Meng

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