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Thu, 16 Sep 2021 17:58:26 +0000 Subject: Re: [PATCH v6 1/3] dt-bindings: pwm: Add Xilinx AXI Timer To: Rob Herring Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, Thierry Reding , Alvaro Gamez , =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= , linux-arm-kernel@lists.infradead.org, Lee Jones , michal.simek@xilinx.com, linux-kernel@vger.kernel.org References: <20210826211830.3311140-1-sean.anderson@seco.com> From: Sean Anderson Message-ID: Date: Thu, 16 Sep 2021 13:58:21 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: BL1PR13CA0189.namprd13.prod.outlook.com (2603:10b6:208:2be::14) To DB7PR03MB4523.eurprd03.prod.outlook.com (2603:10a6:10:19::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [172.27.1.65] (50.195.82.171) by BL1PR13CA0189.namprd13.prod.outlook.com (2603:10b6:208:2be::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4544.6 via Frontend Transport; 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This device is a >> "soft" block, so it has some parameters which would not be configurable in >> most hardware. This binding is usually automatically generated by Xilinx's >> tools, so the names and values of some properties should be kept as they >> are, if possible. In addition, this binding is already in the kernel at >> arch/microblaze/boot/dts/system.dts, and in user software such as QEMU. >> >> The existing driver uses the clock-frequency property, or alternatively the >> /cpus/timebase-frequency property as its frequency input. Because these >> properties are deprecated, they have not been included with this schema. >> All new bindings should use the clocks/clock-names properties to specify >> the parent clock. >> >> Because we need to init timer devices so early in boot, we determine if we >> should use the PWM driver or the clocksource/clockevent driver by the >> presence/absence, respectively, of #pwm-cells. Because both counters are >> used by the PWM, there is no need for a separate property specifying which >> counters are to be used for the PWM. >> >> Signed-off-by: Sean Anderson >> --- >> >> Changes in v6: >> - Fix incorrect schema id >> - Enumerate possible counter widths >> >> Changes in v5: >> - Update commit message to reflect revisions >> - Fix indentation lint >> - Add example for timer binding >> - Remove xlnx,axi-timer-2.0 compatible string >> - Move schema into the timer directory >> >> Changes in v4: >> - Remove references to generate polarity so this can get merged >> - Predicate PWM driver on the presence of #pwm-cells >> - Make some properties optional for clocksource drivers >> >> Changes in v3: >> - Mark all boolean-as-int properties as deprecated >> - Add xlnx,pwm and xlnx,gen?-active-low properties. >> - Make newer replacement properties mutually-exclusive with what they >> replace >> - Add an example with non-deprecated properties only. >> >> Changes in v2: >> - Use 32-bit addresses for example binding >> >> .../bindings/timer/xlnx,xps-timer.yaml | 90 +++++++++++++++++++ >> 1 file changed, 90 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml >> >> diff --git a/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml >> new file mode 100644 >> index 000000000000..5be353a642aa >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml >> @@ -0,0 +1,90 @@ >> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding >> + >> +maintainers: >> + - Sean Anderson >> + >> +properties: >> + compatible: >> + contains: >> + const: xlnx,xps-timer-1.00.a >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + const: s_axi_aclk >> + >> + interrupts: >> + maxItems: 1 >> + >> + reg: >> + maxItems: 1 >> + >> + xlnx,count-width: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [8, 16, 32] >> + default: 32 >> + description: >> + The width of the counter(s), in bits. >> + >> + xlnx,one-timer-only: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + Whether only one timer is present in this block. >> + >> +required: >> + - compatible >> + - reg >> + - xlnx,one-timer-only >> + >> +allOf: >> + - if: >> + required: >> + - '#pwm-cells' >> + then: >> + allOf: >> + - required: >> + - clocks >> + - properties: >> + xlnx,one-timer-only: >> + const: 0 >> + else: >> + required: >> + - interrupts >> + - if: >> + required: >> + - clocks >> + then: >> + required: >> + - clock-names >> + >> +additionalProperties: true > > This needs to be false. What else do you expect to be present? I am going to leave this as true for the next revision to avoid the following error: arch/microblaze/boot/dts/system.dt.yaml: timer@83c00000: 'xlnx,family', 'xlnx,gen0-assert', 'xlnx,gen1-assert', 'xlnx,trig0-assert', 'xlnx,trig1-assert' do not match any of the regexes: 'pinctrl-[0-9]+' --Sean > >> + >> +examples: >> + - | >> + timer@800e0000 { >> + clock-names = "s_axi_aclk"; >> + clocks = <&zynqmp_clk 71>; >> + compatible = "xlnx,xps-timer-1.00.a"; >> + reg = <0x800e0000 0x10000>; >> + interrupts = <0 39 2>; >> + xlnx,count-width = <16>; >> + xlnx,one-timer-only = <0x0>; >> + }; >> + >> + timer@800f0000 { >> + #pwm-cells = <0>; >> + clock-names = "s_axi_aclk"; >> + clocks = <&zynqmp_clk 71>; >> + compatible = "xlnx,xps-timer-1.00.a"; >> + reg = <0x800e0000 0x10000>; >> + xlnx,count-width = <32>; >> + xlnx,one-timer-only = <0x0>; >> + }; >> -- >> 2.25.1 >> >> > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A09C9C433F5 for ; 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dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=seco.com; Received: from DB7PR03MB4523.eurprd03.prod.outlook.com (2603:10a6:10:19::27) by DBBPR03MB6700.eurprd03.prod.outlook.com (2603:10a6:10:20c::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4523.16; Thu, 16 Sep 2021 17:58:26 +0000 Received: from DB7PR03MB4523.eurprd03.prod.outlook.com ([fe80::a9aa:f363:66e:fadf]) by DB7PR03MB4523.eurprd03.prod.outlook.com ([fe80::a9aa:f363:66e:fadf%6]) with mapi id 15.20.4523.016; Thu, 16 Sep 2021 17:58:26 +0000 Subject: Re: [PATCH v6 1/3] dt-bindings: pwm: Add Xilinx AXI Timer To: Rob Herring Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, Thierry Reding , Alvaro Gamez , =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= , linux-arm-kernel@lists.infradead.org, Lee Jones , michal.simek@xilinx.com, linux-kernel@vger.kernel.org References: <20210826211830.3311140-1-sean.anderson@seco.com> From: Sean Anderson Message-ID: Date: Thu, 16 Sep 2021 13:58:21 -0400 User-Agent: Mozilla/5.0 (X11; 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charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 8/31/21 4:11 PM, Rob Herring wrote: > On Thu, Aug 26, 2021 at 05:18:28PM -0400, Sean Anderson wrote: >> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a >> "soft" block, so it has some parameters which would not be configurable in >> most hardware. This binding is usually automatically generated by Xilinx's >> tools, so the names and values of some properties should be kept as they >> are, if possible. In addition, this binding is already in the kernel at >> arch/microblaze/boot/dts/system.dts, and in user software such as QEMU. >> >> The existing driver uses the clock-frequency property, or alternatively the >> /cpus/timebase-frequency property as its frequency input. Because these >> properties are deprecated, they have not been included with this schema. >> All new bindings should use the clocks/clock-names properties to specify >> the parent clock. >> >> Because we need to init timer devices so early in boot, we determine if we >> should use the PWM driver or the clocksource/clockevent driver by the >> presence/absence, respectively, of #pwm-cells. Because both counters are >> used by the PWM, there is no need for a separate property specifying which >> counters are to be used for the PWM. >> >> Signed-off-by: Sean Anderson >> --- >> >> Changes in v6: >> - Fix incorrect schema id >> - Enumerate possible counter widths >> >> Changes in v5: >> - Update commit message to reflect revisions >> - Fix indentation lint >> - Add example for timer binding >> - Remove xlnx,axi-timer-2.0 compatible string >> - Move schema into the timer directory >> >> Changes in v4: >> - Remove references to generate polarity so this can get merged >> - Predicate PWM driver on the presence of #pwm-cells >> - Make some properties optional for clocksource drivers >> >> Changes in v3: >> - Mark all boolean-as-int properties as deprecated >> - Add xlnx,pwm and xlnx,gen?-active-low properties. >> - Make newer replacement properties mutually-exclusive with what they >> replace >> - Add an example with non-deprecated properties only. >> >> Changes in v2: >> - Use 32-bit addresses for example binding >> >> .../bindings/timer/xlnx,xps-timer.yaml | 90 +++++++++++++++++++ >> 1 file changed, 90 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml >> >> diff --git a/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml >> new file mode 100644 >> index 000000000000..5be353a642aa >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml >> @@ -0,0 +1,90 @@ >> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding >> + >> +maintainers: >> + - Sean Anderson >> + >> +properties: >> + compatible: >> + contains: >> + const: xlnx,xps-timer-1.00.a >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + const: s_axi_aclk >> + >> + interrupts: >> + maxItems: 1 >> + >> + reg: >> + maxItems: 1 >> + >> + xlnx,count-width: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [8, 16, 32] >> + default: 32 >> + description: >> + The width of the counter(s), in bits. >> + >> + xlnx,one-timer-only: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + Whether only one timer is present in this block. >> + >> +required: >> + - compatible >> + - reg >> + - xlnx,one-timer-only >> + >> +allOf: >> + - if: >> + required: >> + - '#pwm-cells' >> + then: >> + allOf: >> + - required: >> + - clocks >> + - properties: >> + xlnx,one-timer-only: >> + const: 0 >> + else: >> + required: >> + - interrupts >> + - if: >> + required: >> + - clocks >> + then: >> + required: >> + - clock-names >> + >> +additionalProperties: true > > This needs to be false. What else do you expect to be present? I am going to leave this as true for the next revision to avoid the following error: arch/microblaze/boot/dts/system.dt.yaml: timer@83c00000: 'xlnx,family', 'xlnx,gen0-assert', 'xlnx,gen1-assert', 'xlnx,trig0-assert', 'xlnx,trig1-assert' do not match any of the regexes: 'pinctrl-[0-9]+' --Sean > >> + >> +examples: >> + - | >> + timer@800e0000 { >> + clock-names = "s_axi_aclk"; >> + clocks = <&zynqmp_clk 71>; >> + compatible = "xlnx,xps-timer-1.00.a"; >> + reg = <0x800e0000 0x10000>; >> + interrupts = <0 39 2>; >> + xlnx,count-width = <16>; >> + xlnx,one-timer-only = <0x0>; >> + }; >> + >> + timer@800f0000 { >> + #pwm-cells = <0>; >> + clock-names = "s_axi_aclk"; >> + clocks = <&zynqmp_clk 71>; >> + compatible = "xlnx,xps-timer-1.00.a"; >> + reg = <0x800e0000 0x10000>; >> + xlnx,count-width = <32>; >> + xlnx,one-timer-only = <0x0>; >> + }; >> -- >> 2.25.1 >> >> > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel