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From: Igor Druzhinin <igor.druzhinin@citrix.com>
To: Jan Beulich <jbeulich@suse.com>, Laszlo Ersek <lersek@redhat.com>
Cc: <andrew.cooper3@citrix.com>, <roger.pau@citrix.com>, <wl@xen.org>,
	<iwj@xenproject.org>, <anthony.perard@citrix.com>,
	<xen-devel@lists.xenproject.org>
Subject: Re: [PATCH] hvmloader: pass PCI MMIO layout to OVMF as an info table
Date: Mon, 11 Jan 2021 15:26:38 +0000	[thread overview]
Message-ID: <ef643d22-c547-5ed0-1d2b-b3b1beeab359@citrix.com> (raw)
In-Reply-To: <aacd5a3b-228d-c93f-31ca-34f29f1ec6e8@suse.com>

On 11/01/2021 15:21, Jan Beulich wrote:
> On 11.01.2021 15:49, Laszlo Ersek wrote:
>> On 01/11/21 15:00, Igor Druzhinin wrote:
>>> On 11/01/2021 09:27, Jan Beulich wrote:
>>>> On 11.01.2021 05:53, Igor Druzhinin wrote:
>>>>> We faced a problem with passing through a PCI device with 64GB BAR to
>>>>> UEFI guest. The BAR is expectedly programmed into 64-bit PCI aperture at
>>>>> 64G address which pushes physical address space to 37 bits. OVMF uses
>>>>> address width early in PEI phase to make DXE identity pages covering
>>>>> the whole addressable space so it needs to know the last address it needs
>>>>> to cover but at the same time not overdo the mappings.
>>>>>
>>>>> As there is seemingly no other way to pass or get this information in
>>>>> OVMF at this early phase (ACPI is not yet available, PCI is not yet enumerated,
>>>>> xenstore is not yet initialized) - extend the info structure with a new
>>>>> table. Since the structure was initially created to be extendable -
>>>>> the change is backward compatible.
>>>>
>>>> How does UEFI handle the same situation on baremetal? I'd guess it is
>>>> in even more trouble there, as it couldn't even read addresses from
>>>> BARs, but would first need to assign them (or at least calculate
>>>> their intended positions).
>>>
>>> Maybe Laszlo or Anthony could answer this question quickly while I'm investigating?
>>
>> On the bare metal, the phys address width of the processor is known.
> 
> From CPUID I suppose.
> 
>> OVMF does the whole calculation in reverse because there's no way for it
>> to know the physical address width of the physical (= host) CPU.
>> "Overdoing" the mappings doesn't only waste resources, it breaks hard
>> with EPT -- access to a GPA that is inexpressible with the phys address
>> width of the host CPU (= not mappable successfully with the nested page
>> tables) will behave super bad. I don't recall the exact symptoms, but it
>> prevents booting the guest OS.
>>
>> This is why the most conservative 36-bit width is assumed by default.
> 
> IOW you don't trust virtualized CPUID output?

I'm discussing this with Andrew and it appears we're certainly more lax in
wiring physical address width into the guest from hardware directly rather
than KVM.

Another problem that I faced while experimenting is that creating page
tables for 46-bits (that CPUID returned in my case) of address space takes
about a minute on a modern CPU.

Igor


  reply	other threads:[~2021-01-11 15:27 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-11  4:53 [PATCH] hvmloader: pass PCI MMIO layout to OVMF as an info table Igor Druzhinin
2021-01-11  9:27 ` Jan Beulich
2021-01-11 14:00   ` Igor Druzhinin
2021-01-11 14:14     ` Jan Beulich
2021-01-11 14:43       ` Igor Druzhinin
2021-01-11 14:49     ` Laszlo Ersek
2021-01-11 15:21       ` Jan Beulich
2021-01-11 15:26         ` Igor Druzhinin [this message]
2021-01-11 15:31           ` Jan Beulich
2021-01-11 15:35           ` Laszlo Ersek
2021-01-11 16:31             ` Igor Druzhinin
2021-01-11 16:35               ` Laszlo Ersek
2021-01-11 15:30         ` Laszlo Ersek

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