From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurentiu Tudor Date: Wed, 20 Mar 2019 15:04:08 +0000 Subject: [U-Boot] [PATCH v2 1/3] fsl_sec: fix register layout on Layerscape architectures In-Reply-To: <20190320143130.32726-3-laurentiu.tudor@nxp.com> References: <20190320143130.32726-1-laurentiu.tudor@nxp.com> <20190320143130.32726-3-laurentiu.tudor@nxp.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hello, Please disregards these 3 patches as I've resubmitted them by mistake. I've updated their state in patchworks accordingly. --- Best regards, Laurentiu On 20.03.2019 16:31, laurentiu.tudor at nxp.com wrote: > From: Laurentiu Tudor > > On Layerscape architectures the SEC memory map is 1MB and the > register blocks contained in it are 64KB aligned, not 4KB as > the ccsr_sec structure currently assumes. Fix the layout of > the structure for these architectures. > > Signed-off-by: Laurentiu Tudor > Reviewed-by: Horia Geanta > Reviewed-by: Bharat Bhushan > --- > v2: > - added Reviewed-by tags > > include/fsl_sec.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/include/fsl_sec.h b/include/fsl_sec.h > index 16e3fcb5a1..be08a2b88b 100644 > --- a/include/fsl_sec.h > +++ b/include/fsl_sec.h > @@ -121,10 +121,18 @@ typedef struct ccsr_sec { > u32 chanum_ls; /* CHA Number Register, LS */ > u32 secvid_ms; /* SEC Version ID Register, MS */ > u32 secvid_ls; /* SEC Version ID Register, LS */ > +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) > + u8 res9[0x6f020]; > +#else > u8 res9[0x6020]; > +#endif > u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ > u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ > +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) > + u8 res10[0x8ffd8]; > +#else > u8 res10[0x8fd8]; > +#endif > } ccsr_sec_t; > > #define SEC_CTPR_MS_AXI_LIODN 0x08000000 >