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Tue, 08 Jun 2021 15:38:26 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Jun 2021 15:38:24 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Jun 2021 06:38:22 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 9 Jun 2021 06:38:22 +0800 Message-ID: Subject: Re: [PATCH v9 18/22] clk: mediatek: Add MT8192 mmsys clock support From: Chun-Jie Chen To: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring CC: , , , , , , , Weiyi Lu Date: Wed, 9 Jun 2021 06:38:22 +0800 In-Reply-To: <7520a10b-b362-03d4-e41b-e2098ae26621@gmail.com> References: <20210524122053.17155-1-chun-jie.chen@mediatek.com> <20210524122053.17155-19-chun-jie.chen@mediatek.com> <7520a10b-b362-03d4-e41b-e2098ae26621@gmail.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210608_153834_061197_BCD9D708 X-CRM114-Status: GOOD ( 24.97 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Tue, 2021-06-08 at 16:44 +0200, Matthias Brugger wrote: > > On 24/05/2021 14:20, Chun-Jie Chen wrote: > > Add MT8192 mmsys clock provider > > > > Signed-off-by: Weiyi Lu > > Signed-off-by: chun-jie.chen > > --- > > drivers/clk/mediatek/Kconfig | 6 ++ > > drivers/clk/mediatek/Makefile | 1 + > > drivers/clk/mediatek/clk-mt8192-mm.c | 108 > > +++++++++++++++++++++++++++ > > 3 files changed, 115 insertions(+) > > create mode 100644 drivers/clk/mediatek/clk-mt8192-mm.c > > > > [...] > > + > > +static int clk_mt8192_mm_probe(struct platform_device *pdev) > > +{ > > + struct device *dev = &pdev->dev; > > + struct device_node *node = dev->parent->of_node; > > + struct clk_onecell_data *clk_data; > > + int r; > > + > > + clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); > > + if (!clk_data) > > + return -ENOMEM; > > + > > + r = mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), > > clk_data); > > + if (r) > > + return r; > > + > > + return of_clk_add_provider(node, of_clk_src_onecell_get, > > clk_data); > > +} > > + > > +static struct platform_driver clk_mt8192_mm_drv = { > > + .probe = clk_mt8192_mm_probe, > > + .driver = { > > + .name = "clk-mt8192-mm", > > + }, > > +}; > > Did you had a look at drivers/soc/mediatek/mtk-mmsys.c? How is the > MMSYS > different from all the other SoCs? I suppose it is not. Please don't > just > implement the clock drivers, but check in existing code how they play > together > with the HW they are for. MediaTek unfortunately has the design to > add the clock > registers in the address space of the IP block that needs this > registers. Which > makes it more complicated to implement clock driver in the first > place. > > Regards, > Matthias Did you means binding the mm clock driver by creating a platform device in drivers/soc/mediatek/mtk-mmsys.c? There is 8192 mmsys compatible data in patch [1] but lack of it in the latest patch [2], I will check it. Thanks for your kind reminder. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/1609815993-22744-11-git-send-email-yongqiang.niu@mediatek.com/ [2] https://patchwork.kernel.org/project/linux-mediatek/patch/1618236288-1617-5-git-send-email-yongqiang.niu@mediatek.com/ Best Regards, Chun-Jie _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A522CC47082 for ; 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Wed, 9 Jun 2021 06:38:22 +0800 Message-ID: Subject: Re: [PATCH v9 18/22] clk: mediatek: Add MT8192 mmsys clock support From: Chun-Jie Chen To: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring CC: , , , , , , , Weiyi Lu Date: Wed, 9 Jun 2021 06:38:22 +0800 In-Reply-To: <7520a10b-b362-03d4-e41b-e2098ae26621@gmail.com> References: <20210524122053.17155-1-chun-jie.chen@mediatek.com> <20210524122053.17155-19-chun-jie.chen@mediatek.com> <7520a10b-b362-03d4-e41b-e2098ae26621@gmail.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210608_153834_061197_BCD9D708 X-CRM114-Status: GOOD ( 24.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 2021-06-08 at 16:44 +0200, Matthias Brugger wrote: > > On 24/05/2021 14:20, Chun-Jie Chen wrote: > > Add MT8192 mmsys clock provider > > > > Signed-off-by: Weiyi Lu > > Signed-off-by: chun-jie.chen > > --- > > drivers/clk/mediatek/Kconfig | 6 ++ > > drivers/clk/mediatek/Makefile | 1 + > > drivers/clk/mediatek/clk-mt8192-mm.c | 108 > > +++++++++++++++++++++++++++ > > 3 files changed, 115 insertions(+) > > create mode 100644 drivers/clk/mediatek/clk-mt8192-mm.c > > > > [...] > > + > > +static int clk_mt8192_mm_probe(struct platform_device *pdev) > > +{ > > + struct device *dev = &pdev->dev; > > + struct device_node *node = dev->parent->of_node; > > + struct clk_onecell_data *clk_data; > > + int r; > > + > > + clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); > > + if (!clk_data) > > + return -ENOMEM; > > + > > + r = mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), > > clk_data); > > + if (r) > > + return r; > > + > > + return of_clk_add_provider(node, of_clk_src_onecell_get, > > clk_data); > > +} > > + > > +static struct platform_driver clk_mt8192_mm_drv = { > > + .probe = clk_mt8192_mm_probe, > > + .driver = { > > + .name = "clk-mt8192-mm", > > + }, > > +}; > > Did you had a look at drivers/soc/mediatek/mtk-mmsys.c? How is the > MMSYS > different from all the other SoCs? I suppose it is not. Please don't > just > implement the clock drivers, but check in existing code how they play > together > with the HW they are for. MediaTek unfortunately has the design to > add the clock > registers in the address space of the IP block that needs this > registers. Which > makes it more complicated to implement clock driver in the first > place. > > Regards, > Matthias Did you means binding the mm clock driver by creating a platform device in drivers/soc/mediatek/mtk-mmsys.c? There is 8192 mmsys compatible data in patch [1] but lack of it in the latest patch [2], I will check it. Thanks for your kind reminder. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/1609815993-22744-11-git-send-email-yongqiang.niu@mediatek.com/ [2] https://patchwork.kernel.org/project/linux-mediatek/patch/1618236288-1617-5-git-send-email-yongqiang.niu@mediatek.com/ Best Regards, Chun-Jie _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel