From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D831C6FA82 for ; Sun, 18 Sep 2022 20:29:39 +0000 (UTC) Received: from localhost ([::1]:59080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oa0v4-00083b-EN for qemu-devel@archiver.kernel.org; Sun, 18 Sep 2022 16:29:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39738) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oa0qB-0004Wg-LT; Sun, 18 Sep 2022 16:24:35 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:51161) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oa0q9-0004AG-Pf; Sun, 18 Sep 2022 16:24:35 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id D031775A167; Sun, 18 Sep 2022 22:24:31 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 9BAC875A162; Sun, 18 Sep 2022 22:24:31 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v5 11/21] ppc440_sdram: Get rid of the init RAM hack MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sun, 18 Sep 2022 22:24:31 +0200 (CEST) Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Remove the do_init parameter of ppc440_sdram_init and enable SDRAM controller from the board. Firmware does this so it may only be needed when booting with -kernel without firmware but we enable SDRAM unconditionally to preserve previous behaviour. Signed-off-by: BALATON Zoltan --- v5: Add function to enable sdram controller hw/ppc/ppc440.h | 3 +-- hw/ppc/ppc440_uc.c | 15 +++++++++------ hw/ppc/sam460ex.c | 4 +++- include/hw/ppc/ppc4xx.h | 2 ++ 4 files changed, 15 insertions(+), 9 deletions(-) diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h index e6c905b7d6..01d76b8000 100644 --- a/hw/ppc/ppc440.h +++ b/hw/ppc/ppc440.h @@ -17,8 +17,7 @@ void ppc4xx_l2sram_init(CPUPPCState *env); void ppc4xx_cpr_init(CPUPPCState *env); void ppc4xx_sdr_init(CPUPPCState *env); void ppc440_sdram_init(CPUPPCState *env, int nbanks, - Ppc4xxSdramBank *ram_banks, - int do_init); + Ppc4xxSdramBank *ram_banks); void ppc4xx_ahb_init(CPUPPCState *env); void ppc4xx_dma_init(CPUPPCState *env, int dcr_base); void ppc460ex_pcie_init(CPUPPCState *env); diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 3fbfe4ad13..e8bc088c8f 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -16,6 +16,7 @@ #include "qemu/module.h" #include "hw/irq.h" #include "exec/memory.h" +#include "cpu.h" #include "hw/ppc/ppc4xx.h" #include "hw/qdev-properties.h" #include "hw/pci/pci.h" @@ -727,12 +728,11 @@ static void sdram_reset(void *opaque) ppc440_sdram_t *sdram = opaque; sdram->addr = 0; - sdram->mcopt2 = SDRAM_DDR2_MCOPT2_DCEN; + sdram->mcopt2 = 0; } void ppc440_sdram_init(CPUPPCState *env, int nbanks, - Ppc4xxSdramBank *ram_banks, - int do_init) + Ppc4xxSdramBank *ram_banks) { ppc440_sdram_t *sdram; int i; @@ -749,9 +749,6 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks, sdram, &dcr_read_sdram, &dcr_write_sdram); ppc_dcr_register(env, SDRAM0_CFGDATA, sdram, &dcr_read_sdram, &dcr_write_sdram); - if (do_init) { - sdram_map_bcr(sdram); - } ppc_dcr_register(env, SDRAM_R0BAS, sdram, &dcr_read_sdram, &dcr_write_sdram); @@ -773,6 +770,12 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks, sdram, &dcr_read_sdram, &dcr_write_sdram); } +void ppc440_sdram_enable(CPUPPCState *env) +{ + ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21); + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000); +} + /*****************************************************************************/ /* PLB to AHB bridge */ enum { diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index f4c2a693fb..9c01211b20 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -345,7 +345,9 @@ static void sam460ex_init(MachineState *machine) ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes); /* FIXME: does 460EX have ECC interrupts? */ - ppc440_sdram_init(env, 1, ram_banks, 1); + ppc440_sdram_init(env, 1, ram_banks); + /* Enable SDRAM memory regions as we may boot without firmware */ + ppc440_sdram_enable(env); /* IIC controllers and devices */ dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 558500fb97..78a845399e 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -37,6 +37,8 @@ typedef struct { uint32_t bcr; } Ppc4xxSdramBank; +void ppc440_sdram_enable(CPUPPCState *env); + void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, Ppc4xxSdramBank ram_banks[], const ram_addr_t sdram_bank_sizes[]); -- 2.30.4