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From: Jan Beulich <jbeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	"Wei Liu" <wl@xen.org>,
	"George Dunlap" <george.dunlap@citrix.com>,
	"Roger Pau Monné" <roger.pau@citrix.com>
Subject: Ping: [PATCH 4/5] x86/PV: restrict TLB flushing after mod_l[234]_entry()
Date: Thu, 1 Apr 2021 09:56:06 +0200	[thread overview]
Message-ID: <efc19a1c-5e63-e48e-89fc-5d353374e4d9@suse.com> (raw)
In-Reply-To: <2bee9e95-17f7-4089-4adf-29db50c5c4fd@suse.com>

On 11.01.2021 14:22, Jan Beulich wrote:
> On 11.01.2021 14:00, Roger Pau Monné wrote:
>> On Tue, Nov 03, 2020 at 11:57:33AM +0100, Jan Beulich wrote:
>>> Just like we avoid to invoke remote root pt flushes when all uses of an
>>> L4 table can be accounted for locally, the same can be done for all of
>>> L[234] for the linear pt flush when the table is a "free floating" one,
>>> i.e. it is pinned but not hooked up anywhere. While this situation
>>> doesn't occur very often, it can be observed.
>>>
>>> Since this breaks one of the implications of the XSA-286 fix, drop the
>>> flush_root_pt_local variable again and set ->root_pgt_changed directly,
>>> just like it was before that change.
>>>
>>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>>
>> LGTM, so:
>>
>> Acked-by: Roger Pau Monné <roger.pau@citrix.com>
> 
> Thanks.
> 
>> It would be good however if Andrew can give is opinion also, since he
>> was the one to introduce such logic, and it's not trivial.
> 
> I can certainly wait some, also to hopefully get a comment on
> 
>>> ---
>>> While adjusting the big comment that was added for XSA-286 I wondered
>>> why it talks about the "construction of 32bit PV guests". How are 64-bit
>>> PV guests different in this regard?
> 
> ... this, but his email troubles make it hard to judge for how
> long to wait.

About like for the other one just pinged, I intend to commit this
one together with the other two still pending ones in this series
once the tree is fully open again, unless I hear otherwise by then.
All three have been acked by Roger.

Jan


  reply	other threads:[~2021-04-01  7:56 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-03 10:54 [PATCH 0/5] x86/PV: memory management consistency and minor relaxations Jan Beulich
2020-11-03 10:56 ` [PATCH 1/5] x86/PV: consistently inline {,un}adjust_guest_l<N>e() Jan Beulich
2021-01-08 16:56   ` Roger Pau Monné
2020-11-03 10:56 ` [PATCH 2/5] x86/PV: fold redundant calls to adjust_guest_l<N>e() Jan Beulich
2021-01-11 10:36   ` Roger Pau Monné
2021-01-11 11:30     ` Jan Beulich
2020-11-03 10:57 ` [PATCH 3/5] x86/PV: _PAGE_RW changes may take fast path of mod_l[234]_entry() Jan Beulich
2021-01-11 11:08   ` Roger Pau Monné
2021-01-11 13:31     ` Jan Beulich
2021-01-11 14:26       ` Roger Pau Monné
2020-11-03 10:57 ` [PATCH 4/5] x86/PV: restrict TLB flushing after mod_l[234]_entry() Jan Beulich
2020-11-03 11:14   ` Andrew Cooper
2021-01-11 13:00   ` Roger Pau Monné
2021-01-11 13:22     ` Jan Beulich
2021-04-01  7:56       ` Jan Beulich [this message]
2020-11-03 10:58 ` [PATCH 5/5] x86/PV32: avoid TLB flushing after mod_l3_entry() Jan Beulich
2021-01-11 14:23   ` Roger Pau Monné
2021-01-11 14:28     ` Jan Beulich
2021-01-11 15:57       ` Roger Pau Monné
2020-11-23 13:49 ` Ping: [PATCH 0/5] x86/PV: memory management consistency and minor relaxations Jan Beulich

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