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[83.50.185.174]) by smtp.gmail.com with ESMTPSA id m17sm3674010wms.25.2021.12.17.15.18.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Dec 2021 15:19:00 -0800 (PST) Message-ID: Date: Sat, 18 Dec 2021 00:18:59 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.0 Subject: Re: [RFC PATCH v3 3/3] softmmu/physmem: Introduce MemTxAttrs::memory field and MEMTX_BUS_ERROR To: Peter Maydell References: <20211215182421.418374-1-philmd@redhat.com> <20211215182421.418374-4-philmd@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.718, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.716, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Hildenbrand , Jason Wang , Li Qiang , Qiuhao Li , Peter Xu , qemu-devel@nongnu.org, Alexander Bulekov , qemu-arm@nongnu.org, Gerd Hoffmann , Stefan Hajnoczi , "Edgar E . Iglesias" , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/17/21 23:34, Peter Maydell wrote: > On Wed, 15 Dec 2021 at 18:24, Philippe Mathieu-Daudé wrote: >> >> Add the 'memory' bit to the memory attributes to restrict bus >> controller accesses to memories. >> >> Introduce flatview_access_allowed() to check bus permission >> before running any bus transaction. >> >> Have read/write accessors return MEMTX_BUS_ERROR if an access is >> restricted. >> >> There is no change for the default case where 'memory' is not set. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> include/exec/memattrs.h | 9 +++++++++ >> softmmu/physmem.c | 43 +++++++++++++++++++++++++++++++++++++++-- >> 2 files changed, 50 insertions(+), 2 deletions(-) >> >> diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h >> index 95f2d20d55b..f0063583ee2 100644 >> --- a/include/exec/memattrs.h >> +++ b/include/exec/memattrs.h >> @@ -35,6 +35,14 @@ typedef struct MemTxAttrs { >> unsigned int secure:1; >> /* Memory access is usermode (unprivileged) */ >> unsigned int user:1; >> + /* >> + * Bus interconnect and peripherals can access anything (memories, >> + * devices) by default. By setting the 'memory' bit, bus transaction >> + * are restricted to "normal" memories (per the AMBA documentation) >> + * versus devices. Access to devices will be logged and rejected >> + * (see MEMTX_BUS_ERROR). >> + */ >> + unsigned int memory:1; >> /* Requester ID (for MSI for example) */ >> unsigned int requester_id:16; >> /* Invert endianness for this page */ >> @@ -66,6 +74,7 @@ typedef struct MemTxAttrs { >> #define MEMTX_OK 0 >> #define MEMTX_ERROR (1U << 0) /* device returned an error */ >> #define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ >> +#define MEMTX_BUS_ERROR (1U << 2) /* bus returned an error */ > > This is kind of odd naming, because MEMTX_DECODE_ERROR already means > "bus/interconnect returned an error" and it generally translates > into what at the OS level gets called a "bus error"... MEMTX_DECODE_ERROR is "nothing at that address". We want a name for "there is something, but you don't have access to it". Maybe MEMTX_ILLEGAL_ERROR?