From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LFG1x-0007du-4C for qemu-devel@nongnu.org; Tue, 23 Dec 2008 17:47:13 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LFG1v-0007cn-7e for qemu-devel@nongnu.org; Tue, 23 Dec 2008 17:47:12 -0500 Received: from [199.232.76.173] (port=52803 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LFG1u-0007cW-T4 for qemu-devel@nongnu.org; Tue, 23 Dec 2008 17:47:10 -0500 Received: from mail-bw0-f12.google.com ([209.85.218.12]:63433) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LFG1t-0007A4-1T for qemu-devel@nongnu.org; Tue, 23 Dec 2008 17:47:09 -0500 Received: by bwz5 with SMTP id 5so726092bwz.10 for ; Tue, 23 Dec 2008 14:47:06 -0800 (PST) Message-ID: Date: Tue, 23 Dec 2008 16:45:12 -0600 From: "Anthony Liguori" Subject: Re: [Qemu-devel] LSI53C895A: Implement Scratch Byte Register In-Reply-To: <0113846658934A0CA31221E22E3AC54F@FSCPC> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <0113846658934A0CA31221E22E3AC54F@FSCPC> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Tue, Dec 23, 2008 at 1:34 PM, Sebastian Herbszt wrote: > Qemu exits with > > lsi_scsi: error: Unhandled writeb 0x3a = 0x0 > lsi_scsi: error: readb 0x3a > > when trying to use LSI option rom 8xx_64.rom. Is this enough to get the LSI option rom working? Regards, Anthony Liguori > - Sebastian > > --- qemu-r6125/hw/lsi53c895a.c.orig Tue Dec 23 17:53:51 2008 > +++ qemu-r6125/hw/lsi53c895a.c Tue Dec 23 17:57:31 2008 > @@ -261,6 +261,7 @@ typedef struct { > uint32_t sbc; > uint32_t csbc; > uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */ > + uint8_t sbr; > > /* Script ram is stored as 32-bit words in host byteorder. */ > uint32_t script_ram[2048]; > @@ -329,6 +330,7 @@ static void lsi_soft_reset(LSIState *s) > s->ia = 0; > s->sbc = 0; > s->csbc = 0; > + s->sbr = 0; > } > > static int lsi_dma_40bit(LSIState *s) > @@ -1404,6 +1406,8 @@ static uint8_t lsi_reg_readb(LSIState *s > return s->dmode; > case 0x39: /* DIEN */ > return s->dien; > + case 0x3a: /* SBR */ > + return s->sbr; > case 0x3b: /* DCNTL */ > return s->dcntl; > case 0x40: /* SIEN0 */ > @@ -1616,6 +1620,9 @@ static void lsi_reg_writeb(LSIState *s, case 0x39: > /* DIEN */ > s->dien = val; > lsi_update_irq(s); > + break; > + case 0x3a: /* SBR */ > + s->sbr = val; > break; > case 0x3b: /* DCNTL */ > s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD); > > > >