From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Miao Subject: Re: [PATCH 3/6] pxa: fix pxa168 lcd controller vsync/hsync timing error Date: Wed, 4 Nov 2009 15:20:28 +0800 Message-ID: References: <7c34ac520911022245x7f002a7at846a835dfded550c@mail.gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <7c34ac520911022245x7f002a7at846a835dfded550c@mail.gmail.com> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Jun Nie Cc: linux-fbdev-devel@lists.sourceforge.net, linux-arm-kernel@lists.infradead.org T24gVHVlLCBOb3YgMywgMjAwOSBhdCAyOjQ1IFBNLCBKdW4gTmllIDxuaWVqMDAwMUBnbWFpbC5j b20+IHdyb3RlOgo+IHB4YTogZml4IHB4YTE2OCBsY2QgY29udHJvbGxlciB2c3luYy9oc3luYyB0 aW1pbmcgZXJyb3IKPgo+IFNpZ25lZC1vZmYtYnk6IEp1biBOaWUgPG5qdW5AbWFydmVsbC5jb20+ Cj4gLS0tCj4gwqBkcml2ZXJzL3ZpZGVvL3B4YTE2OGZiLmMgfCDCoCDCoDQgKystLQo+IMKgaW5j bHVkZS92aWRlby9weGExNjhmYi5oIHwgwqAgwqAyIC0tCj4gwqAyIGZpbGVzIGNoYW5nZWQsIDIg aW5zZXJ0aW9ucygrKSwgNCBkZWxldGlvbnMoLSkKPgo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3Zp ZGVvL3B4YTE2OGZiLmMgYi9kcml2ZXJzL3ZpZGVvL3B4YTE2OGZiLmMKPiBpbmRleCAyYmExNDQ0 Li5iZGQ1MjRjIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvdmlkZW8vcHhhMTY4ZmIuYwo+ICsrKyBi L2RyaXZlcnMvdmlkZW8vcHhhMTY4ZmIuYwo+IEBAIC00NTksOCArNDU5LDggQEAgc3RhdGljIHZv aWQgc2V0X2R1bWJfcGFuZWxfY29udHJvbChzdHJ1Y3QgZmJfaW5mbyAqaW5mbykKPiDCoCDCoCDC oCDCoHggfD0gbWktPmludmVydF9jb21wb3NpdGVfYmxhbmsgPyAweDAwMDAwMDQwIDogMDsKPiDC oCDCoCDCoCDCoHggfD0gKGluZm8tPnZhci5zeW5jICYgRkJfU1lOQ19DT01QX0hJR0hfQUNUKSA/ IDB4MDAwMDAwMjAgOiAwOwo+IMKgIMKgIMKgIMKgeCB8PSBtaS0+aW52ZXJ0X3BpeF92YWxfZW5h ID8gMHgwMDAwMDAxMCA6IDA7Cj4gLSDCoCDCoCDCoCB4IHw9IChpbmZvLT52YXIuc3luYyAmIEZC X1NZTkNfVkVSVF9ISUdIX0FDVCkgPyAwIDogMHgwMDAwMDAwODsKPiAtIMKgIMKgIMKgIHggfD0g KGluZm8tPnZhci5zeW5jICYgRkJfU1lOQ19IT1JfSElHSF9BQ1QpID8gMCA6IDB4MDAwMDAwMDQ7 Cj4gKyDCoCDCoCDCoCB4IHw9IChpbmZvLT52YXIuc3luYyAmIEZCX1NZTkNfVkVSVF9ISUdIX0FD VCkgPyAweDAwMDAwMDA4IDogMDsKPiArIMKgIMKgIMKgIHggfD0gKGluZm8tPnZhci5zeW5jICYg RkJfU1lOQ19IT1JfSElHSF9BQ1QpID8gMHgwMDAwMDAwNCA6IDA7CgpIaSBKdW4sCgpDb3VsZCB5 b3UgcGxlYXNlIGhlbHAgZG91YmxlIGNoZWNrIHRoaXM/IE15IHVuZGVyc3RhbmRpbmcgaXMKRkJf U1lOQ19WRVJUX0hJR0hfQUNUIG1lYW5zIGl0J3MgYSBwb3NpdGl2ZSBwdWxzZSBjb3ZlcmluZyBh bGwgdGhlCnZhbGlkIEhTWU5DcywgYW5kIGEgcmlzaW5nIGVkZ2Ugb2YgVlNZTkMgbWVhbnMgYSBz dGFydCBvZiB0aGUgZnJhbWUuCgpIb3dldmVyLCBDRkdfSU5WX1ZTWU5DIGlzICcxJyBtZWFucyB0 aGUgb3Bwb3NpdGUuCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3Rz LmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5m by9saW51eC1hcm0ta2VybmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: eric.y.miao@gmail.com (Eric Miao) Date: Wed, 4 Nov 2009 15:20:28 +0800 Subject: [PATCH 3/6] pxa: fix pxa168 lcd controller vsync/hsync timing error In-Reply-To: <7c34ac520911022245x7f002a7at846a835dfded550c@mail.gmail.com> References: <7c34ac520911022245x7f002a7at846a835dfded550c@mail.gmail.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Nov 3, 2009 at 2:45 PM, Jun Nie wrote: > pxa: fix pxa168 lcd controller vsync/hsync timing error > > Signed-off-by: Jun Nie > --- > ?drivers/video/pxa168fb.c | ? ?4 ++-- > ?include/video/pxa168fb.h | ? ?2 -- > ?2 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/video/pxa168fb.c b/drivers/video/pxa168fb.c > index 2ba1444..bdd524c 100644 > --- a/drivers/video/pxa168fb.c > +++ b/drivers/video/pxa168fb.c > @@ -459,8 +459,8 @@ static void set_dumb_panel_control(struct fb_info *info) > ? ? ? ?x |= mi->invert_composite_blank ? 0x00000040 : 0; > ? ? ? ?x |= (info->var.sync & FB_SYNC_COMP_HIGH_ACT) ? 0x00000020 : 0; > ? ? ? ?x |= mi->invert_pix_val_ena ? 0x00000010 : 0; > - ? ? ? x |= (info->var.sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x00000008; > - ? ? ? x |= (info->var.sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x00000004; > + ? ? ? x |= (info->var.sync & FB_SYNC_VERT_HIGH_ACT) ? 0x00000008 : 0; > + ? ? ? x |= (info->var.sync & FB_SYNC_HOR_HIGH_ACT) ? 0x00000004 : 0; Hi Jun, Could you please help double check this? My understanding is FB_SYNC_VERT_HIGH_ACT means it's a positive pulse covering all the valid HSYNCs, and a rising edge of VSYNC means a start of the frame. However, CFG_INV_VSYNC is '1' means the opposite.