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Fri, 21 Jul 2023 02:03:30 GMT Received: from [10.239.132.204] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 20 Jul 2023 19:03:27 -0700 Message-ID: Date: Fri, 21 Jul 2023 10:03:25 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI To: Konrad Dybcio , , , , CC: , , , , , , , , References: <20230719100135.21325-1-quic_tengfan@quicinc.com> <20230719100135.21325-2-quic_tengfan@quicinc.com> From: Tengfei Fan In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: qP8iqfmLBQKIufLusNeXEOXrWssOhO2T X-Proofpoint-ORIG-GUID: qP8iqfmLBQKIufLusNeXEOXrWssOhO2T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-20_12,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=550 spamscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307210017 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org 在 7/20/2023 3:54 PM, Konrad Dybcio 写道: > On 19.07.2023 12:01, Tengfei Fan wrote: >> This add based DTSI for SM4450 SoC and includes base description of >> CPUs and interrupt-controller which helps to boot to shell with >> console on boards with this SoC. >> >> Signed-off-by: Tengfei Fan >> --- > [...] > >> +#include >> +#include > Please sort them alphabetically V2 patch will resort them. > >> + >> +/ { >> + interrupt-parent = <&intc>; >> + > [...] > >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + CPU0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "qcom,kryo"; > Please post dmesg | grep '\[', this is probably a standard ARM core. sure, will do and update this compatible. > >> + reg = <0x0 0x0>; >> + enable-method = "psci"; >> + next-level-cache = <&L2_0>; >> + power-domains = <&CPU_PD0>; >> + power-domain-names = "psci"; >> + #cooling-cells = <2>; >> + L2_0: l2-cache { > Missing a newline before subnodes V2 patch will add newline. > >> + compatible = "cache"; >> + cache-level = <2>; >> + cache-unified; >> + next-level-cache = <&L3_0>; >> + L3_0: l3-cache { > Ditto V2 patch will add newline. > >> + compatible = "cache"; >> + cache-level = <3>; >> + cache-unified; >> + }; >> + }; >> + }; > [...] > >> + >> + intc: interrupt-controller@17200000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + #redistributor-regions = <1>; >> + redistributor-stride = <0x0 0x20000>; >> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ >> + <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */ > Misasligned V2 patch will align. > > also, please move reg and interrupts after compatible V2 patch will resort. > >> + interrupts = ; >> + }; >> + >> + timer@17420000 { >> + compatible = "arm,armv7-timer-mem"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0 0 0 0x20000000>; >> + reg = <0x0 0x17420000 0x0 0x1000>; >> + clock-frequency = <19200000>; > Drop clock-frequency V2 patch will Drop this clock-frequency node. > > [...] > >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = , >> + , >> + , >> + ; > Misaligned V2 patch will align. > >> + clock-frequency = <19200000>; > Drop V2 patch will drop. > > Konrad >> + }; >> +}; -- Thx and BRs, Tengfei Fan