Re: [PATCH] mtd: rawnand: marvell: fix command xtype in BCH write hook

[Chris Packham <Chris.Packham@alliedtelesis.co.nz>]

Hi Miquel,

On 03/05/18 22:00, Miquel Raynal wrote:
> One layout supported by the Marvell NAND controller supports NAND pages
> of 2048 bytes, all handled in one single chunk when using BCH with a
> strength of 4-bit per 512 bytes. In this case, instead of the generic
> XTYPE_WRITE_DISPATCH/XTYPE_LAST_NAKED_RW couple, the controller expects
> to receive XTYPE_MONOLITHIC_RW.
> 
> This fixes problems at boot like:
> 
> [    1.315475] Scanning device for bad blocks
> [    3.203108] marvell-nfc f10d0000.flash: Timeout waiting for RB signal
> [    3.209564] nand_bbt: error while writing BBT block -110
> [    4.243106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal
> [    5.283106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal
> [    5.289562] nand_bbt: error -110 while marking block 2047 bad
> [    6.323106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal
> [    6.329559] nand_bbt: error while writing BBT block -110
> [    7.363106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal
> [    8.403105] marvell-nfc f10d0000.flash: Timeout waiting for RB signal
> [    8.409559] nand_bbt: error -110 while marking block 2046 bad
> ...
> 
> Fixes: 02f26ecf8c772 ("mtd: nand: add reworked Marvell NAND controller driver")
> Cc: stable@vger.kernel.org
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

For the following combinations

SoC             NAND                    Size     EB      Page OOB
---             ----                    ----     --      ---- ---
Armada-385      Micron MT29F8G08ABACAWP 1024 MiB 256 KiB 4096 224
Armada-385      Micron MT29F2G08ABAEAWP 256 MiB  128 KiB 2048 64
Armada-385      Macronix MX30LF2G18AC   256 MiB  128 KiB 2048 64
Armada-98DX4251 AMD/Spansion S34ML08G2  1024 MiB 128 KiB 2048 128
Armada-98DX4251 Macronix MX60LF8G18AC   1024 MiB 128 KiB 2048 64
Armada-98DX4251 Micron MT29F8G08ABABAWP 1024 MiB 512 KiB 4096 224

Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

I do have one platform that passes the initial detection but starts to 
report ubifs errors when mounted.

Armada-98DX4251 Micron MT29F8G08ABACAWP 1024 MiB 256 KiB 4096 224

This is probably unrelated to this particular fix. It may be as simple 
as something not catering for the Armada-98DX4251 SoC or a genuine 
difference between Armada-98DX4251 and Armada-385. 4.16.4 with 
pxa3xx_nand works with this combination.

> ---
> 
> Chris,
> 
> Can you please give this patch a try? This is very likely to solve your
> boot issue.
> 
> Thanks,
> Miquèl
> 
>   drivers/mtd/nand/raw/marvell_nand.c | 8 +++++++-
>   1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
> index e4b964fd40d8..db5ec4e8bde9 100644
> --- a/drivers/mtd/nand/raw/marvell_nand.c
> +++ b/drivers/mtd/nand/raw/marvell_nand.c
> @@ -1408,6 +1408,7 @@ marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk,
>   	struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
>   	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
>   	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
> +	u32 xtype;
>   	int ret;
>   	struct marvell_nfc_op nfc_op = {
>   		.ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD,
> @@ -1423,7 +1424,12 @@ marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk,
>   	 * last naked write.
>   	 */
>   	if (chunk == 0) {
> -		nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_WRITE_DISPATCH) |
> +		if (lt->nchunks == 1)
> +			xtype = XTYPE_MONOLITHIC_RW;
> +		else
> +			xtype = XTYPE_WRITE_DISPATCH;
> +
> +		nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) |
>   				  NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
>   				  NDCB0_CMD1(NAND_CMD_SEQIN);
>   		nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page);
>