From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48623) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1byzR2-0000YE-Bu for qemu-devel@nongnu.org; Tue, 25 Oct 2016 06:58:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1byzQx-0004Om-DN for qemu-devel@nongnu.org; Tue, 25 Oct 2016 06:58:24 -0400 Received: from 6.mo68.mail-out.ovh.net ([46.105.63.100]:40446) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1byzQx-0004Oe-6o for qemu-devel@nongnu.org; Tue, 25 Oct 2016 06:58:19 -0400 Received: from player788.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 105C09624 for ; Tue, 25 Oct 2016 12:58:16 +0200 (CEST) References: <1477129610-31353-1-git-send-email-clg@kaod.org> <1477129610-31353-14-git-send-email-clg@kaod.org> <20161025053627.GC11052@umbus.fritz.box> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: Date: Tue, 25 Oct 2016 12:58:11 +0200 MIME-Version: 1.0 In-Reply-To: <20161025053627.GC11052@umbus.fritz.box> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v5 13/17] ppc/xics: add a xics_get_cpu_index_by_pir helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org, Alexander Graf On 10/25/2016 07:36 AM, David Gibson wrote: > On Sat, Oct 22, 2016 at 11:46:46AM +0200, C=E9dric Le Goater wrote: >> We will need this helper to translate the server number of the XIVE >> (which is a PIR) into an ICPState index number (which is a cpu index). >> >> Signed-off-by: C=E9dric Le Goater >=20 > Looks correct as far as it goes, but I wonder if this would be more > generally useful as a machine level function that searches the cpu > objects by PIR, returning a pointer. From that to the cpu_index is > then trivial. Well I guess so. The XICSState argument reduces the scope in case of=20 multichip but as this routine is used to initialize the xive registers,=20 it does not need to be fast. So you rather have, something like: PowerPCCPU *ppc_get_vcpu_by_pir(int pir); similar to : PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id); Thanks, C.=20 >> --- >> hw/intc/xics_native.c | 19 +++++++++++++++++++ >> include/hw/ppc/xics.h | 1 + >> 2 files changed, 20 insertions(+) >> >> diff --git a/hw/intc/xics_native.c b/hw/intc/xics_native.c >> index bbdd786aeb50..6318862f53fc 100644 >> --- a/hw/intc/xics_native.c >> +++ b/hw/intc/xics_native.c >> @@ -33,6 +33,25 @@ >> =20 >> #include >> =20 >> +int xics_get_cpu_index_by_pir(XICSState *xics, int pir) >> +{ >> + int i; >> + >> + for (i =3D 0; i < xics->nr_servers; i++) { >> + ICPState *icp =3D &xics->ss[i]; >> + if (icp->cs) { >> + PowerPCCPU *cpu =3D POWERPC_CPU(icp->cs); >> + CPUPPCState *env =3D &cpu->env; >> + >> + if (env->spr_cb[SPR_PIR].default_value =3D=3D pir) { >> + return i; >> + } >> + } >> + } >> + >> + return -1; >> +} >> + >> static void xics_native_reset(void *opaque) >> { >> device_reset(DEVICE(opaque)); >> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h >> index 911cdd5e549f..beb232e616c5 100644 >> --- a/include/hw/ppc/xics.h >> +++ b/include/hw/ppc/xics.h >> @@ -214,6 +214,7 @@ void xics_set_nr_servers(XICSState *xics, uint32_t= nr_servers, >> =20 >> /* Internal XICS interfaces */ >> int xics_get_cpu_index_by_dt_id(int cpu_dt_id); >> +int xics_get_cpu_index_by_pir(XICSState *xics, int pir); >> =20 >> void icp_set_cppr(ICPState *icp, uint8_t cppr); >> void icp_set_mfrr(ICPState *icp, uint8_t mfrr); >=20