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Tue, 19 Apr 2022 23:47:07 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u25-20020a199219000000b0047178ad732fsm1022779lfd.242.2022.04.19.23.47.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Apr 2022 23:47:07 -0700 (PDT) Message-ID: Date: Wed, 20 Apr 2022 09:47:06 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH v2 07/17] drm/msm/dpu: add writeback blocks to DPU RM Content-Language: en-GB To: Abhinav Kumar , freedreno@lists.freedesktop.org References: <1650419169-13760-1-git-send-email-quic_abhinavk@quicinc.com> <1650419169-13760-8-git-send-email-quic_abhinavk@quicinc.com> From: Dmitry Baryshkov In-Reply-To: <1650419169-13760-8-git-send-email-quic_abhinavk@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: markyacoub@chromium.org, liviu.dudau@arm.com, dri-devel@lists.freedesktop.org, swboyd@chromium.org, seanpaul@chromium.org, laurent.pinchart@ideasonboard.com, quic_jesszhan@quicinc.com, quic_aravindh@quicinc.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 20/04/2022 04:45, Abhinav Kumar wrote: > Add writeback blocks to DPU resource manager so that > the encoders can directly request them through RM. > > changes in v2: > - stop global tracking of WB blocks similar to INTF > - align usage of hw_wb to be similar to that of hw_intf > > Signed-off-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 ++++++++++++++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 ++++++++++++ > 2 files changed, 34 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c > index 0e6634b..bb01d31 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c > @@ -9,6 +9,7 @@ > #include "dpu_hw_ctl.h" > #include "dpu_hw_pingpong.h" > #include "dpu_hw_intf.h" > +#include "dpu_hw_wb.h" > #include "dpu_hw_dspp.h" > #include "dpu_hw_merge3d.h" > #include "dpu_hw_dsc.h" > @@ -87,6 +88,9 @@ int dpu_rm_destroy(struct dpu_rm *rm) > } > } > > + for (i = 0; i < ARRAY_SIZE(rm->hw_wb); i++) > + dpu_hw_wb_destroy(rm->hw_wb[i]); > + > return 0; > } > > @@ -186,6 +190,24 @@ int dpu_rm_init(struct dpu_rm *rm, > rm->hw_intf[intf->id - INTF_0] = hw; > } > > + for (i = 0; i < cat->wb_count; i++) { > + struct dpu_hw_wb *hw; > + const struct dpu_wb_cfg *wb = &cat->wb[i]; > + > + if (wb->id < WB_0 || wb->id >= WB_MAX) { > + DPU_ERROR("skip intf %d with invalid id\n", wb->id); > + continue; > + } > + > + hw = dpu_hw_wb_init(wb->id, mmio, cat); > + if (IS_ERR_OR_NULL(hw)) { Just IS_ERR() please. > + rc = PTR_ERR(hw); > + DPU_ERROR("failed wb object creation: err %d\n", rc); > + goto fail; > + } > + rm->hw_wb[wb->id - WB_0] = hw; > + } > + > for (i = 0; i < cat->ctl_count; i++) { > struct dpu_hw_ctl *hw; > const struct dpu_ctl_cfg *ctl = &cat->ctl[i]; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h > index 32e0d8a..ba82e54 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h > @@ -19,6 +19,7 @@ struct dpu_global_state; > * @mixer_blks: array of layer mixer hardware resources > * @ctl_blks: array of ctl hardware resources > * @hw_intf: array of intf hardware resources > + * @hw_wb: array of wb hardware resources > * @dspp_blks: array of dspp hardware resources > */ > struct dpu_rm { > @@ -26,6 +27,7 @@ struct dpu_rm { > struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; > struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; > struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0]; > + struct dpu_hw_wb *hw_wb[WB_MAX - WB_0]; > struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; > struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; > struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0]; > @@ -96,5 +98,15 @@ static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_in > return rm->hw_intf[intf_idx - INTF_0]; > } > > +/** > + * dpu_rm_get_wb - Return a struct dpu_hw_wb instance given it's index. > + * @rm: DPU Resource Manager handle > + * @wb_idx: WB index > + */ > +static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_intf wb_idx) > +{ > + return rm->hw_wb[wb_idx - WB_0]; > +} > + > #endif /* __DPU_RM_H__ */ > -- With best wishes Dmitry