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dkim=none (message not signed) header.d=none; lists.freedesktop.org; dmarc=none action=none header.from=amd.com; Received: from CH0PR12MB5348.namprd12.prod.outlook.com (2603:10b6:610:d7::9) by CH0PR12MB5137.namprd12.prod.outlook.com (2603:10b6:610:bc::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.25; Wed, 19 May 2021 15:44:49 +0000 Received: from CH0PR12MB5348.namprd12.prod.outlook.com ([fe80::9c3:508d:5340:8efd]) by CH0PR12MB5348.namprd12.prod.outlook.com ([fe80::9c3:508d:5340:8efd%6]) with mapi id 15.20.4129.033; Wed, 19 May 2021 15:44:49 +0000 Subject: Re: [PATCH 3/3] drm/amdgpu/pm: display vcn pp dpm To: David M Nieto , amd-gfx@lists.freedesktop.org References: <476f8809-5521-98b4-e08f-1d06fc099468@amd.com> <20210519060233.13597-1-david.nieto@amd.com> <20210519060233.13597-3-david.nieto@amd.com> From: Lijo Lazar Message-ID: Date: Wed, 19 May 2021 21:14:36 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.2 In-Reply-To: <20210519060233.13597-3-david.nieto@amd.com> Content-Language: en-US X-Originating-IP: [117.222.149.218] X-ClientProxiedBy: PN2PR01CA0119.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:27::34) To CH0PR12MB5348.namprd12.prod.outlook.com (2603:10b6:610:d7::9) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [192.168.1.102] (117.222.149.218) by PN2PR01CA0119.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:27::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.25 via Frontend Transport; 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charset="us-ascii"; Format="flowed" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Avoid changes to sienna_cichlid_force_clk_levels as well. With that addressed patch is Reviewed-by: Lijo Lazar On 5/19/2021 11:32 AM, David M Nieto wrote: > Enable displaying DPM levels for VCN clocks > in swsmu supported ASICs > > Signed-off-by: David M Nieto > --- > .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 46 +++++++++++++++++++ > .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 + > .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 8 ++++ > .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 34 ++++++++++++++ > .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 46 +++++++++++++++++++ > 5 files changed, 136 insertions(+) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > index 77693bf0840c..1735a96dd307 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > @@ -822,6 +822,52 @@ static int arcturus_print_clk_levels(struct smu_context *smu, > now) ? "*" : "")); > break; > > + case SMU_VCLK: > + ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); > + if (ret) { > + dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); > + return ret; > + } > + > + single_dpm_table = &(dpm_context->dpm_tables.vclk_table); > + ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); > + if (ret) { > + dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); > + return ret; > + } > + > + for (i = 0; i < single_dpm_table->count; i++) > + size += sprintf(buf + size, "%d: %uMhz %s\n", > + i, single_dpm_table->dpm_levels[i].value, > + (clocks.num_levels == 1) ? "*" : > + (arcturus_freqs_in_same_level( > + clocks.data[i].clocks_in_khz / 1000, > + now) ? "*" : "")); > + break; > + > + case SMU_DCLK: > + ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); > + if (ret) { > + dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); > + return ret; > + } > + > + single_dpm_table = &(dpm_context->dpm_tables.dclk_table); > + ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); > + if (ret) { > + dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); > + return ret; > + } > + > + for (i = 0; i < single_dpm_table->count; i++) > + size += sprintf(buf + size, "%d: %uMhz %s\n", > + i, single_dpm_table->dpm_levels[i].value, > + (clocks.num_levels == 1) ? "*" : > + (arcturus_freqs_in_same_level( > + clocks.data[i].clocks_in_khz / 1000, > + now) ? "*" : "")); > + break; > + > case SMU_PCIE: > gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); > lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > index b8971303a873..7763de464678 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > @@ -1273,6 +1273,8 @@ static int navi10_print_clk_levels(struct smu_context *smu, > case SMU_MCLK: > case SMU_UCLK: > case SMU_FCLK: > + case SMU_VCLK: > + case SMU_DCLK: > case SMU_DCEFCLK: > ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); > if (ret) > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > index 0c40a54c46d7..6da6d08d8858 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > @@ -987,6 +987,10 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, > case SMU_MCLK: > case SMU_UCLK: > case SMU_FCLK: > + case SMU_VCLK: > + case SMU_VCLK1: > + case SMU_DCLK: > + case SMU_DCLK1: > case SMU_DCEFCLK: > ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); > if (ret) > @@ -1150,6 +1154,10 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu, > case SMU_MCLK: > case SMU_UCLK: > case SMU_FCLK: > + case SMU_VCLK: > + case SMU_VCLK1: > + case SMU_DCLK: > + case SMU_DCLK1: > /* There is only 2 levels for fine grained DPM */ > if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { > soft_max_level = (soft_max_level >= 1 ? 1 : 0); > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c > index f43b4c623685..0805dc439572 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c > @@ -109,6 +109,8 @@ static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = { > CLK_MAP(SOCCLK, CLOCK_SOCCLK), > CLK_MAP(UCLK, CLOCK_FCLK), > CLK_MAP(MCLK, CLOCK_FCLK), > + CLK_MAP(VCLK, CLOCK_VCLK), > + CLK_MAP(DCLK, CLOCK_DCLK), > }; > > static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = { > @@ -202,6 +204,17 @@ static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type > return -EINVAL; > *freq = clk_table->FClocks[dpm_level].Freq; > break; > + case SMU_VCLK: > + if (dpm_level >= NUM_VCN_DPM_LEVELS) > + return -EINVAL; > + *freq = clk_table->VClocks[dpm_level].Freq; > + break; > + case SMU_DCLK: > + if (dpm_level >= NUM_VCN_DPM_LEVELS) > + return -EINVAL; > + *freq = clk_table->DClocks[dpm_level].Freq; > + break; > + > default: > return -EINVAL; > } > @@ -532,6 +545,14 @@ static int renoir_print_clk_levels(struct smu_context *smu, > count = NUM_FCLK_DPM_LEVELS; > cur_value = metrics.ClockFrequency[CLOCK_FCLK]; > break; > + case SMU_VCLK: > + count = NUM_VCN_DPM_LEVELS; > + cur_value = metrics.ClockFrequency[CLOCK_VCLK]; > + break; > + case SMU_DCLK: > + count = NUM_VCN_DPM_LEVELS; > + cur_value = metrics.ClockFrequency[CLOCK_DCLK]; > + break; > default: > break; > } > @@ -543,6 +564,8 @@ static int renoir_print_clk_levels(struct smu_context *smu, > case SMU_MCLK: > case SMU_DCEFCLK: > case SMU_FCLK: > + case SMU_VCLK: > + case SMU_DCLK: > for (i = 0; i < count; i++) { > ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value); > if (ret) > @@ -730,6 +753,17 @@ static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks > clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol; > } > > + for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) { > + clock_table->VClocks[i].Freq = table->VClocks[i].Freq; > + clock_table->VClocks[i].Vol = table->VClocks[i].Vol; > + } > + > + for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) { > + clock_table->DClocks[i].Freq = table->DClocks[i].Freq; > + clock_table->DClocks[i].Vol = table->DClocks[i].Vol; > + } > + > + > return 0; > } > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c > index 7c191a5d6db9..fb744f3e17d7 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c > @@ -816,6 +816,52 @@ static int aldebaran_print_clk_levels(struct smu_context *smu, > now) ? "*" : "")); > break; > > + case SMU_VCLK: > + ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); > + if (ret) { > + dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); > + return ret; > + } > + > + single_dpm_table = &(dpm_context->dpm_tables.vclk_table); > + ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); > + if (ret) { > + dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); > + return ret; > + } > + > + for (i = 0; i < single_dpm_table->count; i++) > + size += sprintf(buf + size, "%d: %uMhz %s\n", > + i, single_dpm_table->dpm_levels[i].value, > + (clocks.num_levels == 1) ? "*" : > + (aldebaran_freqs_in_same_level( > + clocks.data[i].clocks_in_khz / 1000, > + now) ? "*" : "")); > + break; > + > + case SMU_DCLK: > + ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); > + if (ret) { > + dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); > + return ret; > + } > + > + single_dpm_table = &(dpm_context->dpm_tables.dclk_table); > + ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table); > + if (ret) { > + dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); > + return ret; > + } > + > + for (i = 0; i < single_dpm_table->count; i++) > + size += sprintf(buf + size, "%d: %uMhz %s\n", > + i, single_dpm_table->dpm_levels[i].value, > + (clocks.num_levels == 1) ? "*" : > + (aldebaran_freqs_in_same_level( > + clocks.data[i].clocks_in_khz / 1000, > + now) ? "*" : "")); > + break; > + > default: > break; > } > -- Thanks, Lijo _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx