From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26212C4707F for ; Thu, 27 May 2021 06:13:56 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 983FC613DA for ; Thu, 27 May 2021 06:13:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 983FC613DA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 527E182052; Thu, 27 May 2021 08:13:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1622096032; bh=UCZTEBg0U1GqXfh4IydRFs+P2vxYD/+Wucra9O91OPM=; h=Subject:To:Cc:References:From:Date:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=KZ+1GF5NxNc+2upn6zt/MDLa15QSSgSOI2C+Xx64ihOWzlqoasmH/WZfJ0p0RXuwt 4+ui/XnXvQ54hwqn+RcG1eIPYqIuVEVagt0bhed4znDu4KE/UKm8b9V6UDNONsRFft 1TAF2FIYbuB/H+vD12Yj+mjIV1lzlneZ1lUIQfO4xb7TklcspJzeDjGyW9gprpi58l 4q+z8coX0QtYiRUjR3/3AalZZmeXBrK/Mma8zoUhEuuzRSantOOAl1DlVA8+hJG2GX 7j6g8PN4YRDRNOoE7/DgPftmntf7H8RzeyLUSZjunzuEKpvlwbtBaI9TbWLsOVMegQ q4pfmIyNkTESQ== Received: by phobos.denx.de (Postfix, from userid 109) id AE08282CAC; Thu, 27 May 2021 08:13:50 +0200 (CEST) Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [91.198.250.252]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0B3AF81DB3 for ; Thu, 27 May 2021 08:13:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4FrHZM6cVyzQjBM; Thu, 27 May 2021 08:13:47 +0200 (CEST) Received: from smtp1.mailbox.org ([80.241.60.240]) by spamfilter01.heinlein-hosting.de (spamfilter01.heinlein-hosting.de [80.241.56.115]) (amavisd-new, port 10030) with ESMTP id qIn1ntTdJVEC; Thu, 27 May 2021 08:13:44 +0200 (CEST) Subject: Re: [PATCH u-boot-marvell 1/5] serial: a37xx: Fix parent clock rate value and divider calculation To: =?UTF-8?Q?Marek_Beh=c3=ban?= , u-boot@lists.denx.de Cc: =?UTF-8?Q?Pali_Roh=c3=a1r?= References: <20210525174242.27509-1-marek.behun@nic.cz> <20210525174242.27509-2-marek.behun@nic.cz> From: Stefan Roese Message-ID: Date: Thu, 27 May 2021 08:13:44 +0200 MIME-Version: 1.0 In-Reply-To: <20210525174242.27509-2-marek.behun@nic.cz> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: de-DE Content-Transfer-Encoding: 8bit X-MBO-SPAM-Probability: X-Rspamd-Score: -6.68 / 15.00 / 15.00 X-Rspamd-Queue-Id: D4B191860 X-Rspamd-UID: ce4f74 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean On 25.05.21 19:42, Marek Behún wrote: > From: Pali Rohár > > UART parent clock is by default the platform's xtal clock, which is > 25 MHz. > > The value defined in the driver, though, is 25.8048 MHz. This is a hack > for the suboptimal divisor calculation > Divisor = UART clock / (16 * baudrate) > which does not use rounding division, resulting in a suboptimal value > for divisor if the correct parent clock rate was used. > > Change the code for divisor calculation to round to closest value, i.e. > Divisor = Round(UART clock / (16 * baudrate)) > and change the parent clock rate value to that returned by > get_ref_clk(). > > This makes A3720 UART stable at standard UART baudrates between 1800 and > 230400. > > Signed-off-by: Pali Rohár > Reviewed-by: Marek Behún Reviewed-by: Stefan Roese Thanks, Stefan > --- > drivers/serial/serial_mvebu_a3700.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c > index 8f404879a5..9e7e479f80 100644 > --- a/drivers/serial/serial_mvebu_a3700.c > +++ b/drivers/serial/serial_mvebu_a3700.c > @@ -7,6 +7,7 @@ > #include > #include > #include > +#include > > struct mvebu_plat { > void __iomem *base; > @@ -29,8 +30,6 @@ struct mvebu_plat { > #define UART_CTRL_RXFIFO_RESET 0x4000 > #define UART_CTRL_TXFIFO_RESET 0x8000 > > -#define CONFIG_UART_BASE_CLOCK 25804800 > - > static int mvebu_serial_putc(struct udevice *dev, const char ch) > { > struct mvebu_plat *plat = dev_get_plat(dev); > @@ -75,12 +74,15 @@ static int mvebu_serial_setbrg(struct udevice *dev, int baudrate) > { > struct mvebu_plat *plat = dev_get_plat(dev); > void __iomem *base = plat->base; > + u32 parent_rate, divider; > > /* > * Calculate divider > * baudrate = clock / 16 / divider > */ > - writel(CONFIG_UART_BASE_CLOCK / baudrate / 16, base + UART_BAUD_REG); > + parent_rate = get_ref_clk() * 1000000; > + divider = DIV_ROUND_CLOSEST(parent_rate, baudrate * 16); > + writel(divider, base + UART_BAUD_REG); > > /* > * Set Programmable Oversampling Stack to 0, > @@ -144,6 +146,7 @@ U_BOOT_DRIVER(serial_mvebu) = { > static inline void _debug_uart_init(void) > { > void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; > + u32 baudrate, parent_rate, divider; > > /* reset FIFOs */ > writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET, > @@ -156,7 +159,10 @@ static inline void _debug_uart_init(void) > * Calculate divider > * baudrate = clock / 16 / divider > */ > - writel(CONFIG_UART_BASE_CLOCK / 115200 / 16, base + UART_BAUD_REG); > + baudrate = 115200; > + parent_rate = get_ref_clk() * 1000000; > + divider = DIV_ROUND_CLOSEST(parent_rate, baudrate * 16); > + writel(divider, base + UART_BAUD_REG); > > /* > * Set Programmable Oversampling Stack to 0, > Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de