From: Stefan Agner <stefan@agner.ch>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v1 1/3] ddr: vybrid: Add DDRMC calibration related registers (DQS to DQ)
Date: Mon, 03 Dec 2018 16:39:38 +0100 [thread overview]
Message-ID: <f35377014383ed1368737b5e61a80534@agner.ch> (raw)
In-Reply-To: <20181202204222.30732-2-lukma@denx.de>
On 02.12.2018 21:42, Lukasz Majewski wrote:
> This commit provides extra defines needed for DDR memory controller
> calibration (read leveling performing).
>
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> ---
>
> arch/arm/include/asm/arch-vf610/imx-regs.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
> b/arch/arm/include/asm/arch-vf610/imx-regs.h
> index 08ba8e94f8..f477e414f9 100644
> --- a/arch/arm/include/asm/arch-vf610/imx-regs.h
> +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
> @@ -206,11 +206,17 @@
> #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
> #define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
> #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
> +#define DDRMC_CR93_SW_LVL_MODE(v) (((v) & 0x3) << 8)
> +#define DDRMC_CR93_SWLVL_LOAD BIT(16)
> +#define DDRMC_CR93_SWLVL_START BIT(24)
> +#define DDRMC_CR93_SWLVL_EXIT BIT(0)
SWLVL_EXIT is in CR94.
With that fixed, looks good.
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
--
Stefan
> +#define DDRMC_CR94_SWLVL_OP_DONE BIT(8)
> #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8)
> #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f)
> #define DDRMC_CR97_WRLVL_EN (1 << 24)
> #define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff)
> #define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff)
> +#define DDRMC_CR101_PHY_RDLVL_EDGE BIT(24)
> #define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16)
> #define DDRMC_CR102_RDLVL_REG_EN (1 << 8)
> #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8)
next prev parent reply other threads:[~2018-12-03 15:39 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-02 20:42 [U-Boot] [PATCH v1 0/3] ddr: vybrid: Support for vf610 built-in DDR3 memory calibration Lukasz Majewski
2018-12-02 20:42 ` [U-Boot] [PATCH v1 1/3] ddr: vybrid: Add DDRMC calibration related registers (DQS to DQ) Lukasz Majewski
2018-12-03 15:39 ` Stefan Agner [this message]
2018-12-02 20:42 ` [U-Boot] [PATCH v1 2/3] ddr: vybrid: Provide code to perform on-boot calibration Lukasz Majewski
2018-12-03 15:53 ` Stefan Agner
2018-12-03 17:06 ` Lukasz Majewski
2018-12-02 20:42 ` [U-Boot] [PATCH v1 3/3] ddr: vybrid: Add calibration code to memory controler's (DDRMC) setup code Lukasz Majewski
2018-12-03 15:55 ` Stefan Agner
2018-12-03 17:07 ` Lukasz Majewski
2018-12-02 21:22 ` [U-Boot] [PATCH v1 0/3] ddr: vybrid: Support for vf610 built-in DDR3 memory calibration Fabio Estevam
2018-12-02 22:12 ` Lukasz Majewski
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