Re: [PATCH v2 0/1] hw/arm/aspeed: Add Fuji machine type

From: "Cédric Le Goater" <clg@kaod.org>
To: <pdel@fb.com>
Cc: patrick@stwcx.xyz, qemu-arm@nongnu.org, joel@jms.id.au,
	qemu-devel@nongnu.org
Subject: Re: [PATCH v2 0/1] hw/arm/aspeed: Add Fuji machine type
Date: Fri, 3 Sep 2021 11:54:21 +0200	[thread overview]
Message-ID: <f380c5b5-a472-d41e-7821-4155113bdbc0@kaod.org> (raw)
In-Reply-To: <20210903082027.704397-1-pdel@fb.com>

On 9/3/21 10:20 AM, pdel@fb.com wrote:
> From: Peter Delevoryas <pdel@fb.com>
> 
> v2:
>   - Added supported i2c devices (lm75, tmp75, tmp422, 24c64, 24c02)
>   - Switched flash model to mx66l1g45g (128MB)
>   - Completely separated fuji class definition from ast2600-evb
>   - Removed image acceptance test
> 
> Link: https://github.com/peterdelevoryas/qemu/tree/aspeed-next
> 
> I investigated the boot issues pointed out in the previous submission a
> little, let me know if any of these are blockers for this patch:
> 
>>> Is the Fuji using the Aspeed RTC ?
>>>
>>> hwclock: ioctl(RTC_RD_TIME) to /dev/rtc0 to read the time failed: Invalid argument
> 
> I don't understand exactly what's going on here, but running "hwclock --get"
> and "hwclock --set --date 2021-01-01" both seem to work fine after booting,
> so I think the Aspeed RTC is setup correctly and working. As far as I know
> Fuji uses it, but I'm not really sure.

QEMU doesn't model the SoC RTC. Something to add on the TODO list.

>>>
>>> That's a weird MMIO range for the ADC ?
>>>
>>> [   42.856022] aspeed_adc: probe of 1e6e9100.adc failed with error -110
> 
> I think there's 2 ADC's in the DTS, one at 1e6e9000 and one at 1e6e9100, but
> I don't see explicit support for the Aspeed ADC in hw/adc/, and I'm not sure
> that any of the existing emulators would work.

The ADC model is not merged yet. It's aging in the aspeed-6.2 branch. 

The Ast2600 has indeed 2 ADCs. We missed that in QEMU.

>>>
>>> And that's unexected :
>>>
>>> Error: unable to disable the 2nd watchdog: FMC_WDT2=0xFFFFFFFF
> 
> So, this is an OpenBMC script trying to disable the alternate boot watchdog
> by writing 0x0 to 0x1e620064 (Aspeed SMC 0x64). It checks the register after
> attempting to write it and prints this error message if the lowest bit is
> not cleared. Since the Aspeed SMC is not simulating this register, I don't
> think aspeed_smc_write() does anything, and aspeed_smc_read() returns -1. I
> also testetd changing -1 to 0xdeadbeef locally to confirm.

I see. QEMU is also missing support. 

> https://github.com/facebook/openbmc/blob/helium/common/recipes-utils/openbmc-utils/files/aspeed-g6/disable_watchdog.sh
> 
> Let me know if there's anything else I should look into. I'm still planning
> on submitting an image acceptance test for this too, but as a separate
> patch.

yes. 

> I've also included a boot log at the end of this cover letter for
> reference.

Thanks

C. 

> Thanks,
> Peter
> 
> Peter Delevoryas (1):
>   hw/arm/aspeed: Add Fuji machine type
> 
>  hw/arm/aspeed.c | 112 ++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 112 insertions(+)
> 