From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C8F2C433F5 for ; Fri, 8 Oct 2021 06:28:10 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C7EED60F94 for ; Fri, 8 Oct 2021 06:28:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C7EED60F94 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 629DA82952; Fri, 8 Oct 2021 08:28:07 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1633674488; bh=/pxnTQjaz51pWnXaBWUEOzU3Yhzw3XtfW9cCJpqrIL8=; h=Subject:To:Cc:References:From:Date:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=NARXFbm/GqZbB5DlvQ5GbOPsqRwzhSxIVPNoQ/mbMMmRQWg0Ed7ZJnhvdH9kffRxA 3w5noJJQ/od4N6K0MGTPIipvCVnirNMvbCeMFPRbOSzH4smUye4DmSD9MUA+qMSHys p+FAlyLBAaFA+XWIwDMpoxsvIY2TWAAiqlOhurWA3ZyydIf84JcUVrN3F9vlFPEq89 bAqnWCqjuF6F6bVVxwhl55w4uzKQKKsioR4hZlPYS/kg7D1arscfi+oynUCVfo5VQ8 hDg5Rz2XnWODWEvsQbsjl/HtsNnMlC2NS98pH5siIWJV4yxcFwr3fNvibUB4ZQtyeY rqwDCAyU16HSg== Received: by phobos.denx.de (Postfix, from userid 109) id 3AE1582006; Fri, 8 Oct 2021 08:28:05 +0200 (CEST) Received: from mout-u-205.mailbox.org (mout-u-205.mailbox.org [91.198.250.254]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C446582006 for ; Fri, 8 Oct 2021 08:28:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp102.mailbox.org (smtp102.mailbox.org [80.241.60.233]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-205.mailbox.org (Postfix) with ESMTPS id 4HQdXw57tdzQkwj; Fri, 8 Oct 2021 08:28:00 +0200 (CEST) Subject: Re: [PATCH u-boot-marvell 4/9] arm: mvebu: a38x: serdes: Don't overwrite read-only SAR PCIe registers To: =?UTF-8?Q?Marek_Beh=c3=ban?= Cc: u-boot@lists.denx.de, pali@kernel.org References: <20210924205922.25432-1-marek.behun@nic.cz> <20210924205922.25432-5-marek.behun@nic.cz> From: Stefan Roese Message-ID: Date: Fri, 8 Oct 2021 08:27:57 +0200 MIME-Version: 1.0 In-Reply-To: <20210924205922.25432-5-marek.behun@nic.cz> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: de-DE Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: E9FFA270 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 24.09.21 22:59, Marek Behún wrote: > From: Pali Rohár > > Device/Port Type bits of PCIe Root Port PCI Express Capabilities Register > are read-only SAR registers and are initialized according to current mode > configured by PCIe controller. Changing PCIe controller mode (from Root > Complex mode to Endpoint mode or the other way) is possible via PCI > Express Control Register (offset 0x41A00), bit 1 (ConfRoot Complex). This > has to be done in PCIe controller driver (in our case pci_mvebu.c). Note > that default mode is Root Complex. > > Maximum Link Speed bits of PCIe Root Port Link Capabilities Register are > platform specific and overwriting them does not make sense. They are set by > PCIe controller according to current SerDes configuration. For A38x it is > 5.0 GT/s if SerDes supports appropriate speed. > > Maximum Link Width bits of PCIe Root Port Link Capabilities Register are > read-only SAR registers, but unfortunately if this is not set correctly > here, then access PCI config space of the endpoint card behind this Root > Port does not work. > > Signed-off-by: Pali Rohár > Reviewed-by: Marek Behún Reviewed-by: Stefan Roese Thanks, Stefan > --- > arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 22 ---------- > arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 4 ++ > .../serdes/a38x/high_speed_env_spec.c | 40 +++++++------------ > 3 files changed, 19 insertions(+), 47 deletions(-) > > diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c > index 0eb31d589c..7c18df8113 100644 > --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c > +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c > @@ -28,28 +28,6 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count) > > DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n"); > > - for (idx = 0; idx < count; idx++) { > - serdes_type = serdes_map[idx].serdes_type; > - /* configuration for PEX only */ > - if ((serdes_type != PEX0) && (serdes_type != PEX1) && > - (serdes_type != PEX2) && (serdes_type != PEX3)) > - continue; > - > - if ((serdes_type != PEX0) && > - ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) || > - (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) { > - /* for PEX by4 - relevant for the first port only */ > - continue; > - } > - > - /* Set Device/Port Type to RootComplex */ > - pex_idx = serdes_type - PEX0; > - tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx)); > - tmp &= ~(0xf << 20); > - tmp |= (0x4 << 20); > - reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp); > - } > - > tmp = reg_read(SOC_CONTROL_REG1); > tmp &= ~0x03; > > diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h > index a882d24208..5d70166fc5 100644 > --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h > +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h > @@ -6,8 +6,12 @@ > #ifndef _CTRL_PEX_H > #define _CTRL_PEX_H > > +#include > #include "high_speed_env_spec.h" > > +/* Direct access to PEX0 Root Port's PCIe Capability structure */ > +#define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60) > + > /* Sample at Reset */ > #define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4)) > > diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c > index 09192acef2..a712fa8994 100644 > --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c > +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c > @@ -1714,7 +1714,7 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, > (serdes_mode == PEX_END_POINT_X1); > pex_idx = serdes_type - PEX0; > > - if ((is_pex_by1 == 1) || (serdes_type == PEX0)) { > + if (serdes_type == PEX0) { > /* For PEX by 4, init only the PEX 0 */ > reg_data = reg_read(SOC_CONTROL_REG1); > if (is_pex_by1 == 1) > @@ -1723,30 +1723,20 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, > reg_data &= ~0x4000; > reg_write(SOC_CONTROL_REG1, reg_data); > > - /* Set Maximum Link Width to X1 or X4 */ > - reg_data = reg_read(PEX_CFG_DIRECT_ACCESS( > - pex_idx, > - PEX_LINK_CAPABILITY_REG)); > - reg_data &= ~0x3f0; > - if (is_pex_by1 == 1) > - reg_data |= 0x10; > - else > - reg_data |= 0x40; > - reg_write(PEX_CFG_DIRECT_ACCESS( > - pex_idx, > - PEX_LINK_CAPABILITY_REG), > - reg_data); > - > - /* Set Maximum Link Speed to 5 GT/s */ > - reg_data = reg_read(PEX_CFG_DIRECT_ACCESS( > - pex_idx, > - PEX_LINK_CAPABILITY_REG)); > - reg_data &= ~0xf; > - reg_data |= 0x2; > - reg_write(PEX_CFG_DIRECT_ACCESS( > - pex_idx, > - PEX_LINK_CAPABILITY_REG), > - reg_data); > + /* > + * Set Maximum Link Width to X1 or X4 in Root > + * Port's PCIe Link Capability register. > + * This register is read-only but if is not set > + * correctly then access to PCI config space of > + * endpoint card behind this Root Port does not > + * work. > + */ > + reg_data = reg_read(PEX0_RP_PCIE_CFG_OFFSET + > + PCI_EXP_LNKCAP); > + reg_data &= ~PCI_EXP_LNKCAP_MLW; > + reg_data |= (is_pex_by1 ? 1 : 4) << 4; > + reg_write(PEX0_RP_PCIE_CFG_OFFSET + > + PCI_EXP_LNKCAP, reg_data); > > /* > * Set Common Clock Configuration to indicates > Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de