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[50.195.43.97]) by smtp.gmail.com with ESMTPSA id o201sm3193720qke.31.2020.04.23.23.41.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Apr 2020 23:41:47 -0700 (PDT) Subject: Re: [PATCH tip/core/rcu 2/6] Documentation/memory-barriers.txt: ACCESS_ONCE() provides cache coherence To: "Paul E. McKenney" , "linux-kernel@vger.kernel.org" References: <1392672413-5114-2-git-send-email-paulmck () linux ! vnet ! ibm ! com> From: Jon Masters Organization: World Organi{s,z}ation of Broken Dreams Message-ID: Date: Thu, 23 Apr 2020 23:36:19 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <1392672413-5114-2-git-send-email-paulmck () linux ! vnet ! ibm ! com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Paul, On 2/17/14 4:26 PM, Paul E. McKenney wrote: > The ACCESS_ONCE() primitive provides cache coherence, but the > documentation does not clearly state this. This commit therefore upgrades > the documentation. > + In short, ACCESS_ONCE() provides "cache coherence" for accesses from > + multiple CPUs to a single variable. (ACCESS_ONCE is now READ_ONCE/WRITE_ONCE but the above added the original language around cache coherence) I would argue that we might want to avoid describing it in this manner. The hardware provides cache coherency in order to keep a single memory location coherent between multiple observers. These kernel macros only tell the compiler to perform the load once. They take advantage of the properties of coherence in the presence of multiple observers. Jon. -- Computer Architect