From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCF8FC433EF for ; Mon, 1 Nov 2021 23:56:12 +0000 (UTC) Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by mail.kernel.org (Postfix) with ESMTP id 5290060F56 for ; Mon, 1 Nov 2021 23:56:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5290060F56 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dpdk.org Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8480F4069F; Tue, 2 Nov 2021 00:56:11 +0100 (CET) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 0C1FA4068F for ; Tue, 2 Nov 2021 00:56:09 +0100 (CET) X-IronPort-AV: E=McAfee;i="6200,9189,10155"; a="218058077" X-IronPort-AV: E=Sophos;i="5.87,201,1631602800"; d="scan'208";a="218058077" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2021 16:56:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,201,1631602800"; d="scan'208";a="727595282" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmsmga006.fm.intel.com with ESMTP; 01 Nov 2021 16:56:07 -0700 Received: from shsmsx602.ccr.corp.intel.com (10.109.6.142) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Mon, 1 Nov 2021 16:56:06 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX602.ccr.corp.intel.com (10.109.6.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 2 Nov 2021 07:56:04 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2242.012; Tue, 2 Nov 2021 07:56:04 +0800 From: "Zhang, Qi Z" To: "Guo, Junfeng" , "Wu, Jingjing" , "Xing, Beilei" CC: "dev@dpdk.org" , "Yigit, Ferruh" , "Xu, Ting" Thread-Topic: [PATCH v8 4/4] net/ice: enable protocol agnostic flow offloading in FDIR Thread-Index: AQHXzvuvANhRh1Xr/ke19ACn7vuEjavvVMrg Date: Mon, 1 Nov 2021 23:56:04 +0000 Message-ID: References: <20211028091346.1674650-5-junfeng.guo@intel.com> <20211101083612.2380503-1-junfeng.guo@intel.com> <20211101083612.2380503-5-junfeng.guo@intel.com> In-Reply-To: <20211101083612.2380503-5-junfeng.guo@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.6.200.16 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v8 4/4] net/ice: enable protocol agnostic flow offloading in FDIR X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Guo, Junfeng > Sent: Monday, November 1, 2021 4:36 PM > To: Zhang, Qi Z ; Wu, Jingjing ; > Xing, Beilei > Cc: dev@dpdk.org; Yigit, Ferruh ; Xu, Ting > ; Guo, Junfeng > Subject: [PATCH v8 4/4] net/ice: enable protocol agnostic flow offloading= in > FDIR >=20 > Protocol agnostic flow offloading in Flow Director is enabled by this pat= ch > based on the Parser Library, using existing rte_flow raw API. >=20 > Note that the raw flow requires: > 1. byte string of raw target packet bits. > 2. byte string of mask of target packet. >=20 > Here is an example: > FDIR matching ipv4 dst addr with 1.2.3.4 and redirect to queue 3: >=20 > flow create 0 ingress pattern raw \ > pattern spec \ > 0000000000000000000000000800450000140000400040100000000000000 > 1020304 \ pattern mask \ > 000000000000000000000000000000000000000000000000000000000000ff > ffffff \ / end actions queue index 3 / mark id 3 / end >=20 > Note that mask of some key bits (e.g., 0x0800 to indicate ipv4 proto) is > optional in our cases. To avoid redundancy, we just omit the mask of 0x08= 00 > (with 0xFFFF) in the mask byte string example. The prefix '0x' for the sp= ec and > mask byte (hex) strings are also omitted here. >=20 > Signed-off-by: Junfeng Guo > --- > doc/guides/rel_notes/release_21_11.rst | 1 + > drivers/net/ice/ice_ethdev.h | 14 ++ > drivers/net/ice/ice_fdir_filter.c | 235 +++++++++++++++++++++++++ > drivers/net/ice/ice_generic_flow.c | 7 + > drivers/net/ice/ice_generic_flow.h | 3 + > 5 files changed, 260 insertions(+) >=20 > diff --git a/doc/guides/rel_notes/release_21_11.rst > b/doc/guides/rel_notes/release_21_11.rst > index 98d50a160b..36fdee0a98 100644 > --- a/doc/guides/rel_notes/release_21_11.rst > +++ b/doc/guides/rel_notes/release_21_11.rst > @@ -167,6 +167,7 @@ New Features >=20 > * **Updated Intel ice driver.** >=20 > + * Added protocol agnostic flow offloading support in Flow Director. > * Added 1PPS out support by a devargs. > * Added IPv4 and L4 (TCP/UDP/SCTP) checksum hash support in RSS flow. > * Added DEV_RX_OFFLOAD_TIMESTAMP support. > diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h = index > 0e42c4c063..bbfeb0cc23 100644 > --- a/drivers/net/ice/ice_ethdev.h > +++ b/drivers/net/ice/ice_ethdev.h > @@ -318,6 +318,11 @@ struct ice_fdir_filter_conf { > uint64_t input_set_o; /* used for non-tunnel or tunnel outer fields */ > uint64_t input_set_i; /* only for tunnel inner fields */ > uint32_t mark_flag; > + > + struct ice_parser_profile *prof; > + const u8 *pkt_buf; > + bool parser_ena; > + u8 pkt_len; > }; >=20 > #define ICE_MAX_FDIR_FILTER_NUM (1024 * 16) > @@ -487,6 +492,14 @@ struct ice_devargs { > uint8_t pps_out_ena; > }; >=20 > +/** > + * Structure to store fdir fv entry. > + */ > +struct ice_fdir_prof_info { > + struct ice_parser_profile prof; > + u64 fdir_actived_cnt; > +}; > + > /** > * Structure to store private data for each PF/VF instance. > */ > @@ -510,6 +523,7 @@ struct ice_adapter { > struct rte_timecounter tx_tstamp_tc; > bool ptp_ena; > uint64_t time_hw; > + struct ice_fdir_prof_info fdir_prof_info[ICE_MAX_PTGS]; > #ifdef RTE_ARCH_X86 > bool rx_use_avx2; > bool rx_use_avx512; > diff --git a/drivers/net/ice/ice_fdir_filter.c b/drivers/net/ice/ice_fdir= _filter.c > index bd627e3aa8..888f0dea6d 100644 > --- a/drivers/net/ice/ice_fdir_filter.c > +++ b/drivers/net/ice/ice_fdir_filter.c > @@ -107,6 +107,7 @@ > ICE_INSET_NAT_T_ESP_SPI) >=20 > static struct ice_pattern_match_item ice_fdir_pattern_list[] =3D { > + {pattern_raw, ICE_INSET_NONE, > ICE_INSET_NONE, ICE_INSET_NONE}, > {pattern_ethertype, ICE_FDIR_INSET_ETH, > ICE_INSET_NONE, ICE_INSET_NONE}, > {pattern_eth_ipv4, ICE_FDIR_INSET_ETH_IPV4, > ICE_INSET_NONE, ICE_INSET_NONE}, > {pattern_eth_ipv4_udp, ICE_FDIR_INSET_ETH_IPV4_UDP, > ICE_INSET_NONE, ICE_INSET_NONE}, > @@ -1188,6 +1189,24 @@ ice_fdir_is_tunnel_profile(enum > ice_fdir_tunnel_type tunnel_type) > return 0; > } >=20 > +static int > +ice_fdir_add_del_raw(struct ice_pf *pf, > + struct ice_fdir_filter_conf *filter, > + bool add) > +{ > + struct ice_hw *hw =3D ICE_PF_TO_HW(pf); > + > + unsigned char *pkt =3D (unsigned char *)pf->fdir.prg_pkt; > + rte_memcpy(pkt, filter->pkt_buf, filter->pkt_len); > + > + struct ice_fltr_desc desc; > + memset(&desc, 0, sizeof(desc)); > + filter->input.comp_report =3D ICE_FXD_FLTR_QW0_COMP_REPORT_SW; > + ice_fdir_get_prgm_desc(hw, &filter->input, &desc, add); > + > + return ice_fdir_programming(pf, &desc); } > + > static int > ice_fdir_add_del_filter(struct ice_pf *pf, > struct ice_fdir_filter_conf *filter, @@ -1303,6 +1322,72 @@ > ice_fdir_create_filter(struct ice_adapter *ad, > struct ice_fdir_fltr_pattern key; > bool is_tun; > int ret; > + int i; > + > + if (filter->parser_ena) { > + struct ice_hw *hw =3D ICE_PF_TO_HW(pf); > + > + int id =3D ice_find_first_bit(filter->prof->ptypes, UINT16_MAX); > + int ptg =3D hw->blk[ICE_BLK_FD].xlt1.t[id]; > + u16 ctrl_vsi =3D pf->fdir.fdir_vsi->idx; > + u16 main_vsi =3D pf->main_vsi->idx; > + bool fv_found =3D false; > + > + struct ice_fdir_prof_info *pi =3D &ad->fdir_prof_info[ptg]; > + if (pi->fdir_actived_cnt !=3D 0) { > + for (i =3D 0; i < ICE_MAX_FV_WORDS; i++) > + if (pi->prof.fv[i].proto_id !=3D > + filter->prof->fv[i].proto_id || > + pi->prof.fv[i].offset !=3D > + filter->prof->fv[i].offset || > + pi->prof.fv[i].msk !=3D > + filter->prof->fv[i].msk) > + break; > + if (i =3D=3D ICE_MAX_FV_WORDS) { > + fv_found =3D true; > + pi->fdir_actived_cnt++; > + } > + } > + > + if (!fv_found) { > + ret =3D ice_flow_set_hw_prof(hw, main_vsi, ctrl_vsi, > + filter->prof, ICE_BLK_FD); > + if (ret) > + return -rte_errno; > + } > + > + ret =3D ice_fdir_add_del_raw(pf, filter, true); > + if (ret) > + return -rte_errno; > + > + if (!fv_found) { > + for (i =3D 0; i < filter->prof->fv_num; i++) { > + pi->prof.fv[i].proto_id =3D > + filter->prof->fv[i].proto_id; > + pi->prof.fv[i].offset =3D > + filter->prof->fv[i].offset; > + pi->prof.fv[i].spec =3D filter->prof->fv[i].spec; > + pi->prof.fv[i].msk =3D filter->prof->fv[i].msk; > + } > + pi->fdir_actived_cnt =3D 1; > + } > + > + if (filter->mark_flag =3D=3D 1) > + ice_fdir_rx_parsing_enable(ad, 1); > + > + entry =3D rte_zmalloc("fdir_entry", sizeof(*entry), 0); > + if (!entry) > + return -rte_errno; > + > + rte_memcpy(entry, filter, sizeof(*filter)); > + > + filter->prof =3D NULL; > + filter->pkt_buf =3D NULL; Should we free filter here? as a copy of it already be assigned to flow->ru= le. Actually the filter is assigned by meta, and it is created during parse_pat= tern_action, and assume to be freed in create_filter. Or we can assign meta to flow->rule directly, then we only need to free it = during destroy. =20 > + > + flow->rule =3D entry; > + > + return 0; > + } >=20 > ice_fdir_extract_fltr_key(&key, filter); > node =3D ice_fdir_entry_lookup(fdir_info, &key); @@ -1397,6 +1482,49 > @@ ice_fdir_destroy_filter(struct ice_adapter *ad, >=20 > filter =3D (struct ice_fdir_filter_conf *)flow->rule; >=20 > + if (filter->parser_ena) { > + struct ice_hw *hw =3D ICE_PF_TO_HW(pf); > + > + int id =3D ice_find_first_bit(filter->prof->ptypes, UINT16_MAX); > + int ptg =3D hw->blk[ICE_BLK_FD].xlt1.t[id]; > + u16 ctrl_vsi =3D pf->fdir.fdir_vsi->idx; > + u16 main_vsi =3D pf->main_vsi->idx; > + u16 vsi_num; > + > + ret =3D ice_fdir_add_del_raw(pf, filter, false); > + if (ret) > + return -rte_errno; > + > + struct ice_fdir_prof_info *pi =3D &ad->fdir_prof_info[ptg]; > + if (pi->fdir_actived_cnt !=3D 0) { > + pi->fdir_actived_cnt--; > + if (!pi->fdir_actived_cnt) { > + vsi_num =3D ice_get_hw_vsi_num(hw, ctrl_vsi); > + ret =3D ice_rem_prof_id_flow(hw, ICE_BLK_FD, > + vsi_num, id); > + if (ret) > + return -rte_errno; > + > + vsi_num =3D ice_get_hw_vsi_num(hw, main_vsi); > + ret =3D ice_rem_prof_id_flow(hw, ICE_BLK_FD, > + vsi_num, id); > + if (ret) > + return -rte_errno; > + } > + } > + > + if (filter->mark_flag =3D=3D 1) > + ice_fdir_rx_parsing_enable(ad, 0); > + > + flow->rule =3D NULL; > + filter->prof =3D NULL; > + filter->pkt_buf =3D NULL; Should we free the pkt_buf and prof before assign them to NULL. They are created during parse_pattern but never be freed before. > + > + rte_free(filter); > + > + return 0; > + } > +