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From: "Christian König" <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Shaoyun Liu <Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org>,
	amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 2/5] drm/amdgpu: Use the dynamic IP based offset for register access for SOC15
Date: Wed, 29 Nov 2017 21:05:09 +0100	[thread overview]
Message-ID: <f42f643b-2bbe-dc05-6424-acd0ea07a1be@gmail.com> (raw)
In-Reply-To: <1511982570-8702-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org>

Am 29.11.2017 um 20:09 schrieb Shaoyun Liu:
> Change-Id: I29f33ee3b4bbd6737f3426385a9e8452fb528a67
> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c    | 21 +++----------------
>   drivers/gpu/drm/amd/amdgpu/soc15_common.h | 34 ++++++++-----------------------
>   2 files changed, 11 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 4c55f21..e324c66 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -107,24 +107,9 @@
>   	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00000002
>   };
>   
> -static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset)
> -{
> -	u32 base = 0;
> -
> -	switch (instance) {
> -	case 0:
> -		base = SDMA0_BASE.instance[0].segment[0];
> -		break;
> -	case 1:
> -		base = SDMA1_BASE.instance[0].segment[0];
> -		break;
> -	default:
> -		BUG();
> -		break;
> -	}
> -
> -	return base + internal_offset;
> -}
> +#define sdma_v4_0_get_reg_offset(inst, offset) ( 0 == inst ? \
> +	(adev->reg_offset[SDMA0_HWIP][0][0] + offset) : \
> +	(adev->reg_offset[SDMA1_HWIP][0][0] + offset))

Please keep that a function, not a define.

Apart from that looks really good to me.

Christian.

>   
>   static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
>   {
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> index 7a8e4e28..62a6e21 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> @@ -54,42 +54,24 @@ struct nbio_pcie_index_data {
>                                                               (ip##_BASE__INST##inst##_SEG4 + reg)))))
>   
>   #define WREG32_FIELD15(ip, idx, reg, field, val)	\
> -	WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
> +	WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,	\
> +	(RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg)	\
> +	& ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
>   
>   #define RREG32_SOC15(ip, inst, reg) \
> -	RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
> -		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> -		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> -		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> -		(ip##_BASE__INST##inst##_SEG4 + reg))))))
> +	RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>   
>   #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
> -	RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
> -		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> -		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> -		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> -		(ip##_BASE__INST##inst##_SEG4 + reg))))) + offset)
> +	RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
>   
>   #define WREG32_SOC15(ip, inst, reg, value) \
> -	WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
> -		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> -		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> -		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> -		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
> +	WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
>   
>   #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
> -	WREG32_NO_KIQ( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
> -		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> -		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> -		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> -		(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
> +	WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
>   
>   #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
> -	WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
> -		(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> -		(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> -		(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> -		(ip##_BASE__INST##inst##_SEG4 + reg))))) + offset, value)
> +	WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
>   
>   #endif
>   

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  parent reply	other threads:[~2017-11-29 20:05 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-29 19:09 [PATCH 2/5] drm/amdgpu: Use the dynamic IP based offset for register access for SOC15 Shaoyun Liu
     [not found] ` <1511982570-8702-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org>
2017-11-29 20:05   ` Christian König [this message]
     [not found]     ` <f42f643b-2bbe-dc05-6424-acd0ea07a1be-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-11-29 20:38       ` Liu, Shaoyun
     [not found]         ` <DM5PR12MB11790800E5624203E667AFC9F43B0-2J9CzHegvk8p/eksZXEfgQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-11-30  8:33           ` Christian König
2017-11-30 22:53 Shaoyun Liu
     [not found] ` <1512082425-25917-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org>
2017-12-01  8:22   ` Christian König

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