From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43)
	id 1Ih34J-0005Or-Kc
	for qemu-devel@nongnu.org; Sun, 14 Oct 2007 08:59:43 -0400
Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43)
	id 1Ih34H-0005Ob-1P
	for qemu-devel@nongnu.org; Sun, 14 Oct 2007 08:59:42 -0400
Received: from [199.232.76.173] (helo=monty-python.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1Ih34G-0005OY-Sl
	for qemu-devel@nongnu.org; Sun, 14 Oct 2007 08:59:40 -0400
Received: from nf-out-0910.google.com ([64.233.182.190])
	by monty-python.gnu.org with esmtp (Exim 4.60)
	(envelope-from <blauwirbel@gmail.com>) id 1Ih34G-00038n-F3
	for qemu-devel@nongnu.org; Sun, 14 Oct 2007 08:59:40 -0400
Received: by nf-out-0910.google.com with SMTP id 30so1167149nfu
	for <qemu-devel@nongnu.org>; Sun, 14 Oct 2007 05:59:39 -0700 (PDT)
Message-ID: <f43fc5580710140559y5861c095i14101be4340348cc@mail.gmail.com>
Date: Sun, 14 Oct 2007 15:59:38 +0300
From: "Blue Swirl" <blauwirbel@gmail.com>
Subject: Re: [Qemu-devel] RFC: reverse-endian softmmu memory accessors
In-Reply-To: <1192362549.9976.389.camel@rapid>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit
Content-Disposition: inline
References: <1192362549.9976.389.camel@rapid>
Reply-To: qemu-devel@nongnu.org
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.gnu.org/pipermail/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: qemu-devel@nongnu.org

On 10/14/07, J. Mayer <l_indien@magic.fr> wrote:
> Here's an updated version of the patch against current CVS.
> This patches provides reverse-endian, little-endian and big-endian
> memory accessors, available with and without softmmu. It also provides
> an IO_MEM_REVERSE TLB flag to allow future support of per-page
> endianness control, which is required by some targets CPU emulations.
> Having reverse-endian memory accessors also make it possible to optimise
> reverse-endian memory access when the target CPU has dedicated
> instructions. For now, it includes optimisations for the PowerPC target.

This breaks Sparc32 softmmu, I get a black screen. Your changes to
target-sparc and hw/sun4m.c look fine, so the problem could be in IO?