From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MsfxN-0006Kt-2P for qemu-devel@nongnu.org; Tue, 29 Sep 2009 12:53:41 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MsfxI-0006FX-1b for qemu-devel@nongnu.org; Tue, 29 Sep 2009 12:53:40 -0400 Received: from [199.232.76.173] (port=47477 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MsfxH-0006FE-D5 for qemu-devel@nongnu.org; Tue, 29 Sep 2009 12:53:35 -0400 Received: from mx20.gnu.org ([199.232.41.8]:35539) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MsfIO-0008N6-S2 for qemu-devel@nongnu.org; Tue, 29 Sep 2009 12:11:21 -0400 Received: from mail-fx0-f214.google.com ([209.85.220.214]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MseSV-0001zZ-5L for qemu-devel@nongnu.org; Tue, 29 Sep 2009 11:17:43 -0400 Received: by fxm10 with SMTP id 10so1017113fxm.8 for ; Tue, 29 Sep 2009 08:15:41 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20090929145006.GA3301@redhat.com> References: <4ABF4110.80300@redhat.com> <4ABF52A5.5080409@redhat.com> <20090927120041.GB24031@redhat.com> <4ABF585D.7000201@redhat.com> <20090927140841.GA24769@redhat.com> <4ABF7359.8050404@redhat.com> <20090927142129.GA24851@redhat.com> <20090927142422.GB24851@redhat.com> <20090929145006.GA3301@redhat.com> From: Blue Swirl Date: Tue, 29 Sep 2009 18:15:21 +0300 Message-ID: Subject: Re: [Qemu-devel] Re: [PATCHv2] qemu: target library, use it in msix Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Avi Kivity , qemu-devel@nongnu.org On Tue, Sep 29, 2009 at 5:50 PM, Michael S. Tsirkin wrote: > On Sun, Sep 27, 2009 at 06:19:05PM +0300, Blue Swirl wrote: >> On Sun, Sep 27, 2009 at 5:24 PM, Michael S. Tsirkin wro= te: >> > On Sun, Sep 27, 2009 at 04:21:29PM +0200, Michael S. Tsirkin wrote: >> >> On Sun, Sep 27, 2009 at 04:14:49PM +0200, Avi Kivity wrote: >> >> > On 09/27/2009 04:08 PM, Michael S. Tsirkin wrote: >> >> >> >> >> >> >> >> >>>> In practice, the only user is now msix and it does not. =C2=A0It= has 0x1000 >> >> >>>> as a constant parameter. =C2=A0For target_phys_addr_t users if w= e ever have >> >> >>>> them, we'll just add target_phys_page_align. Generally it's unus= ual for >> >> >>>> devices to care about size of target physical page. >> >> >>>> >> >> >>>> >> >> >>> I'd fill better with uint64_t, at least that won't truncate. >> >> >>> >> >> >> Doesn't naming it target_page_align32 address this concern? >> >> >> >> >> > >> >> > How can the caller (except in your special case) know if it has a >> >> > quantity that will fit in 32 bits? >> >> >> >> It's actually not unusual for devices to limit addressing to 32 bit, = whatever >> >> the bus supports. >> > >> > I would say that devices normally have a specific addressing, and shou= ld >> > not be using target specific types at all. =C2=A0This alignment to tar= get >> > page size is actually an unusual thing. >> >> Actually, AFAICT MSI-X spec (6.8.2, from the MSI entry in Wikipedia) >> only requires a QWORD alignment. There is some blurb about 4k >> alignment, but I think it only describes how software should use the >> structure. >> If this is the case, we could drop the whole target page >> stuff. > > The variable MSIX_PAGE_SIZE actually specifies the size of the space > allocated for MSIX in the memory region. =C2=A0Spec requires locating MSI= -X > tables in a 4K region separate from any other device register, so from > that point of view we could just have had > #define MSIX_PAGE_SIZE 0x1000 Can you cite the spec, I only found the QWORD stuff. > The main reason I round the space for MSI-X tables up to cpu page size, > is because I have to call cpu_register_physical_memory on it, which > requires that size is a multiple of target page size. There is no such requirement anymore (since r2868 in 2007), devices can register regions of arbitrary size and multiple devices can share a page.