From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.4 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35AA4C433DB for ; Thu, 4 Feb 2021 15:18:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DCF2964DDA for ; Thu, 4 Feb 2021 15:18:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DCF2964DDA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6252F6EDD2; Thu, 4 Feb 2021 15:18:37 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id A0D606EDD2 for ; Thu, 4 Feb 2021 15:18:35 +0000 (UTC) IronPort-SDR: 7ZOGf+dpNB5mmKqfrR/6iugYVOf0Ha+erXz4NQrQyhT+iVX1S6G31Guj4g7BvZ8jXEi7rchFxP VpTsIl5LqdOg== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="245329863" X-IronPort-AV: E=Sophos;i="5.79,401,1602572400"; d="scan'208";a="245329863" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 07:18:34 -0800 IronPort-SDR: f6NYoW/O54P4H5kL8cdZ08M8a9qD9/Z+aKSDRbjE9YtR7Xd6pHklmZXSuNg2SU6Lpd2WU66UbW GBhI0F/hILWA== X-IronPort-AV: E=Sophos;i="5.79,401,1602572400"; d="scan'208";a="393216165" Received: from acanalx-mobl.ger.corp.intel.com (HELO [10.249.32.114]) ([10.249.32.114]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 07:18:33 -0800 To: Chris Wilson , intel-gfx@lists.freedesktop.org References: <20210201085715.27435-1-chris@chris-wilson.co.uk> <20210201085715.27435-30-chris@chris-wilson.co.uk> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc Message-ID: Date: Thu, 4 Feb 2021 15:18:31 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.1 MIME-Version: 1.0 In-Reply-To: <20210201085715.27435-30-chris@chris-wilson.co.uk> Content-Language: en-US Subject: Re: [Intel-gfx] [PATCH 30/57] drm/i915: Move timeslicing flag to scheduler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 01/02/2021 08:56, Chris Wilson wrote: > Whether a scheduler chooses to implement timeslicing is up to it, and > not an underlying property of the HW engine. The scheduler does depend > on the HW supporting preemption. Therefore, continuing on the comment I made in the previous patch, if we had a helper with which engine would request scheduling (setting the tasklet), if it passed in a pointer to itself, scheduler would then be able to inspect if the engine supports preemption and so set its own internal flag. Makes sense? It would require something like: i915_sched_enable_scheduling(se, engine, tasklet) Or something like that if my memory still holds. Regards, Tvrtko > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/gt/intel_engine.h | 6 ++++++ > drivers/gpu/drm/i915/gt/intel_engine_types.h | 18 ++++-------------- > .../drm/i915/gt/intel_execlists_submission.c | 9 ++++++--- > drivers/gpu/drm/i915/gt/selftest_execlists.c | 2 +- > drivers/gpu/drm/i915/i915_scheduler_types.h | 10 ++++++++++ > 5 files changed, 27 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h > index 4f0163457aed..ca3a9cb06328 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -279,4 +279,10 @@ intel_engine_flush_scheduler(struct intel_engine_cs *engine) > i915_sched_flush(intel_engine_get_scheduler(engine)); > } > > +static inline bool > +intel_engine_has_timeslices(struct intel_engine_cs *engine) > +{ > + return i915_sched_has_timeslices(intel_engine_get_scheduler(engine)); > +} > + > #endif /* _INTEL_RINGBUFFER_H_ */ > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h > index a3024a0de1de..96a0aec29672 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h > @@ -442,11 +442,10 @@ struct intel_engine_cs { > #define I915_ENGINE_SUPPORTS_STATS BIT(1) > #define I915_ENGINE_HAS_PREEMPTION BIT(2) > #define I915_ENGINE_HAS_SEMAPHORES BIT(3) > -#define I915_ENGINE_HAS_TIMESLICES BIT(4) > -#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5) > -#define I915_ENGINE_IS_VIRTUAL BIT(6) > -#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7) > -#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8) > +#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4) > +#define I915_ENGINE_IS_VIRTUAL BIT(5) > +#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6) > +#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7) > unsigned int flags; > > /* > @@ -541,15 +540,6 @@ intel_engine_has_semaphores(const struct intel_engine_cs *engine) > return engine->flags & I915_ENGINE_HAS_SEMAPHORES; > } > > -static inline bool > -intel_engine_has_timeslices(const struct intel_engine_cs *engine) > -{ > - if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION)) > - return false; > - > - return engine->flags & I915_ENGINE_HAS_TIMESLICES; > -} > - > static inline bool > intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine) > { > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > index 3217cb4369ad..d4b6d262265a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > @@ -1023,7 +1023,7 @@ static bool needs_timeslice(const struct intel_engine_cs *engine, > { > const struct i915_sched *se = &engine->sched; > > - if (!intel_engine_has_timeslices(engine)) > + if (!i915_sched_has_timeslices(se)) > return false; > > /* If not currently active, or about to switch, wait for next event */ > @@ -2918,8 +2918,6 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) > engine->flags |= I915_ENGINE_HAS_SEMAPHORES; > if (can_preempt(engine)) { > engine->flags |= I915_ENGINE_HAS_PREEMPTION; > - if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION)) > - engine->flags |= I915_ENGINE_HAS_TIMESLICES; > } > } > > @@ -2927,6 +2925,11 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) > engine->emit_bb_start = gen8_emit_bb_start; > else > engine->emit_bb_start = gen8_emit_bb_start_noarb; > + > + if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION) && > + intel_engine_has_preemption(engine)) > + __set_bit(I915_SCHED_HAS_TIMESLICES_BIT, > + &engine->sched.flags); > } > > static void logical_ring_default_irqs(struct intel_engine_cs *engine) > diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c > index cfc0f4b9fbc5..147cbfd6dec0 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c > +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c > @@ -3825,7 +3825,7 @@ static unsigned int > __select_siblings(struct intel_gt *gt, > unsigned int class, > struct intel_engine_cs **siblings, > - bool (*filter)(const struct intel_engine_cs *)) > + bool (*filter)(struct intel_engine_cs *)) > { > unsigned int n = 0; > unsigned int inst; > diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h > index cb1eddb7edc8..dfb29b8c2bee 100644 > --- a/drivers/gpu/drm/i915/i915_scheduler_types.h > +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h > @@ -12,12 +12,14 @@ > #include > > #include "i915_priolist_types.h" > +#include "i915_utils.h" > > struct drm_printer; > struct i915_request; > > enum { > I915_SCHED_ACTIVE_BIT = 0, > + I915_SCHED_HAS_TIMESLICES_BIT, > }; > > /** > @@ -184,4 +186,12 @@ static inline bool i915_sched_is_active(const struct i915_sched *se) > return test_bit(I915_SCHED_ACTIVE_BIT, &se->flags); > } > > +static inline bool i915_sched_has_timeslices(const struct i915_sched *se) > +{ > + if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION)) > + return false; > + > + return test_bit(I915_SCHED_HAS_TIMESLICES_BIT, &se->flags); > +} > + > #endif /* _I915_SCHEDULER_TYPES_H_ */ > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx