From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77FB0C4332F for ; Wed, 5 Jan 2022 08:48:56 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3A29A830E5; Wed, 5 Jan 2022 09:48:54 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1641372534; bh=nc9fzrssOXVPQykN/+7R5LYUOQcuad8qbGkQWWAVT1M=; h=Date:Subject:To:Cc:References:From:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=SyBbq2MhIZvDhvXYTvwORTZc0iDK0Px7RKufTZT6sj9dGvLMZiQsbuch2wTYIQzjN He/3dogNJyofrcH1pdZ5Ghv2WE63sKli+xDaNi2oP3/DQ5/e2PovxEoemSt+AxGslB +0AFS+WEkIt/PVRCkPKVEd48yWI6N4AI9CkxjM80PF8wMzZHt9Ab2Xy4i/lgbejiQR knPe6u51VtTb14iSkLKGUPFSTOFPnXs5jXo65oE6+2N7FGs7rrzK8KP1/CI3AUX4bw f16E7wTuVK4iCh0mbY7hOA2jknA6E82xVJUw7gSaQSKOvo5GdTIKsn/bLuD31JnsWR 59pYbCUv4lCLw== Received: by phobos.denx.de (Postfix, from userid 109) id E778A80031; Wed, 5 Jan 2022 09:48:52 +0100 (CET) Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [91.198.250.252]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 16DD680031 for ; Wed, 5 Jan 2022 09:48:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp2.mailbox.org (unknown [91.198.250.124]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4JTNSK3qjNzQlJP; Wed, 5 Jan 2022 09:48:49 +0100 (CET) Message-ID: Date: Wed, 5 Jan 2022 09:48:43 +0100 MIME-Version: 1.0 Subject: Re: [PATCH u-boot-marvell] ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode determination Content-Language: en-US To: =?UTF-8?Q?Marek_Beh=c3=ban?= , Chris Packham , Chris Packham , Baruch Siach , =?UTF-8?Q?Pavol_Roh=c3=a1r?= , u-boot@lists.denx.de, Dirk Eibach , Mario Six , Dennis Gilmore , Kostya Porotchkin Cc: =?UTF-8?Q?Marek_Beh=c3=ban?= References: <20220104145749.18626-1-kabel@kernel.org> From: Stefan Roese In-Reply-To: <20220104145749.18626-1-kabel@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 1/4/22 15:57, Marek Behún wrote: > From: Marek Behún > > Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async > mode"), Asynchornous Mode was only used when the CPU Subsystem Clock > Options[4:0] field in the SAR1 register was set to value 0x13: CPU at > 2 GHz and DDR at 933 MHz. > > Then commit 4c289425752f ("mv_ddr: a38x: add support for ddr async > mode") added support for Asynchornous Modes with frequencies other than > 933 MHz (but at least 467 MHz), but the code it added to check for > whether Asynchornous Mode should be used is wrong: it checks whether the > frequency setting in board DDR topology map is set to value other than > MV_DDR_FREQ_SAR. > > Thus boards which define a specific value, greater than 400 MHz, for DDR > frequency in their board topology (e.g. Turris Omnia defines > MV_DDR_FREQ_800), are incorrectly put into Asynchornous Mode after that > commit. > > The A38x Functional Specification, section 10.12 DRAM Clocking, says: > In Synchornous mode, the DRAM and CPU clocks are edge aligned and run > in 1:2 or 1:3 CPU to DRAM frequency ratios. > > Change the check for whether Asynchornous Mode should be used according > to this explanation in Functional Specification. > > Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Thanks, Stefan > --- > A PR was also created for mv-ddr-marvell: > https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/35 > > Please test this. It is possible this commit will fix DDR training > issues, since commit 4c289425752f in mv-ddr-marvell started using > Asynchronous Mode where Synchronous Mode was used previously. > --- > drivers/ddr/marvell/a38x/mv_ddr_plat.c | 19 ++++++++----------- > 1 file changed, 8 insertions(+), 11 deletions(-) > > diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c > index faafc86ea2..7c7bce73a3 100644 > --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c > +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c > @@ -167,8 +167,6 @@ static u16 a38x_vco_freq_per_sar_ref_clk_40_mhz[] = { > }; > > > -static u32 async_mode_at_tf; > - > static u32 dq_bit_map_2_phy_pin[] = { > 1, 0, 2, 6, 9, 8, 3, 7, /* 0 */ > 8, 9, 1, 7, 2, 6, 3, 0, /* 1 */ > @@ -734,7 +732,8 @@ static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, > u32 divider = 0; > u32 sar_val, ref_clk_satr; > u32 async_val; > - u32 freq = mv_ddr_freq_get(frequency); > + u32 cpu_freq; > + u32 ddr_freq = mv_ddr_freq_get(frequency); > > if (if_id != 0) { > DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, > @@ -751,11 +750,14 @@ static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, > ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); > if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == > DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ) > - divider = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val] / freq; > + cpu_freq = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val]; > else > - divider = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val] / freq; > + cpu_freq = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val]; > + > + divider = cpu_freq / ddr_freq; > > - if ((async_mode_at_tf == 1) && (freq > 400)) { > + if (((cpu_freq % ddr_freq != 0) || (divider != 2 && divider != 3)) && > + (ddr_freq > 400)) { > /* Set async mode */ > dunit_write(0x20220, 0x1000, 0x1000); > dunit_write(0xe42f4, 0x200, 0x200); > @@ -869,8 +871,6 @@ int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr, > > int mv_ddr_early_init(void) > { > - struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); > - > /* FIXME: change this configuration per ddr type > * configure a380 and a390 to work with receiver odt timing > * the odt_config is defined: > @@ -882,9 +882,6 @@ int mv_ddr_early_init(void) > > mv_ddr_sw_db_init(0, 0); > > - if (tm->interface_params[0].memory_freq != MV_DDR_FREQ_SAR) > - async_mode_at_tf = 1; > - > return MV_OK; > } > > Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de