From: Harry Wentland <harry.wentland@amd.com> To: "Shankar, Uma" <uma.shankar@intel.com>, Pekka Paalanen <ppaalanen@gmail.com> Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>, "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>, "Modem, Bhanuprakash" <bhanuprakash.modem@intel.com> Subject: Re: [PATCH 01/21] drm: Add Enhanced Gamma and color lut range attributes Date: Fri, 4 Jun 2021 11:23:14 -0400 [thread overview] Message-ID: <f51cbf2d-69c7-bd7c-379a-a74724ad6d87@amd.com> (raw) In-Reply-To: <2015b90626a04860808eb02fa5f8a117@intel.com> On 2021-06-02 4:26 p.m., Shankar, Uma wrote: > > >> -----Original Message----- >> From: Pekka Paalanen <ppaalanen@gmail.com> >> Sent: Wednesday, June 2, 2021 3:04 PM >> To: Shankar, Uma <uma.shankar@intel.com> >> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Modem, >> Bhanuprakash <bhanuprakash.modem@intel.com> >> Subject: Re: [PATCH 01/21] drm: Add Enhanced Gamma and color lut range >> attributes >> >> On Tue, 1 Jun 2021 16:21:58 +0530 >> Uma Shankar <uma.shankar@intel.com> wrote: >> >>> Existing LUT precision structure is having only 16 bit precision. This >>> is not enough for upcoming enhanced hardwares and advance usecases >>> like HDR processing. Hence added a new structure with 32 bit precision >>> values. >>> >>> This also defines a new structure to define color lut ranges, along >>> with related macro definitions and enums. This will help describe >>> multi segmented lut ranges in the hardware. >>> >>> Signed-off-by: Uma Shankar <uma.shankar@intel.com> >>> --- >>> include/uapi/drm/drm_mode.h | 58 >>> +++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 58 insertions(+) >>> >>> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h >>> index 9b6722d45f36..d0ce48d2e732 100644 >>> --- a/include/uapi/drm/drm_mode.h >>> +++ b/include/uapi/drm/drm_mode.h >>> @@ -819,6 +819,64 @@ struct hdr_output_metadata { >>> }; >>> }; >>> >>> +/* >>> + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means >> the LUT >>> + * can be used for either purpose, but not simultaneously. To expose >>> + * modes that support gamma and degamma simultaneously the gamma mode >>> + * must declare distinct DRM_MODE_LUT_GAMMA and >> DRM_MODE_LUT_DEGAMMA >>> + * ranges. >>> + */ >>> +/* LUT is for gamma (after CTM) */ >>> +#define DRM_MODE_LUT_GAMMA BIT(0) >>> +/* LUT is for degamma (before CTM) */ #define DRM_MODE_LUT_DEGAMMA >>> +BIT(1) >>> +/* linearly interpolate between the points */ #define >>> +DRM_MODE_LUT_INTERPOLATE BIT(2) >>> +/* >>> + * the last value of the previous range is the >>> + * first value of the current range. >>> + */ >>> +#define DRM_MODE_LUT_REUSE_LAST BIT(3) >>> +/* the curve must be non-decreasing */ #define >>> +DRM_MODE_LUT_NON_DECREASING BIT(4) >>> +/* the curve is reflected across origin for negative inputs */ >>> +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5) >>> +/* the same curve (red) is used for blue and green channels as well >>> +*/ #define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6) >>> + >>> +struct drm_color_lut_range { >>> + /* DRM_MODE_LUT_* */ >>> + __u32 flags; >>> + /* number of points on the curve */ >>> + __u16 count; >>> + /* input/output bits per component */ >>> + __u8 input_bpc, output_bpc; >>> + /* input start/end values */ >>> + __s32 start, end; >>> + /* output min/max values */ >>> + __s32 min, max; >>> +}; >>> + >>> +enum lut_type { >> >> Unprefixed type name in UAPI headers is probably not a good idea. > > Ok, will rename these. > >>> + LUT_TYPE_DEGAMMA = 0, >>> + LUT_TYPE_GAMMA = 1, >>> +}; >> >> All the above stuff seems to be the same in your other patch series' >> patch "[PATCH 1/9] drm: Add gamma mode property". Is this series replacing the >> series "[PATCH 0/9] Enhance pipe color support for multi segmented luts" or what >> does this mean? > > The concept and idea is similar and the range definition is also common. But this series > focuses on plane color management while the other one is for pipe/crtc color features. > Hence separated and floated them as unique series for review. > Might be better in this case to combine both patchsets. It wasn't entirely clear to me whether I could base one patchset on top of the other (doesn't look like it) and what base to apply them on. I had success applying the plane stuff on drm-next and the crtc stuff on drm-intel. Harry > Regards, > Uma Shankar >> >> Thanks, >> pq >> >>> + >>> +/* >>> + * Creating 64 bit palette entries for better data >>> + * precision. This will be required for HDR and >>> + * similar color processing usecases. >>> + */ >>> +struct drm_color_lut_ext { >>> + /* >>> + * Data is U32.32 fixed point format. >>> + */ >>> + __u64 red; >>> + __u64 green; >>> + __u64 blue; >>> + __u64 reserved; >>> +}; >>> + >>> #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define >>> DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define >>> DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 >
WARNING: multiple messages have this Message-ID (diff)
From: Harry Wentland <harry.wentland@amd.com> To: "Shankar, Uma" <uma.shankar@intel.com>, Pekka Paalanen <ppaalanen@gmail.com> Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>, "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org> Subject: Re: [Intel-gfx] [PATCH 01/21] drm: Add Enhanced Gamma and color lut range attributes Date: Fri, 4 Jun 2021 11:23:14 -0400 [thread overview] Message-ID: <f51cbf2d-69c7-bd7c-379a-a74724ad6d87@amd.com> (raw) In-Reply-To: <2015b90626a04860808eb02fa5f8a117@intel.com> On 2021-06-02 4:26 p.m., Shankar, Uma wrote: > > >> -----Original Message----- >> From: Pekka Paalanen <ppaalanen@gmail.com> >> Sent: Wednesday, June 2, 2021 3:04 PM >> To: Shankar, Uma <uma.shankar@intel.com> >> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Modem, >> Bhanuprakash <bhanuprakash.modem@intel.com> >> Subject: Re: [PATCH 01/21] drm: Add Enhanced Gamma and color lut range >> attributes >> >> On Tue, 1 Jun 2021 16:21:58 +0530 >> Uma Shankar <uma.shankar@intel.com> wrote: >> >>> Existing LUT precision structure is having only 16 bit precision. This >>> is not enough for upcoming enhanced hardwares and advance usecases >>> like HDR processing. Hence added a new structure with 32 bit precision >>> values. >>> >>> This also defines a new structure to define color lut ranges, along >>> with related macro definitions and enums. This will help describe >>> multi segmented lut ranges in the hardware. >>> >>> Signed-off-by: Uma Shankar <uma.shankar@intel.com> >>> --- >>> include/uapi/drm/drm_mode.h | 58 >>> +++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 58 insertions(+) >>> >>> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h >>> index 9b6722d45f36..d0ce48d2e732 100644 >>> --- a/include/uapi/drm/drm_mode.h >>> +++ b/include/uapi/drm/drm_mode.h >>> @@ -819,6 +819,64 @@ struct hdr_output_metadata { >>> }; >>> }; >>> >>> +/* >>> + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means >> the LUT >>> + * can be used for either purpose, but not simultaneously. To expose >>> + * modes that support gamma and degamma simultaneously the gamma mode >>> + * must declare distinct DRM_MODE_LUT_GAMMA and >> DRM_MODE_LUT_DEGAMMA >>> + * ranges. >>> + */ >>> +/* LUT is for gamma (after CTM) */ >>> +#define DRM_MODE_LUT_GAMMA BIT(0) >>> +/* LUT is for degamma (before CTM) */ #define DRM_MODE_LUT_DEGAMMA >>> +BIT(1) >>> +/* linearly interpolate between the points */ #define >>> +DRM_MODE_LUT_INTERPOLATE BIT(2) >>> +/* >>> + * the last value of the previous range is the >>> + * first value of the current range. >>> + */ >>> +#define DRM_MODE_LUT_REUSE_LAST BIT(3) >>> +/* the curve must be non-decreasing */ #define >>> +DRM_MODE_LUT_NON_DECREASING BIT(4) >>> +/* the curve is reflected across origin for negative inputs */ >>> +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5) >>> +/* the same curve (red) is used for blue and green channels as well >>> +*/ #define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6) >>> + >>> +struct drm_color_lut_range { >>> + /* DRM_MODE_LUT_* */ >>> + __u32 flags; >>> + /* number of points on the curve */ >>> + __u16 count; >>> + /* input/output bits per component */ >>> + __u8 input_bpc, output_bpc; >>> + /* input start/end values */ >>> + __s32 start, end; >>> + /* output min/max values */ >>> + __s32 min, max; >>> +}; >>> + >>> +enum lut_type { >> >> Unprefixed type name in UAPI headers is probably not a good idea. > > Ok, will rename these. > >>> + LUT_TYPE_DEGAMMA = 0, >>> + LUT_TYPE_GAMMA = 1, >>> +}; >> >> All the above stuff seems to be the same in your other patch series' >> patch "[PATCH 1/9] drm: Add gamma mode property". Is this series replacing the >> series "[PATCH 0/9] Enhance pipe color support for multi segmented luts" or what >> does this mean? > > The concept and idea is similar and the range definition is also common. But this series > focuses on plane color management while the other one is for pipe/crtc color features. > Hence separated and floated them as unique series for review. > Might be better in this case to combine both patchsets. It wasn't entirely clear to me whether I could base one patchset on top of the other (doesn't look like it) and what base to apply them on. I had success applying the plane stuff on drm-next and the crtc stuff on drm-intel. Harry > Regards, > Uma Shankar >> >> Thanks, >> pq >> >>> + >>> +/* >>> + * Creating 64 bit palette entries for better data >>> + * precision. This will be required for HDR and >>> + * similar color processing usecases. >>> + */ >>> +struct drm_color_lut_ext { >>> + /* >>> + * Data is U32.32 fixed point format. >>> + */ >>> + __u64 red; >>> + __u64 green; >>> + __u64 blue; >>> + __u64 reserved; >>> +}; >>> + >>> #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define >>> DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define >>> DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-06-04 15:23 UTC|newest] Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-01 10:51 [PATCH 00/21] Add Support for Plane Color Lut and CSC features Uma Shankar 2021-06-01 10:51 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:51 ` [PATCH 01/21] drm: Add Enhanced Gamma and color lut range attributes Uma Shankar 2021-06-01 10:51 ` [Intel-gfx] " Uma Shankar 2021-06-02 9:33 ` Pekka Paalanen 2021-06-02 9:33 ` [Intel-gfx] " Pekka Paalanen 2021-06-02 20:26 ` Shankar, Uma 2021-06-02 20:26 ` [Intel-gfx] " Shankar, Uma 2021-06-04 15:23 ` Harry Wentland [this message] 2021-06-04 15:23 ` Harry Wentland 2021-06-07 17:19 ` Shankar, Uma 2021-06-07 17:19 ` [Intel-gfx] " Shankar, Uma 2021-06-01 10:51 ` [PATCH 02/21] drm: Add Plane Degamma Mode property Uma Shankar 2021-06-01 10:51 ` [Intel-gfx] " Uma Shankar 2021-06-04 18:24 ` Harry Wentland 2021-06-04 18:24 ` [Intel-gfx] " Harry Wentland 2021-06-07 11:00 ` Pekka Paalanen 2021-06-07 11:00 ` [Intel-gfx] " Pekka Paalanen 2021-06-07 17:34 ` Shankar, Uma 2021-06-07 17:34 ` [Intel-gfx] " Shankar, Uma 2021-06-08 8:34 ` Pekka Paalanen 2021-06-08 8:34 ` [Intel-gfx] " Pekka Paalanen 2021-06-01 10:52 ` [PATCH 03/21] drm: Add Plane Degamma Lut property Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 04/21] drm/i915/xelpd: Define Degamma Lut range struct for HDR planes Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-28 15:14 ` Harry Wentland 2021-06-28 15:14 ` [Intel-gfx] " Harry Wentland 2021-06-30 11:36 ` Shankar, Uma 2021-06-30 11:36 ` [Intel-gfx] " Shankar, Uma 2021-06-01 10:52 ` [PATCH 05/21] drm/i915/xelpd: Add register definitions for Plane Degamma Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 06/21] drm/i915/xelpd: Enable plane color features Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 07/21] drm/i915/xelpd: Add color capabilities of SDR planes Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 08/21] drm/i915/xelpd: Program Plane Degamma Registers Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 09/21] drm/i915/xelpd: Add plane color check to glk_plane_color_ctl Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 10/21] drm/i915/xelpd: Initialize plane color features Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 11/21] drm/i915/xelpd: Load plane color luts from atomic flip Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 12/21] drm: Add Plane CTM property Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 13/21] drm: Add helper to attach Plane ctm property Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 14/21] drm/i915/xelpd: Define Plane CSC Registers Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 15/21] drm/i915/xelpd: Enable Plane CSC Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 16/21] drm: Add Plane Gamma Mode property Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 17/21] drm: Add Plane Gamma Lut property Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 18/21] drm/i915/xelpd: Define and Initialize Plane Gamma Lut range Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 19/21] drm/i915/xelpd: Add register definitions for Plane Gamma Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 20/21] drm/i915/xelpd: Program Plane Gamma Registers Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 10:52 ` [PATCH 21/21] drm/i915/xelpd: Enable plane gamma Uma Shankar 2021-06-01 10:52 ` [Intel-gfx] " Uma Shankar 2021-06-01 13:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add Support for Plane Color Lut and CSC features Patchwork 2021-06-01 13:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-06-01 13:49 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2021-06-02 9:28 ` [PATCH 00/21] " Pekka Paalanen 2021-06-02 9:28 ` [Intel-gfx] " Pekka Paalanen 2021-06-02 20:22 ` Shankar, Uma 2021-06-02 20:22 ` [Intel-gfx] " Shankar, Uma 2021-06-02 23:42 ` Harry Wentland 2021-06-02 23:42 ` [Intel-gfx] " Harry Wentland 2021-06-03 8:47 ` Pekka Paalanen 2021-06-03 8:47 ` [Intel-gfx] " Pekka Paalanen 2021-06-03 12:30 ` Sebastian Wick 2021-06-03 12:30 ` [Intel-gfx] " Sebastian Wick 2021-06-03 12:58 ` Pekka Paalanen 2021-06-03 12:58 ` [Intel-gfx] " Pekka Paalanen
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