From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AD66C433ED for ; Wed, 19 May 2021 17:49:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CDCCA611BF for ; Wed, 19 May 2021 17:49:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CDCCA611BF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=eldorado.org.br Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:40504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljQJY-0001pQ-K5 for qemu-devel@archiver.kernel.org; Wed, 19 May 2021 13:49:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58076) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQFF-0007Ma-Pa; Wed, 19 May 2021 13:44:33 -0400 Received: from [201.28.113.2] (port=25524 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljQFC-0004pk-Sn; Wed, 19 May 2021 13:44:33 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Wed, 19 May 2021 14:44:25 -0300 Received: from [127.0.0.1] (unknown [10.10.71.235]) by power9a (Postfix) with ESMTPS id 610B780139F; Wed, 19 May 2021 14:44:25 -0300 (-03) Subject: Re: [PATCH 18/24] target/ppc: Push real-mode handling into ppc_radix64_xlate To: Richard Henderson , qemu-devel@nongnu.org References: <20210518201146.794854-1-richard.henderson@linaro.org> <20210518201146.794854-19-richard.henderson@linaro.org> From: Bruno Piazera Larsen Message-ID: Date: Wed, 19 May 2021 14:44:24 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210518201146.794854-19-richard.henderson@linaro.org> Content-Type: multipart/alternative; boundary="------------6F013632150B7A95393E4275" Content-Language: en-US X-OriginalArrivalTime: 19 May 2021 17:44:25.0613 (UTC) FILETIME=[9C162BD0:01D74CD6] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass client-ip=201.28.113.2; envelope-from=bruno.larsen@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, HTML_MESSAGE=0.001, NICE_REPLY_A=-0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is a multi-part message in MIME format. --------------6F013632150B7A95393E4275 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit On 18/05/2021 17:11, Richard Henderson wrote: > This removes some incomplete duplication between > ppc_radix64_handle_mmu_fault and ppc_radix64_get_phys_page_debug. > The former was correct wrt SPR_HRMOR and the latter was not. > > Signed-off-by: Richard Henderson Reviewed-by: Bruno Larsen (billionai) > --- > target/ppc/mmu-radix64.c | 77 ++++++++++++++++++---------------------- > 1 file changed, 34 insertions(+), 43 deletions(-) > > diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c > index f6d96f73b2..76a5cc8cdb 100644 > --- a/target/ppc/mmu-radix64.c > +++ b/target/ppc/mmu-radix64.c > @@ -466,7 +466,6 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, > */ > static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, > MMUAccessType access_type, > - bool relocation, > hwaddr *raddr, int *psizep, int *protp, > bool guest_visible) > { > @@ -475,6 +474,37 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, > ppc_v3_pate_t pate; > int psize, prot; > hwaddr g_raddr; > + bool relocation; > + > + assert(!(msr_hv && cpu->vhyp)); > + > + relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr); > + > + /* HV or virtual hypervisor Real Mode Access */ > + if (!relocation && (msr_hv || cpu->vhyp)) { > + /* In real mode top 4 effective addr bits (mostly) ignored */ > + *raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; > + > + /* In HV mode, add HRMOR if top EA bit is clear */ > + if (msr_hv || !env->has_hv_mode) { > + if (!(eaddr >> 63)) { > + *raddr |= env->spr[SPR_HRMOR]; > + } > + } > + *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC; > + *psizep = TARGET_PAGE_BITS; > + return 0; > + } > + > + /* > + * Check UPRT (we avoid the check in real mode to deal with > + * transitional states during kexec. > + */ > + if (guest_visible && !ppc64_use_proc_tbl(cpu)) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "LPCR:UPRT not set in radix mode ! LPCR=" > + TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); > + } > > /* Virtual Mode Access - get the fully qualified address */ > if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) { > @@ -560,43 +590,11 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, > MMUAccessType access_type, int mmu_idx) > { > CPUState *cs = CPU(cpu); > - CPUPPCState *env = &cpu->env; > int page_size, prot; > - bool relocation; > hwaddr raddr; > > - assert(!(msr_hv && cpu->vhyp)); > - > - relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr); > - /* HV or virtual hypervisor Real Mode Access */ > - if (!relocation && (msr_hv || cpu->vhyp)) { > - /* In real mode top 4 effective addr bits (mostly) ignored */ > - raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; > - > - /* In HV mode, add HRMOR if top EA bit is clear */ > - if (msr_hv || !env->has_hv_mode) { > - if (!(eaddr >> 63)) { > - raddr |= env->spr[SPR_HRMOR]; > - } > - } > - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, > - PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, > - TARGET_PAGE_SIZE); > - return 0; > - } > - > - /* > - * Check UPRT (we avoid the check in real mode to deal with > - * transitional states during kexec. > - */ > - if (!ppc64_use_proc_tbl(cpu)) { > - qemu_log_mask(LOG_GUEST_ERROR, > - "LPCR:UPRT not set in radix mode ! LPCR=" > - TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); > - } > - > /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */ > - if (ppc_radix64_xlate(cpu, eaddr, access_type, relocation, &raddr, > + if (ppc_radix64_xlate(cpu, eaddr, access_type, &raddr, > &page_size, &prot, true)) { > return 1; > } > @@ -608,18 +606,11 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, > > hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) > { > - CPUPPCState *env = &cpu->env; > int psize, prot; > hwaddr raddr; > > - /* Handle Real Mode */ > - if ((msr_dr == 0) && (msr_hv || cpu->vhyp)) { > - /* In real mode top 4 effective addr bits (mostly) ignored */ > - return eaddr & 0x0FFFFFFFFFFFFFFFULL; > - } > - > - if (ppc_radix64_xlate(cpu, eaddr, 0, msr_dr, &raddr, &psize, > - &prot, false)) { > + if (ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, > + &psize, &prot, false)) { > return -1; > } > -- Bruno Piazera Larsen Instituto de Pesquisas ELDORADO Departamento Computação Embarcada Analista de Software Trainee Aviso Legal - Disclaimer --------------6F013632150B7A95393E4275 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 8bit


On 18/05/2021 17:11, Richard Henderson wrote:
This removes some incomplete duplication between
ppc_radix64_handle_mmu_fault and ppc_radix64_get_phys_page_debug.
The former was correct wrt SPR_HRMOR and the latter was not.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
 target/ppc/mmu-radix64.c | 77 ++++++++++++++++++----------------------
 1 file changed, 34 insertions(+), 43 deletions(-)

diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index f6d96f73b2..76a5cc8cdb 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -466,7 +466,6 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
  */
 static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,
                              MMUAccessType access_type,
-                             bool relocation,
                              hwaddr *raddr, int *psizep, int *protp,
                              bool guest_visible)
 {
@@ -475,6 +474,37 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,
     ppc_v3_pate_t pate;
     int psize, prot;
     hwaddr g_raddr;
+    bool relocation;
+
+    assert(!(msr_hv && cpu->vhyp));
+
+    relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);
+
+    /* HV or virtual hypervisor Real Mode Access */
+    if (!relocation && (msr_hv || cpu->vhyp)) {
+        /* In real mode top 4 effective addr bits (mostly) ignored */
+        *raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
+
+        /* In HV mode, add HRMOR if top EA bit is clear */
+        if (msr_hv || !env->has_hv_mode) {
+            if (!(eaddr >> 63)) {
+                *raddr |= env->spr[SPR_HRMOR];
+           }
+        }
+        *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        *psizep = TARGET_PAGE_BITS;
+        return 0;
+    }
+
+    /*
+     * Check UPRT (we avoid the check in real mode to deal with
+     * transitional states during kexec.
+     */
+    if (guest_visible && !ppc64_use_proc_tbl(cpu)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "LPCR:UPRT not set in radix mode ! LPCR="
+                      TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
+    }
 
     /* Virtual Mode Access - get the fully qualified address */
     if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) {
@@ -560,43 +590,11 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
                                  MMUAccessType access_type, int mmu_idx)
 {
     CPUState *cs = CPU(cpu);
-    CPUPPCState *env = &cpu->env;
     int page_size, prot;
-    bool relocation;
     hwaddr raddr;
 
-    assert(!(msr_hv && cpu->vhyp));
-
-    relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);
-    /* HV or virtual hypervisor Real Mode Access */
-    if (!relocation && (msr_hv || cpu->vhyp)) {
-        /* In real mode top 4 effective addr bits (mostly) ignored */
-        raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
-
-        /* In HV mode, add HRMOR if top EA bit is clear */
-        if (msr_hv || !env->has_hv_mode) {
-            if (!(eaddr >> 63)) {
-                raddr |= env->spr[SPR_HRMOR];
-           }
-        }
-        tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
-                     PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
-                     TARGET_PAGE_SIZE);
-        return 0;
-    }
-
-    /*
-     * Check UPRT (we avoid the check in real mode to deal with
-     * transitional states during kexec.
-     */
-    if (!ppc64_use_proc_tbl(cpu)) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "LPCR:UPRT not set in radix mode ! LPCR="
-                      TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
-    }
-
     /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */
-    if (ppc_radix64_xlate(cpu, eaddr, access_type, relocation, &raddr,
+    if (ppc_radix64_xlate(cpu, eaddr, access_type, &raddr,
                           &page_size, &prot, true)) {
         return 1;
     }
@@ -608,18 +606,11 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
 
 hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
 {
-    CPUPPCState *env = &cpu->env;
     int psize, prot;
     hwaddr raddr;
 
-    /* Handle Real Mode */
-    if ((msr_dr == 0) && (msr_hv || cpu->vhyp)) {
-        /* In real mode top 4 effective addr bits (mostly) ignored */
-        return eaddr & 0x0FFFFFFFFFFFFFFFULL;
-    }
-
-    if (ppc_radix64_xlate(cpu, eaddr, 0, msr_dr, &raddr, &psize,
-                          &prot, false)) {
+    if (ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr,
+                          &psize, &prot, false)) {
         return -1;
     }
--
Bruno Piazera Larsen
Instituto de Pesquisas ELDORADO
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer
--------------6F013632150B7A95393E4275--