From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 477E8C2D0DB for ; Thu, 23 Jan 2020 19:55:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0EEF62077C for ; Thu, 23 Jan 2020 19:55:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="KhA1MIMD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728708AbgAWTzg (ORCPT ); Thu, 23 Jan 2020 14:55:36 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:49679 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726118AbgAWTzf (ORCPT ); Thu, 23 Jan 2020 14:55:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1579809334; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TC1aPguYbO4LyZ/z5OOvapVO0qs9innz+fiEUFsArMw=; b=KhA1MIMDf/Bg8zPqUZD5sgKrk6YdZA1l0KLQ3+rVBmELqbCSjMWMcx9DEKkd4MEUH9nd44 EtCtPKGypPJGmK2DCl7C6wWMHVy8E/on1JjD/Byyuyc6gN/PISG7CrX4rMHzCQOV+Ymypn GgwcpO9k0A9FHpW030HXfF8PaRZNWfI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-174-_Xk029daMc20sZmGUDfqxQ-1; Thu, 23 Jan 2020 14:55:30 -0500 X-MC-Unique: _Xk029daMc20sZmGUDfqxQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id D09FF107ACC5; Thu, 23 Jan 2020 19:55:26 +0000 (UTC) Received: from llong.remote.csb (dhcp-17-59.bos.redhat.com [10.18.17.59]) by smtp.corp.redhat.com (Postfix) with ESMTP id D69F51001901; Thu, 23 Jan 2020 19:55:24 +0000 (UTC) Subject: Re: [PATCH v9 4/5] locking/qspinlock: Introduce starvation avoidance into CNA To: Alex Kogan , linux@armlinux.org.uk, peterz@infradead.org, mingo@redhat.com, will.deacon@arm.com, arnd@arndb.de, linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, bp@alien8.de, hpa@zytor.com, x86@kernel.org, guohanjun@huawei.com, jglauber@marvell.com Cc: steven.sistare@oracle.com, daniel.m.jordan@oracle.com, dave.dice@oracle.com References: <20200115035920.54451-1-alex.kogan@oracle.com> <20200115035920.54451-5-alex.kogan@oracle.com> From: Waiman Long Organization: Red Hat Message-ID: Date: Thu, 23 Jan 2020 14:55:24 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 MIME-Version: 1.0 In-Reply-To: <20200115035920.54451-5-alex.kogan@oracle.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/14/20 10:59 PM, Alex Kogan wrote: > Keep track of the number of intra-node lock handoffs, and force > inter-node handoff once this number reaches a preset threshold. > The default value for the threshold can be overridden with > the new kernel boot command-line option "numa_spinlock_threshold". > > Signed-off-by: Alex Kogan > Reviewed-by: Steve Sistare > Reviewed-by: Waiman Long > --- > .../admin-guide/kernel-parameters.txt | 8 ++++ > kernel/locking/qspinlock.c | 3 ++ > kernel/locking/qspinlock_cna.h | 41 ++++++++++++++++++- > 3 files changed, 51 insertions(+), 1 deletion(-) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Document= ation/admin-guide/kernel-parameters.txt > index b68cb80e477f..30d79819a3b0 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -3200,6 +3200,14 @@ > Not specifying this option is equivalent to > numa_spinlock=3Dauto. > =20 > + numa_spinlock_threshold=3D [NUMA, PV_OPS] > + Set the threshold for the number of intra-node > + lock hand-offs before the NUMA-aware spinlock > + is forced to be passed to a thread on another NUMA node. > + Valid values are in the [0..31] range. Smaller values > + result in a more fair, but less performant spinlock, and > + vice versa. The default value is 16. > + > cpu0_hotplug [X86] Turn on CPU0 hotplug feature when > CONFIG_BOOTPARAM_HOTPLUG_CPU0 is off. > Some features depend on CPU0. Known dependencies are: > diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c > index 609980a53841..e382d8946ccc 100644 > --- a/kernel/locking/qspinlock.c > +++ b/kernel/locking/qspinlock.c > @@ -597,6 +597,9 @@ EXPORT_SYMBOL(queued_spin_lock_slowpath); > #if !defined(_GEN_CNA_LOCK_SLOWPATH) && defined(CONFIG_NUMA_AWARE_SPIN= LOCKS) > #define _GEN_CNA_LOCK_SLOWPATH > =20 > +#undef pv_init_node > +#define pv_init_node cna_init_node > + > #undef pv_wait_head_or_lock > #define pv_wait_head_or_lock cna_pre_scan > =20 > diff --git a/kernel/locking/qspinlock_cna.h b/kernel/locking/qspinlock_= cna.h > index 8000231f3d51..a2b65f87e6f8 100644 > --- a/kernel/locking/qspinlock_cna.h > +++ b/kernel/locking/qspinlock_cna.h > @@ -51,13 +51,25 @@ struct cna_node { > int numa_node; > u32 encoded_tail; > u32 pre_scan_result; /* encoded tail or enum val */ > + u32 intra_count; > }; > =20 > enum { > LOCAL_WAITER_FOUND =3D 2, /* 0 and 1 are reserved for @locked */ > + FLUSH_SECONDARY_QUEUE =3D 3, > MIN_ENCODED_TAIL > }; > =20 > +/* > + * Controls the threshold for the number of intra-node lock hand-offs = before > + * the NUMA-aware variant of spinlock is forced to be passed to a thre= ad on > + * another NUMA node. By default, the chosen value provides reasonable > + * long-term fairness without sacrificing performance compared to a lo= ck > + * that does not have any fairness guarantees. The default setting can > + * be changed with the "numa_spinlock_threshold" boot option. > + */ > +unsigned int intra_node_handoff_threshold __ro_after_init =3D 1 << 16; > + > static void __init cna_init_nodes_per_cpu(unsigned int cpu) > { > struct mcs_spinlock *base =3D per_cpu_ptr(&qnodes[0].mcs, cpu); > @@ -97,6 +109,11 @@ static int __init cna_init_nodes(void) > } > early_initcall(cna_init_nodes); > =20 > +static __always_inline void cna_init_node(struct mcs_spinlock *node) > +{ > + ((struct cna_node *)node)->intra_count =3D 0; > +} > + > /* this function is called only when the primary queue is empty */ > static inline bool cna_try_change_tail(struct qspinlock *lock, u32 val= , > struct mcs_spinlock *node) > @@ -232,7 +249,9 @@ __always_inline u32 cna_pre_scan(struct qspinlock *= lock, > { > struct cna_node *cn =3D (struct cna_node *)node; > =20 > - cn->pre_scan_result =3D cna_scan_main_queue(node, node); > + cn->pre_scan_result =3D > + cn->intra_count =3D=3D intra_node_handoff_threshold ? > + FLUSH_SECONDARY_QUEUE : cna_scan_main_queue(node, node); > =20 > return 0; > } > @@ -262,6 +281,9 @@ static inline void cna_pass_lock(struct mcs_spinloc= k *node, > * if we acquired the MCS lock when its queue was empty > */ > val =3D node->locked ? node->locked : 1; > + /* inc @intra_count if the secondary queue is not empty */ > + ((struct cna_node *)next_holder)->intra_count =3D > + cn->intra_count + (node->locked > 1); Playing with lock event counts, I would like you to change the meaning intra_count parameter that you are tracking. Instead of tracking the number of times a lock is passed to a waiter of the same node consecutively, I would like you to track the number of times the head waiter in the secondary queue has given up its chance to acquire the lock because a later waiter has jumped the queue and acquire the lock before it. This value determines the worst case latency that a secondary queue waiter can experience. So @@ -332,8 +334,12 @@ static inline void cna_pass_lock(struct mcs_spinlock *node, =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 */ =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 val =3D node->locked ? node->locked : 1; =C2=A0 -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 /* inc @intra_count if the secondary queue is not empty */ -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 next_cn->intra_count =3D cn->intra_count + (node->locked > 1= ); +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 /* +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 * inc @intra_count and pass it down if the secondary q= ueue +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 * is not empty +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 */ +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 if (node->locked > 1) +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 next_cn->int= ra_count =3D cn->intra_count + 1; =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } else if (node->locked > 1) {= =C2=A0=C2=A0=C2=A0 /* if secondary queue is not empty */ =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 /* next holder will be the first node in the secondary queue */ Maybe rename it to jump_count or some other more meaningful name. With that change, we could probably reduce the default threshold from 64k to maybe 256 or 512. I changed the threshold to 256 and run a 96-thread locking stress test for 10s, the lock event counts: cna_flush_queue=3D15687 cna_intra_max=3D256 cna_mainscan_hit=3D13 cna_merge_queue=3D15691 cna_prescan_hit=3D4344037 cna_prescan_miss=3D21 cna_splice_new=3D15701 cna_splice_old=3D1289 lock_pending=3D4384 lock_slowpath=3D47998292 lock_use_node2=3D16778 Of the prescan hits, only about 0.4% of that resulted in a queue flush which I thought is reasonable. I didn't see any noticeable degradation in the performance of the stress test by reducing the threshold from 64k to 256. Cheers, Longman From mboxrd@z Thu Jan 1 00:00:00 1970 From: Waiman Long Subject: Re: [PATCH v9 4/5] locking/qspinlock: Introduce starvation avoidance into CNA Date: Thu, 23 Jan 2020 14:55:24 -0500 Message-ID: References: <20200115035920.54451-1-alex.kogan@oracle.com> <20200115035920.54451-5-alex.kogan@oracle.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20200115035920.54451-5-alex.kogan@oracle.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane-mx.org@lists.infradead.org To: Alex Kogan , linux@armlinux.org.uk, peterz@infradead.org, mingo@redhat.com, will.deacon@arm.com, arnd@arndb.de, linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, bp@alien8.de, hpa@zytor.com, x86@kernel.org, guohanjun@huawei.com, jglauber@marvell.com Cc: dave.dice@oracle.com, steven.sistare@oracle.com, daniel.m.jordan@oracle.com List-Id: linux-arch.vger.kernel.org T24gMS8xNC8yMCAxMDo1OSBQTSwgQWxleCBLb2dhbiB3cm90ZToKPiBLZWVwIHRyYWNrIG9mIHRo ZSBudW1iZXIgb2YgaW50cmEtbm9kZSBsb2NrIGhhbmRvZmZzLCBhbmQgZm9yY2UKPiBpbnRlci1u b2RlIGhhbmRvZmYgb25jZSB0aGlzIG51bWJlciByZWFjaGVzIGEgcHJlc2V0IHRocmVzaG9sZC4K PiBUaGUgZGVmYXVsdCB2YWx1ZSBmb3IgdGhlIHRocmVzaG9sZCBjYW4gYmUgb3ZlcnJpZGRlbiB3 aXRoCj4gdGhlIG5ldyBrZXJuZWwgYm9vdCBjb21tYW5kLWxpbmUgb3B0aW9uICJudW1hX3NwaW5s b2NrX3RocmVzaG9sZCIuCj4KPiBTaWduZWQtb2ZmLWJ5OiBBbGV4IEtvZ2FuIDxhbGV4LmtvZ2Fu QG9yYWNsZS5jb20+Cj4gUmV2aWV3ZWQtYnk6IFN0ZXZlIFNpc3RhcmUgPHN0ZXZlbi5zaXN0YXJl QG9yYWNsZS5jb20+Cj4gUmV2aWV3ZWQtYnk6IFdhaW1hbiBMb25nIDxsb25nbWFuQHJlZGhhdC5j b20+Cj4gLS0tCj4gIC4uLi9hZG1pbi1ndWlkZS9rZXJuZWwtcGFyYW1ldGVycy50eHQgICAgICAg ICB8ICA4ICsrKysKPiAga2VybmVsL2xvY2tpbmcvcXNwaW5sb2NrLmMgICAgICAgICAgICAgICAg ICAgIHwgIDMgKysKPiAga2VybmVsL2xvY2tpbmcvcXNwaW5sb2NrX2NuYS5oICAgICAgICAgICAg ICAgIHwgNDEgKysrKysrKysrKysrKysrKysrLQo+ICAzIGZpbGVzIGNoYW5nZWQsIDUxIGluc2Vy dGlvbnMoKyksIDEgZGVsZXRpb24oLSkKPgo+IGRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2Fk bWluLWd1aWRlL2tlcm5lbC1wYXJhbWV0ZXJzLnR4dCBiL0RvY3VtZW50YXRpb24vYWRtaW4tZ3Vp ZGUva2VybmVsLXBhcmFtZXRlcnMudHh0Cj4gaW5kZXggYjY4Y2I4MGU0NzdmLi4zMGQ3OTgxOWEz YjAgMTAwNjQ0Cj4gLS0tIGEvRG9jdW1lbnRhdGlvbi9hZG1pbi1ndWlkZS9rZXJuZWwtcGFyYW1l dGVycy50eHQKPiArKysgYi9Eb2N1bWVudGF0aW9uL2FkbWluLWd1aWRlL2tlcm5lbC1wYXJhbWV0 ZXJzLnR4dAo+IEBAIC0zMjAwLDYgKzMyMDAsMTQgQEAKPiAgCQkJTm90IHNwZWNpZnlpbmcgdGhp cyBvcHRpb24gaXMgZXF1aXZhbGVudCB0bwo+ICAJCQludW1hX3NwaW5sb2NrPWF1dG8uCj4gIAo+ ICsJbnVtYV9zcGlubG9ja190aHJlc2hvbGQ9CVtOVU1BLCBQVl9PUFNdCj4gKwkJCVNldCB0aGUg dGhyZXNob2xkIGZvciB0aGUgbnVtYmVyIG9mIGludHJhLW5vZGUKPiArCQkJbG9jayBoYW5kLW9m ZnMgYmVmb3JlIHRoZSBOVU1BLWF3YXJlIHNwaW5sb2NrCj4gKwkJCWlzIGZvcmNlZCB0byBiZSBw YXNzZWQgdG8gYSB0aHJlYWQgb24gYW5vdGhlciBOVU1BIG5vZGUuCj4gKwkJCVZhbGlkIHZhbHVl cyBhcmUgaW4gdGhlIFswLi4zMV0gcmFuZ2UuIFNtYWxsZXIgdmFsdWVzCj4gKwkJCXJlc3VsdCBp biBhIG1vcmUgZmFpciwgYnV0IGxlc3MgcGVyZm9ybWFudCBzcGlubG9jaywgYW5kCj4gKwkJCXZp Y2UgdmVyc2EuIFRoZSBkZWZhdWx0IHZhbHVlIGlzIDE2Lgo+ICsKPiAgCWNwdTBfaG90cGx1Zwlb WDg2XSBUdXJuIG9uIENQVTAgaG90cGx1ZyBmZWF0dXJlIHdoZW4KPiAgCQkJQ09ORklHX0JPT1RQ QVJBTV9IT1RQTFVHX0NQVTAgaXMgb2ZmLgo+ICAJCQlTb21lIGZlYXR1cmVzIGRlcGVuZCBvbiBD UFUwLiBLbm93biBkZXBlbmRlbmNpZXMgYXJlOgo+IGRpZmYgLS1naXQgYS9rZXJuZWwvbG9ja2lu Zy9xc3BpbmxvY2suYyBiL2tlcm5lbC9sb2NraW5nL3FzcGlubG9jay5jCj4gaW5kZXggNjA5OTgw YTUzODQxLi5lMzgyZDg5NDZjY2MgMTAwNjQ0Cj4gLS0tIGEva2VybmVsL2xvY2tpbmcvcXNwaW5s b2NrLmMKPiArKysgYi9rZXJuZWwvbG9ja2luZy9xc3BpbmxvY2suYwo+IEBAIC01OTcsNiArNTk3 LDkgQEAgRVhQT1JUX1NZTUJPTChxdWV1ZWRfc3Bpbl9sb2NrX3Nsb3dwYXRoKTsKPiAgI2lmICFk ZWZpbmVkKF9HRU5fQ05BX0xPQ0tfU0xPV1BBVEgpICYmIGRlZmluZWQoQ09ORklHX05VTUFfQVdB UkVfU1BJTkxPQ0tTKQo+ICAjZGVmaW5lIF9HRU5fQ05BX0xPQ0tfU0xPV1BBVEgKPiAgCj4gKyN1 bmRlZiBwdl9pbml0X25vZGUKPiArI2RlZmluZSBwdl9pbml0X25vZGUJCQljbmFfaW5pdF9ub2Rl Cj4gKwo+ICAjdW5kZWYgcHZfd2FpdF9oZWFkX29yX2xvY2sKPiAgI2RlZmluZSBwdl93YWl0X2hl YWRfb3JfbG9jawkJY25hX3ByZV9zY2FuCj4gIAo+IGRpZmYgLS1naXQgYS9rZXJuZWwvbG9ja2lu Zy9xc3BpbmxvY2tfY25hLmggYi9rZXJuZWwvbG9ja2luZy9xc3BpbmxvY2tfY25hLmgKPiBpbmRl eCA4MDAwMjMxZjNkNTEuLmEyYjY1Zjg3ZTZmOCAxMDA2NDQKPiAtLS0gYS9rZXJuZWwvbG9ja2lu Zy9xc3BpbmxvY2tfY25hLmgKPiArKysgYi9rZXJuZWwvbG9ja2luZy9xc3BpbmxvY2tfY25hLmgK PiBAQCAtNTEsMTMgKzUxLDI1IEBAIHN0cnVjdCBjbmFfbm9kZSB7Cj4gIAlpbnQJCQludW1hX25v ZGU7Cj4gIAl1MzIJCQllbmNvZGVkX3RhaWw7Cj4gIAl1MzIJCQlwcmVfc2Nhbl9yZXN1bHQ7IC8q IGVuY29kZWQgdGFpbCBvciBlbnVtIHZhbCAqLwo+ICsJdTMyCQkJaW50cmFfY291bnQ7Cj4gIH07 Cj4gIAo+ICBlbnVtIHsKPiAgCUxPQ0FMX1dBSVRFUl9GT1VORCA9IDIsCS8qIDAgYW5kIDEgYXJl IHJlc2VydmVkIGZvciBAbG9ja2VkICovCj4gKwlGTFVTSF9TRUNPTkRBUllfUVVFVUUgPSAzLAo+ ICAJTUlOX0VOQ09ERURfVEFJTAo+ICB9Owo+ICAKPiArLyoKPiArICogQ29udHJvbHMgdGhlIHRo cmVzaG9sZCBmb3IgdGhlIG51bWJlciBvZiBpbnRyYS1ub2RlIGxvY2sgaGFuZC1vZmZzIGJlZm9y ZQo+ICsgKiB0aGUgTlVNQS1hd2FyZSB2YXJpYW50IG9mIHNwaW5sb2NrIGlzIGZvcmNlZCB0byBi ZSBwYXNzZWQgdG8gYSB0aHJlYWQgb24KPiArICogYW5vdGhlciBOVU1BIG5vZGUuIEJ5IGRlZmF1 bHQsIHRoZSBjaG9zZW4gdmFsdWUgcHJvdmlkZXMgcmVhc29uYWJsZQo+ICsgKiBsb25nLXRlcm0g ZmFpcm5lc3Mgd2l0aG91dCBzYWNyaWZpY2luZyBwZXJmb3JtYW5jZSBjb21wYXJlZCB0byBhIGxv Y2sKPiArICogdGhhdCBkb2VzIG5vdCBoYXZlIGFueSBmYWlybmVzcyBndWFyYW50ZWVzLiBUaGUg ZGVmYXVsdCBzZXR0aW5nIGNhbgo+ICsgKiBiZSBjaGFuZ2VkIHdpdGggdGhlICJudW1hX3NwaW5s b2NrX3RocmVzaG9sZCIgYm9vdCBvcHRpb24uCj4gKyAqLwo+ICt1bnNpZ25lZCBpbnQgaW50cmFf bm9kZV9oYW5kb2ZmX3RocmVzaG9sZCBfX3JvX2FmdGVyX2luaXQgPSAxIDw8IDE2Owo+ICsKPiAg c3RhdGljIHZvaWQgX19pbml0IGNuYV9pbml0X25vZGVzX3Blcl9jcHUodW5zaWduZWQgaW50IGNw dSkKPiAgewo+ICAJc3RydWN0IG1jc19zcGlubG9jayAqYmFzZSA9IHBlcl9jcHVfcHRyKCZxbm9k ZXNbMF0ubWNzLCBjcHUpOwo+IEBAIC05Nyw2ICsxMDksMTEgQEAgc3RhdGljIGludCBfX2luaXQg Y25hX2luaXRfbm9kZXModm9pZCkKPiAgfQo+ICBlYXJseV9pbml0Y2FsbChjbmFfaW5pdF9ub2Rl cyk7Cj4gIAo+ICtzdGF0aWMgX19hbHdheXNfaW5saW5lIHZvaWQgY25hX2luaXRfbm9kZShzdHJ1 Y3QgbWNzX3NwaW5sb2NrICpub2RlKQo+ICt7Cj4gKwkoKHN0cnVjdCBjbmFfbm9kZSAqKW5vZGUp LT5pbnRyYV9jb3VudCA9IDA7Cj4gK30KPiArCj4gIC8qIHRoaXMgZnVuY3Rpb24gaXMgY2FsbGVk IG9ubHkgd2hlbiB0aGUgcHJpbWFyeSBxdWV1ZSBpcyBlbXB0eSAqLwo+ICBzdGF0aWMgaW5saW5l IGJvb2wgY25hX3RyeV9jaGFuZ2VfdGFpbChzdHJ1Y3QgcXNwaW5sb2NrICpsb2NrLCB1MzIgdmFs LAo+ICAJCQkJICAgICAgIHN0cnVjdCBtY3Nfc3BpbmxvY2sgKm5vZGUpCj4gQEAgLTIzMiw3ICsy NDksOSBAQCBfX2Fsd2F5c19pbmxpbmUgdTMyIGNuYV9wcmVfc2NhbihzdHJ1Y3QgcXNwaW5sb2Nr ICpsb2NrLAo+ICB7Cj4gIAlzdHJ1Y3QgY25hX25vZGUgKmNuID0gKHN0cnVjdCBjbmFfbm9kZSAq KW5vZGU7Cj4gIAo+IC0JY24tPnByZV9zY2FuX3Jlc3VsdCA9IGNuYV9zY2FuX21haW5fcXVldWUo bm9kZSwgbm9kZSk7Cj4gKwljbi0+cHJlX3NjYW5fcmVzdWx0ID0KPiArCQljbi0+aW50cmFfY291 bnQgPT0gaW50cmFfbm9kZV9oYW5kb2ZmX3RocmVzaG9sZCA/Cj4gKwkJCUZMVVNIX1NFQ09OREFS WV9RVUVVRSA6IGNuYV9zY2FuX21haW5fcXVldWUobm9kZSwgbm9kZSk7Cj4gIAo+ICAJcmV0dXJu IDA7Cj4gIH0KPiBAQCAtMjYyLDYgKzI4MSw5IEBAIHN0YXRpYyBpbmxpbmUgdm9pZCBjbmFfcGFz c19sb2NrKHN0cnVjdCBtY3Nfc3BpbmxvY2sgKm5vZGUsCj4gIAkJICogaWYgd2UgYWNxdWlyZWQg dGhlIE1DUyBsb2NrIHdoZW4gaXRzIHF1ZXVlIHdhcyBlbXB0eQo+ICAJCSAqLwo+ICAJCXZhbCA9 IG5vZGUtPmxvY2tlZCA/IG5vZGUtPmxvY2tlZCA6IDE7Cj4gKwkJLyogaW5jIEBpbnRyYV9jb3Vu dCBpZiB0aGUgc2Vjb25kYXJ5IHF1ZXVlIGlzIG5vdCBlbXB0eSAqLwo+ICsJCSgoc3RydWN0IGNu YV9ub2RlICopbmV4dF9ob2xkZXIpLT5pbnRyYV9jb3VudCA9Cj4gKwkJCWNuLT5pbnRyYV9jb3Vu dCArIChub2RlLT5sb2NrZWQgPiAxKTsKClBsYXlpbmcgd2l0aCBsb2NrIGV2ZW50IGNvdW50cywg SSB3b3VsZCBsaWtlIHlvdSB0byBjaGFuZ2UgdGhlIG1lYW5pbmcKaW50cmFfY291bnQgcGFyYW1l dGVyIHRoYXQgeW91IGFyZSB0cmFja2luZy4gSW5zdGVhZCBvZiB0cmFja2luZyB0aGUKbnVtYmVy IG9mIHRpbWVzIGEgbG9jayBpcyBwYXNzZWQgdG8gYSB3YWl0ZXIgb2YgdGhlIHNhbWUgbm9kZQpj b25zZWN1dGl2ZWx5LCBJIHdvdWxkIGxpa2UgeW91IHRvIHRyYWNrIHRoZSBudW1iZXIgb2YgdGlt ZXMgdGhlIGhlYWQKd2FpdGVyIGluIHRoZSBzZWNvbmRhcnkgcXVldWUgaGFzIGdpdmVuIHVwIGl0 cyBjaGFuY2UgdG8gYWNxdWlyZSB0aGUKbG9jayBiZWNhdXNlIGEgbGF0ZXIgd2FpdGVyIGhhcyBq dW1wZWQgdGhlIHF1ZXVlIGFuZCBhY3F1aXJlIHRoZSBsb2NrCmJlZm9yZSBpdC4gVGhpcyB2YWx1 ZSBkZXRlcm1pbmVzIHRoZSB3b3JzdCBjYXNlIGxhdGVuY3kgdGhhdCBhIHNlY29uZGFyeQpxdWV1 ZSB3YWl0ZXIgY2FuIGV4cGVyaWVuY2UuIFNvCgpAQCAtMzMyLDggKzMzNCwxMiBAQCBzdGF0aWMg aW5saW5lIHZvaWQgY25hX3Bhc3NfbG9jayhzdHJ1Y3QKbWNzX3NwaW5sb2NrICpub2RlLArCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAqLwrCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqAgdmFsID0gbm9kZS0+bG9ja2VkID8gbm9kZS0+bG9ja2VkIDogMTsKwqAKLcKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqAgLyogaW5jIEBpbnRyYV9jb3VudCBpZiB0aGUgc2Vjb25kYXJ5 IHF1ZXVlIGlzIG5vdCBlbXB0eSAqLwotwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBuZXh0 X2NuLT5pbnRyYV9jb3VudCA9IGNuLT5pbnRyYV9jb3VudCArIChub2RlLT5sb2NrZWQgPiAxKTsK K8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgLyoKK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoCAqIGluYyBAaW50cmFfY291bnQgYW5kIHBhc3MgaXQgZG93biBpZiB0aGUgc2Vjb25k YXJ5IHF1ZXVlCivCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgKiBpcyBub3QgZW1wdHkK K8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAqLworwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoCBpZiAobm9kZS0+bG9ja2VkID4gMSkKK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoMKgIG5leHRfY24tPmludHJhX2NvdW50ID0gY24tPmludHJhX2NvdW50 ICsgMTsKwqDCoMKgwqDCoMKgwqAgfSBlbHNlIGlmIChub2RlLT5sb2NrZWQgPiAxKSB7wqDCoMKg IC8qIGlmIHNlY29uZGFyeSBxdWV1ZSBpcyBub3QKZW1wdHkgKi8KwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgIC8qIG5leHQgaG9sZGVyIHdpbGwgYmUgdGhlIGZpcnN0IG5vZGUgaW4gdGhl IHNlY29uZGFyeQpxdWV1ZSAqLwoKTWF5YmUgcmVuYW1lIGl0IHRvIGp1bXBfY291bnQgb3Igc29t ZSBvdGhlciBtb3JlIG1lYW5pbmdmdWwgbmFtZS4gV2l0aAp0aGF0IGNoYW5nZSwgd2UgY291bGQg cHJvYmFibHkgcmVkdWNlIHRoZSBkZWZhdWx0IHRocmVzaG9sZCBmcm9tIDY0ayB0bwptYXliZSAy NTYgb3IgNTEyLgoKSSBjaGFuZ2VkIHRoZSB0aHJlc2hvbGQgdG8gMjU2IGFuZCBydW4gYSA5Ni10 aHJlYWQgbG9ja2luZyBzdHJlc3MgdGVzdApmb3IgMTBzLCB0aGUgbG9jayBldmVudCBjb3VudHM6 CgpjbmFfZmx1c2hfcXVldWU9MTU2ODcKY25hX2ludHJhX21heD0yNTYKY25hX21haW5zY2FuX2hp dD0xMwpjbmFfbWVyZ2VfcXVldWU9MTU2OTEKY25hX3ByZXNjYW5faGl0PTQzNDQwMzcKY25hX3By ZXNjYW5fbWlzcz0yMQpjbmFfc3BsaWNlX25ldz0xNTcwMQpjbmFfc3BsaWNlX29sZD0xMjg5Cmxv Y2tfcGVuZGluZz00Mzg0CmxvY2tfc2xvd3BhdGg9NDc5OTgyOTIKbG9ja191c2Vfbm9kZTI9MTY3 NzgKCk9mIHRoZSBwcmVzY2FuIGhpdHMsIG9ubHkgYWJvdXQgMC40JSBvZiB0aGF0IHJlc3VsdGVk IGluIGEgcXVldWUgZmx1c2gKd2hpY2ggSSB0aG91Z2h0IGlzIHJlYXNvbmFibGUuIEkgZGlkbid0 IHNlZSBhbnkgbm90aWNlYWJsZSBkZWdyYWRhdGlvbgppbiB0aGUgcGVyZm9ybWFuY2Ugb2YgdGhl IHN0cmVzcyB0ZXN0IGJ5IHJlZHVjaW5nIHRoZSB0aHJlc2hvbGQgZnJvbSA2NGsKdG8gMjU2LgoK Q2hlZXJzLApMb25nbWFuCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBs aXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlz dGluZm8vbGludXgtYXJtLWtlcm5lbAo=