From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC3B3C433F5 for ; Wed, 20 Apr 2022 07:05:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359576AbiDTHI3 (ORCPT ); Wed, 20 Apr 2022 03:08:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231806AbiDTHIZ (ORCPT ); Wed, 20 Apr 2022 03:08:25 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E9F22559B; Wed, 20 Apr 2022 00:05:40 -0700 (PDT) Received: from [192.168.1.111] (91-156-85-209.elisa-laajakaista.fi [91.156.85.209]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id ECC0625B; Wed, 20 Apr 2022 09:05:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1650438338; bh=XI60ceOSPiOukm0RgGIMWmc07mkMjnkrZjqcQsrwgeI=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=VP5344N7sW30pjejQzEYeRU72UYfQq6pmhRTDBQhDQceHec72h4/ndutm5YbALjJh zHK/HVvwAhsTafWTtjvE3rYp5aHDvRw1yOcZaW6Hwo2Nc6UtiMflPFdD+1SmJ9h1su no87Z1//a8Iy1x4F1TdwnhnIgetHUrBDTjOrpvt0= Message-ID: Date: Wed, 20 Apr 2022 10:05:34 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt Content-Language: en-US To: Rob Herring Cc: Jyri Sarha , Vignesh Raghavendra , Nishanth Menon , DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar , Aradhya Bhatia References: <20220419070302.16502-1-a-bhatia1@ti.com> <20220419070302.16502-2-a-bhatia1@ti.com> From: Tomi Valkeinen In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 19/04/2022 17:20, Rob Herring wrote: > On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote: >> The DSS IP on the ti-am65x soc supports an additional register space, >> named "common1". Further. the IP services a maximum number of 2 >> interrupts. >> >> Add the missing register space "common1" and the additional interrupt. >> >> Signed-off-by: Aradhya Bhatia >> --- >> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- >> 1 file changed, 7 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> index 5c7d2cbc4aac..102059e9e0d5 100644 >> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> @@ -26,6 +26,7 @@ properties: >> Addresses to each DSS memory region described in the SoC's TRM. >> items: >> - description: common DSS register area >> + - description: common1 DSS register area > > You've just broken the ABI. > > New entries have to go on the end. I'm curious, if the 'reg-names' is a required property, as it is here, does this still break the ABI? Tomi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70F93C433F5 for ; Wed, 20 Apr 2022 07:05:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AC11510F175; Wed, 20 Apr 2022 07:05:41 +0000 (UTC) Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6D73010F179 for ; Wed, 20 Apr 2022 07:05:40 +0000 (UTC) Received: from [192.168.1.111] (91-156-85-209.elisa-laajakaista.fi [91.156.85.209]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id ECC0625B; Wed, 20 Apr 2022 09:05:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1650438338; bh=XI60ceOSPiOukm0RgGIMWmc07mkMjnkrZjqcQsrwgeI=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=VP5344N7sW30pjejQzEYeRU72UYfQq6pmhRTDBQhDQceHec72h4/ndutm5YbALjJh zHK/HVvwAhsTafWTtjvE3rYp5aHDvRw1yOcZaW6Hwo2Nc6UtiMflPFdD+1SmJ9h1su no87Z1//a8Iy1x4F1TdwnhnIgetHUrBDTjOrpvt0= Message-ID: Date: Wed, 20 Apr 2022 10:05:34 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt Content-Language: en-US To: Rob Herring References: <20220419070302.16502-1-a-bhatia1@ti.com> <20220419070302.16502-2-a-bhatia1@ti.com> From: Tomi Valkeinen In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Devicetree , Vignesh Raghavendra , Aradhya Bhatia , Linux Kernel , DRI Development , Jyri Sarha , Nikhil Devshatwar , Linux ARM Kernel Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, On 19/04/2022 17:20, Rob Herring wrote: > On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote: >> The DSS IP on the ti-am65x soc supports an additional register space, >> named "common1". Further. the IP services a maximum number of 2 >> interrupts. >> >> Add the missing register space "common1" and the additional interrupt. >> >> Signed-off-by: Aradhya Bhatia >> --- >> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- >> 1 file changed, 7 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> index 5c7d2cbc4aac..102059e9e0d5 100644 >> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> @@ -26,6 +26,7 @@ properties: >> Addresses to each DSS memory region described in the SoC's TRM. >> items: >> - description: common DSS register area >> + - description: common1 DSS register area > > You've just broken the ABI. > > New entries have to go on the end. I'm curious, if the 'reg-names' is a required property, as it is here, does this still break the ABI? Tomi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BFDCBC433F5 for ; Wed, 20 Apr 2022 07:07:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Cb85nOX1vx8DEdAjDFMM5wS2fV2JVs9os5JVd5Zf41M=; b=tYdMgGvzr0QnX4 Kks1wQwJ1f4CcUm1gfAn3S8u7F3ucY0ilISuajRIlhnzCweERPTipPUK4xtIbYUGn9HptpUnQv0X0 skEqV6spuqKPHpoq1dX1Wx45xz1guO7PrvwprxEJ9OiQwDAjhRQx9xa5qUgxzJIQjuxSpmNLU4fEp G4P2Af+bcaHOracg1x6EY7bP22dKx38fjD294MpOViRG2h44AIAkt5bgJG8HlKq+Lq1Frvk72JByy vPVNaSeSyqvIDiATXxBRuyIVUdGAOiEa6zQeRUax9QqkkXtwCdZuBga/L1/Nu8NxWPuvmw/OYf3EZ 0Af0YxMFQp6jhMvLLv7g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nh4PI-007gRF-Pf; Wed, 20 Apr 2022 07:05:44 +0000 Received: from perceval.ideasonboard.com ([213.167.242.64]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nh4PF-007gQ5-Nb for linux-arm-kernel@lists.infradead.org; Wed, 20 Apr 2022 07:05:43 +0000 Received: from [192.168.1.111] (91-156-85-209.elisa-laajakaista.fi [91.156.85.209]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id ECC0625B; Wed, 20 Apr 2022 09:05:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1650438338; bh=XI60ceOSPiOukm0RgGIMWmc07mkMjnkrZjqcQsrwgeI=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=VP5344N7sW30pjejQzEYeRU72UYfQq6pmhRTDBQhDQceHec72h4/ndutm5YbALjJh zHK/HVvwAhsTafWTtjvE3rYp5aHDvRw1yOcZaW6Hwo2Nc6UtiMflPFdD+1SmJ9h1su no87Z1//a8Iy1x4F1TdwnhnIgetHUrBDTjOrpvt0= Message-ID: Date: Wed, 20 Apr 2022 10:05:34 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt Content-Language: en-US To: Rob Herring Cc: Jyri Sarha , Vignesh Raghavendra , Nishanth Menon , DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar , Aradhya Bhatia References: <20220419070302.16502-1-a-bhatia1@ti.com> <20220419070302.16502-2-a-bhatia1@ti.com> From: Tomi Valkeinen In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220420_000541_966922_139EB87E X-CRM114-Status: GOOD ( 14.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On 19/04/2022 17:20, Rob Herring wrote: > On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote: >> The DSS IP on the ti-am65x soc supports an additional register space, >> named "common1". Further. the IP services a maximum number of 2 >> interrupts. >> >> Add the missing register space "common1" and the additional interrupt. >> >> Signed-off-by: Aradhya Bhatia >> --- >> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- >> 1 file changed, 7 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> index 5c7d2cbc4aac..102059e9e0d5 100644 >> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> @@ -26,6 +26,7 @@ properties: >> Addresses to each DSS memory region described in the SoC's TRM. >> items: >> - description: common DSS register area >> + - description: common1 DSS register area > > You've just broken the ABI. > > New entries have to go on the end. I'm curious, if the 'reg-names' is a required property, as it is here, does this still break the ABI? Tomi _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel