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Fri, 30 Jul 2021 07:08:11 +0900 (KST) Received: from [10.113.113.235] (unknown [10.113.113.235]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20210729220811epsmtip10d4e830c6db0c56bbbc9ce7df3395f6a~WYmKr1pHe1943119431epsmtip1i; Thu, 29 Jul 2021 22:08:11 +0000 (GMT) Subject: Re: Help with u-boot when using the eMMC card in DDR mode To: Abder Cc: u-boot@lists.denx.de From: Jaehoon Chung Message-ID: Date: Fri, 30 Jul 2021 07:09:02 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US Content-Transfer-Encoding: 8bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrIKsWRmVeSWpSXmKPExsWy7bCmge4ZNeZEg4dPuCxOv9rEbvF2bye7 A5PHzll32T3O3tnBGMAUlW2TkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pmYKhraGlhrqSQl5ib aqvk4hOg65aZAzRfSaEsMacUKBSQWFyspG9nU5RfWpKqkJFfXGKrlFqQklNgWaBXnJhbXJqX rpecn2tlaGBgZApUmJCdceb5YfaCWVYVP1ftZGtgPKLexcjJISFgInG+5zRjFyMXh5DADkaJ o5vOQDmfGCV+dn1ggnA+M0pcOXiYBablzazZLBCJXYwSB1YvZYVw3jNKdPfdZAepEhZwkuj4 dI0RxBYRUJRYvW8jM4jNLCAhseTQfVYQm01AR2L7t+NMIDavgJ3EutMtQL0cHCwCqhLTr7mB hEUFIiXO717AAlEiKHFy5hMwm1MgUOJC8w02iJHiEreezGeCsOUlmrfOZga5R0LgFrvE1Ne3 oa52kZj17hIbhC0s8er4FnYIW0ri87u9UPFqiV3NZ6CaOxglbm1rYoJIGEvsXzqZCeQ4ZgFN ifW79CHCihI7f89lhFjMJ/Huaw8rSImEAK9ER5sQRImKxKXXL5lgVt198p8VwvaQuLx7OdsE RsVZSF6bheSdWUjemYWweAEjyypGsdSC4tz01GLDAlPk2N7ECE57WpY7GKe//aB3iJGJg/EQ owQHs5II7+sf/xOEeFMSK6tSi/Lji0pzUosPMZoCw3ois5Rocj4w8eaVxBuaGhkbG1uYGJqZ GhoqifN+i/2aICSQnliSmp2aWpBaBNPHxMEp1cDEb2ObedJlc+ld68yeF2Xuszi+Rx0p3Gq1 2dnyagjrId7tRiu29cmJXs5k+dmoLqkg1KwRL6hTaqxf/86X++PXwiX3a0+s71qt7aDVPk3+ 16WSQyb/ftxuf++/bWEc/6WljJXM61Ydc7BfHFvzeGUt0+VuL+WET4+qDvpKWj1cJj1ritrE e0cLrK/UzWr5IzNPw3/1ihiBgvBHMnNWrLgmH8/6XEfpvq/AnZ98HD+b/RRunBHulkiq+GYV Lbf30lr2DSF7Llz8cPz4huTVT32EKtPOHno8w/r7x9A2iV0r2TaL3d1aFriDaU2w44PussIa plszb3pfZT7bfeXmgS6VxT9nCq7wKt1fp8l7fP0mJZbijERDLeai4kQA7brf0wQEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHLMWRmVeSWpSXmKPExsWy7bCSnO5pNeZEg+5vYhanX21it3i7t5Pd gclj56y77B5n7+xgDGCK4rJJSc3JLEst0rdL4Mo48/wwe8Esq4qfq3ayNTAeUe9i5OSQEDCR eDNrNksXIxeHkMAORolZWzazQySkJD4/ncrWxcgBZAtLHD5cDBIWEnjLKDFhPg+ILSzgJNHx 6RojiC0ioCixet9GZhCbWUBCYsmh+6wQMx8zS5y/d5gFJMEmoCOx/dtxJhCbV8BOYt3pFnaQ +SwCqhLTr7mBhEUFIiU+L3jFClEiKHFy5hOwVk6BQIkLzTfYIOarS/yZdwlql7jErSfzmSBs eYnmrbOZJzAKzULSPgtJyywkLbOQtCxgZFnFKJlaUJybnltsWGCUl1quV5yYW1yal66XnJ+7 iREc5FpaOxj3rPqgd4iRiYPxEKMEB7OSCO/rH/8ThHhTEiurUovy44tKc1KLDzFKc7AoifNe 6DoZLySQnliSmp2aWpBaBJNl4uCUamCa8uyZtBDXib3/nx5RWXtnx1RbP9+WxomBDx7s2yCx 6On03RsnKbw5ff+ZtsifxoO5TMEpIa1mkj9EutSTzv2O+b08WcBXITXAafcj+S8XE2UPzZK+ OjHCKVFL5JKJvba63JOcOO3fJjxc99qffWA9ESZYdDyhfdvTSTFf710/+X+D7XkethNSieef X9WYr+f4+8KT7WKHl5Rf+3fjwcMHuwQ58j7N+ndJbW1Iw5qW0LN5+1tWp4ewe27ZX+kUcH+x 65bPy3U2PpnRpLjkZyzvVpGVXS3lzvtDj0Sf5JXXOS55Y+6jmu7PnXUpsXmBZxm2rZdln6s9 UW7FtN3XFt091N670WzSonNfqgwab3jaKymxFGckGmoxFxUnAgCgHVNU4QIAAA== X-CMS-MailID: 20210729220811epcas1p1faec9dcfc6bbf61dc75a208aa6d78476 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: SVC_REQ_APPROVE CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20210726074153epcas1p2e7ff5b484d0c67ce7344808db8aa6f8a References: <290e93bd-7e34-a32c-d10c-d078fd3cd9e0@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi On 7/28/21 1:57 AM, Abder wrote: > The previously mentioned commit didn't resolve the issue. When testing I > made a mistake. > > The workaround I'm using to resolve the issue is by disabling the DDR mode > juste before re-init happens (DDR mode will be automatically enabled later > in the init process). > > Now I don't know if this is really a bug in the mmc driver, or I'm just > missing some additional configuration to work with the eMMC in DDR mode ! > It seems that it has a bug in fsl_esdhc_imx.c. I don't have any boards to use its driver. But when i have checked a code, there is a bit relevant to DDR enable bit in esdhc_set_timing(). If it doesn't clear its bit when it's re-initializing, it's possible to fail. Best Regards, Jaehoon Chung > > > > Le mar. 27 juil. 2021 à 15:14, Abder a écrit : > >> Hi Jaehoon, >> yes, DDR mode works fine before executing "mmc dev 2" command. >> However, for "mmc rescan" command or "mmc info" to work, I need to first >> select the correct mmc device using the "mmc dev 2" command, cuz the >> default one is device 0 in my case which is empty. >> >> OTOH, after hours of debugging I found the origin of the issue. In fact, >> the "mmc dev 2" command forces a reinitialization of the emmc, and if the >> emmc was already initialized in DDR mode at boot up, the implemented >> re-init flow leads to bad clock settings. >> (basicly the host tries to set the clock of the emmc to 400KHz >> (identification mode), but as the DDR mode is still enabled, the >> configured clock corresponds to the half of that = 200KHz). The mismatch in >> frequency is what caused the -70 ECOM error. >> and as the command fails, the emmc stays at 200KHz, which leads any >> attempt to interact with the emmc afterwards to failure. >> >> I found out that this bug was patched recently in >> 390f9bddb9c84f75649024b41b8cf2a766379ce0 in the main u-boot. >> >> Anyhow.. Thanks for your replies. >> >> Best regards, >> Abder >> >> >> Le mar. 27 juil. 2021 à 04:03, Jaehoon Chung a >> écrit : >> >>> On 7/26/21 5:36 PM, Abder wrote: >>>> Hi Jaehoon, >>>> This is the output with MMC_TRACE enabled >>>> >>>> U-Boot >mmc dev 2 >>>> blk_find_device: if_type=6, devnum=2: usdhc@02198000.blk, 6, 2 >>>> ofnode_read_u32: vmmc-supply: 0x33 (51) >>>> ofnode_read_u32: vqmmc-supply: 0x33 (51) >>>> clock is disabled (0Hz) >>>> fixed_regulator_set_enable: dev='3p3v', enable=1, delay=0, has_gpio=0 >>>> clock is enabled (400000Hz) >>>> CMD_SEND:0 >>>> ARG 0x00000000 >>>> MMC_RSP_NONE >>>> CMD_SEND:8 >>>> ARG 0x000001aa >>>> RET -110 >>>> CMD_SEND:55 >>>> ARG 0x00000000 >>>> RET -110 >>>> CMD_SEND:0 >>>> ARG 0x00000000 >>>> MMC_RSP_NONE >>>> CMD_SEND:1 >>>> ARG 0x00000000 >>>> MMC_RSP_R3,4 0x00ff8080 >>>> CMD_SEND:1 >>>> ARG 0x40300000 >>>> MMC_RSP_R3,4 0x00ff8080 >>>> CMD_SEND:0 >>>> ARG 0x00000000 >>>> MMC_RSP_NONE >>>> CMD_SEND:1 >>>> ARG 0x40300000 >>>> MMC_RSP_R3,4 0x00ff8080 >>>> CMD_SEND:1 >>>> ARG 0x40300000 >>>> MMC_RSP_R3,4 0x00ff8080 >>>> CMD_SEND:1 >>>> ARG 0x40300000 >>>> MMC_RSP_R3,4 0x00ff8080 >>>> CMD_SEND:1 >>>> ARG 0x40300000 >>>> MMC_RSP_R3,4 0xc0ff8080 >>>> CMD_SEND:2 >>>> ARG 0x00000000 >>>> RET -70 >>>> CMD_SEND:2 >>>> ARG 0x00000000 >>>> RET -70 >>>> CMD_SEND:2 >>>> ARG 0x00000000 >>>> RET -70 >>>> CMD_SEND:2 >>>> ARG 0x00000000 >>>> RET -70 >>>> CMD_SEND:2 >>>> ARG 0x00000000 >>>> RET -70 >>>> CMD_SEND:2 >>>> ARG 0x00000000 >>>> RET -70 >>>> Command failed, result=1 >>>> U-Boot > >>>> >>>> I believe the -70 error is an ECOM error (Communication error on send). >>>> However this does not occur when eMMC is in HS mode for example. >>>> and even in DDR mode, before executing the "mmc dev 2" cmd, the >>>> communication with the emmc with "load" works without a hitch. >>> >>> Sorry. I didn't understand clearly. >>> Does DDR mode work fine before "mmc dev 2" command? >>> Did you try to run other command? e,g) mmcinfo or mmc rescan? >>> >>> It seems that error is returned in fsl_esdhc_imx.c. >>> Well, it seems that not cleared something after some operation. >>> It needs to check full log and sequence. >>> >>> Best Regards, >>> Jaehoon Chung >>> >>>> >>>> >>>> >>>> Le lun. 26 juil. 2021 à 10:03, Jaehoon Chung a >>>> écrit : >>>> >>>>> Hi, >>>>> >>>>> On 7/26/21 4:41 PM, Abder wrote: >>>>>> Hi, >>>>>> >>>>>> I have been trying recently to optimize the boot time on a customized >>>>> board >>>>>> based on the IMX6DP. >>>>>> >>>>>> For the time being, I succeeded in enabling the DDR (dual data rate) >>> mode >>>>>> for the emmc to speed up the data rate for read and write cycles in >>>>> u-boot. >>>>>> >>>>>> By reading a file from the emmc using the "load" command (e.g. load >>> mmc >>>>> 2:1 >>>>>> 0x12000000 file), I can see that the data rate has doubled, confirming >>>>> that >>>>>> the DDR mode is enabled. >>>>>> >>>>>> However, the problem I have is that when I execute the u-boot command >>>>> "mmc >>>>>> dev 2" to switch the current device to the onboard eMMC, the command >>>>> fails >>>>>> with the output below : (with DEBUG enabled) >>>>> >>>>> If you can enable CONFIG_MMC_TRACE, then you can get more information >>>>> relevant to MMC. >>>>> Could you also share log after enabled MMC_TRACE? >>>>> >>>>> Best Regards, >>>>> Jaehoon Chung >>>>> >>>>>> >>>>>> U-Boot >mmc dev 2 >>>>>> blk_find_device: if_type=6, devnum=2: usdhc@02198000.blk, 6, 2 >>>>>> ofnode_read_u32: vmmc-supply: 0x33 (51) >>>>>> ofnode_read_u32: vqmmc-supply: 0x33 (51) >>>>>> clock is disabled (0Hz) >>>>>> fixed_regulator_set_enable: dev='3p3v', enable=1, delay=0, has_gpio=0 >>>>>> clock is enabled (400000Hz) >>>>>> Command failed, result=1 >>>>>> U-Boot > >>>>>> >>>>>> and after this command, any attempt to interact with the emmc (e.g. >>> fatls >>>>>> mmc 2:1 ) ends with failure. >>>>>> >>>>>> To enable the DDR mode, all I did was define the macro >>>>>> CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE in the header of my board. >>>>>> >>>>>> Any help is greatly appreciated ! >>>>>> >>>>>> -- >>>>>> >>>>>> Abder, >>>>>> >>>>> >>>>> >>>> >>> >>> >