From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE
Date: Fri, 26 Jun 2020 10:45:56 -0700 [thread overview]
Message-ID: <f6b67b54-cd8d-adde-f260-1a7151e687a0@intel.com> (raw)
In-Reply-To: <159318215858.13600.17747631516505792821@build.alporthouse.com>
On 6/26/20 7:35 AM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:07)
>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>> index 26cae4846c82..ddefc52f6e09 100644
>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>> @@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
>> MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>> MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>> MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>> - if (HAS_ENGINE(dev_priv, VCS1)) \
>> + if (HAS_ENGINE(&dev_priv->gt, VCS1)) \
>
> Implicit param! It can switch to gvt->gt for all callsites, killing the
> dev_priv locals.
I've switched this to gvt->gt, but unfortunately the locals will have to
stay because some of the display register definitions still use dev_priv
implicitly to access the display mmio base and the
pipe_offsets/trans_offsets arrays.
Daniele
> -Chris
>
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next prev parent reply other threads:[~2020-06-26 17:45 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-25 23:42 [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt Daniele Ceraolo Spurio
2020-06-25 23:42 ` [Intel-gfx] [PATCH 1/7] drm/i915: Convert device_info to uncore/de_read Daniele Ceraolo Spurio
2020-06-26 14:18 ` Tvrtko Ursulin
2020-06-25 23:42 ` [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE Daniele Ceraolo Spurio
2020-06-26 14:20 ` Tvrtko Ursulin
2020-06-26 14:35 ` Chris Wilson
2020-06-26 17:45 ` Daniele Ceraolo Spurio [this message]
2020-06-26 18:03 ` Chris Wilson
2020-06-25 23:42 ` [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio Daniele Ceraolo Spurio
2020-06-26 14:38 ` Tvrtko Ursulin
2020-06-26 14:38 ` Chris Wilson
2020-06-26 14:46 ` Daniele Ceraolo Spurio
2020-06-26 14:51 ` Chris Wilson
2020-06-25 23:42 ` [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info Daniele Ceraolo Spurio
2020-06-26 14:45 ` Tvrtko Ursulin
2020-06-26 16:44 ` Daniele Ceraolo Spurio
2020-06-26 16:50 ` Chris Wilson
2020-06-25 23:42 ` [Intel-gfx] [PATCH 5/7] drm/i915: Introduce gt_init_mmio Daniele Ceraolo Spurio
2020-06-26 14:46 ` Tvrtko Ursulin
2020-06-25 23:42 ` [Intel-gfx] [PATCH 6/7] drm/i915/sseu: Move sseu detection and dump to intel_sseu Daniele Ceraolo Spurio
2020-06-26 15:00 ` Tvrtko Ursulin
2020-06-25 23:42 ` [Intel-gfx] [PATCH 7/7] drm/i915/sseu: Move sseu_info under gt_info Daniele Ceraolo Spurio
2020-06-26 15:22 ` Tvrtko Ursulin
2020-06-26 16:49 ` Daniele Ceraolo Spurio
2020-06-27 8:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Move some device capabilities under intel_gt Patchwork
2020-06-27 8:38 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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