From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v4 07/20] ppc/pnv: add XSCOM handlers to PnvCore
Date: Thu, 13 Oct 2016 08:50:41 +0200 [thread overview]
Message-ID: <f7244dc1-654c-ba6c-2e0d-f9315ca523ad@kaod.org> (raw)
In-Reply-To: <20161013005118.GI18039@umbus.fritz.box>
On 10/13/2016 02:51 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:43AM +0200, Cédric Le Goater wrote:
>> Now that we are using real HW ids for the cores in PowerNV chips, we
>> can route the XSCOM accesses to them. We just need to attach a
>> specific XSCOM memory region to each core in the appropriate window
>> for the core number.
>>
>> To start with, let's install the DTS (Digital Thermal Sensor) handlers
>> which should return 38°C for each core.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>>
>> Changes since v3:
>>
>> - moved to new XSCOM model
>> - kept the write op on the XSCOM memory region for later use
>>
>> Changes since v2:
>>
>> - added a XSCOM memory region to handle access to the EX core
>> registers
>> - extended the PnvCore object with a XSCOM_INTERFACE so that we can
>> use pnv_xscom_pcba() and pnv_xscom_addr() to handle XSCOM address
>> translation.
>>
>> hw/ppc/pnv.c | 4 ++++
>> hw/ppc/pnv_core.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++
>> include/hw/ppc/pnv_core.h | 2 ++
>> include/hw/ppc/pnv_xscom.h | 19 ++++++++++++++++++
>> 4 files changed, 75 insertions(+)
>>
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index 5e19b6880387..ffe245fe59d2 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -620,6 +620,10 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
>> &error_fatal);
>> object_unref(OBJECT(pnv_core));
>> i++;
>> +
>> + memory_region_add_subregion(&chip->xscom,
>> + PNV_XSCOM_EX_CORE_BASE(core_hwid) << 3,
>> + &PNV_CORE(pnv_core)->xscom_regs);
>
> Might be worth adding some convenience functions for doing the various
> bits of xscom MR juggling, otherwise this looks fine.
To do the 8 byte shifting ? or something like this :
void pnv_xscom_add_subregion(PnvChip *chip, uint32_t pcba,
MemoryRegion *subregion);
or even :
void pnv_xscom_add_subregion(PnvChip *chip, PnvXScomInterface *obj)
but that would require some more handlers under PnvXScomInterface.
Thanks,
C.
>> }
>> g_free(typename);
>> }
>> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
>> index d37788f142f4..a1c8a14f06b6 100644
>> --- a/hw/ppc/pnv_core.c
>> +++ b/hw/ppc/pnv_core.c
>> @@ -19,6 +19,7 @@
>> #include "qemu/osdep.h"
>> #include "sysemu/sysemu.h"
>> #include "qapi/error.h"
>> +#include "qemu/log.h"
>> #include "target-ppc/cpu.h"
>> #include "hw/ppc/ppc.h"
>> #include "hw/ppc/pnv.h"
>> @@ -64,6 +65,51 @@ static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp)
>> powernv_cpu_reset(cpu);
>> }
>>
>> +/*
>> + * These values are read by the PowerNV HW monitors under Linux
>> + */
>> +#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
>> +#define PNV_XSCOM_EX_DTS_RESULT1 0x50001
>> +
>> +static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr,
>> + unsigned int width)
>> +{
>> + uint32_t offset = addr >> 3;
>> + uint64_t val = 0;
>> +
>> + /* The result should be 38 C */
>> + switch (offset) {
>> + case PNV_XSCOM_EX_DTS_RESULT0:
>> + val = 0x26f024f023f0000ull;
>> + break;
>> + case PNV_XSCOM_EX_DTS_RESULT1:
>> + val = 0x24f000000000000ull;
>> + break;
>> + default:
>> + qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx,
>> + addr);
>> + }
>> +
>> + return val;
>> +}
>> +
>> +static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val,
>> + unsigned int width)
>> +{
>> + qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx,
>> + addr);
>> +}
>> +
>> +static const MemoryRegionOps pnv_core_xscom_ops = {
>> + .read = pnv_core_xscom_read,
>> + .write = pnv_core_xscom_write,
>> + .valid.min_access_size = 8,
>> + .valid.max_access_size = 8,
>> + .impl.min_access_size = 8,
>> + .impl.max_access_size = 8,
>> + .endianness = DEVICE_BIG_ENDIAN,
>> +};
>> +
>> static void pnv_core_realize_child(Object *child, Error **errp)
>> {
>> Error *local_err = NULL;
>> @@ -119,6 +165,10 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
>> goto err;
>> }
>> }
>> +
>> + snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
>> + memory_region_init_io(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_ops,
>> + pc, name, PNV_XSCOM_EX_CORE_SIZE << 3);
>> return;
>>
>> err:
>> diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
>> index a151e281c017..2955a41c901f 100644
>> --- a/include/hw/ppc/pnv_core.h
>> +++ b/include/hw/ppc/pnv_core.h
>> @@ -36,6 +36,8 @@ typedef struct PnvCore {
>> /*< public >*/
>> void *threads;
>> uint32_t pir;
>> +
>> + MemoryRegion xscom_regs;
>> } PnvCore;
>>
>> typedef struct PnvCoreClass {
>> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
>> index f50eb0bc4099..79975a6cbe46 100644
>> --- a/include/hw/ppc/pnv_xscom.h
>> +++ b/include/hw/ppc/pnv_xscom.h
>> @@ -41,6 +41,25 @@ typedef struct PnvXScomInterfaceClass {
>> int (*populate)(PnvXScomInterface *dev, void *fdt, int offset);
>> } PnvXScomInterfaceClass;
>>
>> +/*
>> + * Layout of the XSCOM PCB addresses of EX core 1
>> + *
>> + * GPIO 0x1100xxxx
>> + * SCOM 0x1101xxxx
>> + * OHA 0x1102xxxx
>> + * CLOCK CTL 0x1103xxxx
>> + * FIR 0x1104xxxx
>> + * THERM 0x1105xxxx
>> + * <reserved> 0x1106xxxx
>> + * ..
>> + * 0x110Exxxx
>> + * PCB SLAVE 0x110Fxxxx
>> + */
>> +
>> +#define PNV_XSCOM_EX_BASE 0x10000000
>> +#define PNV_XSCOM_EX_CORE_BASE(i) (PNV_XSCOM_EX_BASE | (((uint64_t)i) << 24))
>> +#define PNV_XSCOM_EX_CORE_SIZE 0x100000
>> +
>> extern void pnv_xscom_realize(PnvChip *chip, Error **errp);
>> extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset);
>>
>
next prev parent reply other threads:[~2016-10-13 6:50 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-03 7:24 [Qemu-devel] [PATCH v4 00/20] ppc/pnv: booting the kernel and reaching user space Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 01/20] ppc/pnv: add skeleton PowerNV platform Cédric Le Goater
2016-10-07 4:14 ` David Gibson
2016-10-07 4:16 ` David Gibson
2016-10-07 7:38 ` Cédric Le Goater
2016-10-07 16:29 ` Jeff Cody
2016-10-07 8:36 ` Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 02/20] ppc/pnv: add a PnvChip object Cédric Le Goater
2016-10-07 4:26 ` David Gibson
2016-10-07 9:16 ` Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 03/20] ppc/pnv: add a core mask to PnvChip Cédric Le Goater
2016-10-07 4:32 ` David Gibson
2016-10-07 5:01 ` Benjamin Herrenschmidt
2016-10-07 5:11 ` David Gibson
2016-10-07 8:24 ` Cédric Le Goater
2016-10-10 12:56 ` Cédric Le Goater
2016-10-11 10:24 ` David Gibson
2016-10-12 8:53 ` Cédric Le Goater
2016-10-13 0:24 ` David Gibson
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 04/20] ppc/pnv: add a PIR handler " Cédric Le Goater
2016-10-07 4:34 ` David Gibson
2016-10-10 8:14 ` Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 05/20] ppc/pnv: add a PnvCore object Cédric Le Goater
2016-10-07 4:52 ` David Gibson
2016-10-10 8:07 ` Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 06/20] ppc/pnv: add XSCOM infrastructure Cédric Le Goater
2016-10-13 0:41 ` David Gibson
2016-10-13 6:26 ` Cédric Le Goater
2016-11-07 8:26 ` Olaf Hering
2016-11-07 8:32 ` Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 07/20] ppc/pnv: add XSCOM handlers to PnvCore Cédric Le Goater
2016-10-13 0:51 ` David Gibson
2016-10-13 6:50 ` Cédric Le Goater [this message]
2016-10-13 22:24 ` David Gibson
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 08/20] ppc/pnv: add a LPC controller Cédric Le Goater
2016-10-13 2:52 ` David Gibson
2016-10-13 2:53 ` David Gibson
2016-10-13 6:31 ` Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 09/20] ppc/pnv: add a ISA bus Cédric Le Goater
2016-10-13 2:58 ` David Gibson
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 10/20] ppc/xics: Make the ICSState a list Cédric Le Goater
2016-10-14 5:32 ` David Gibson
2016-10-14 7:35 ` Cédric Le Goater
2016-10-16 23:53 ` David Gibson
2016-10-17 8:13 ` Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 11/20] ppc/xics: Split ICS into ics-base and ics class Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 12/20] ppc/xics: Add xics to the monitor "info pic" command Cédric Le Goater
2016-10-14 5:30 ` David Gibson
2016-10-14 7:39 ` Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 13/20] ppc/xics: introduce helpers to find an ICP from some (CPU) index Cédric Le Goater
2016-10-14 5:34 ` David Gibson
2016-10-14 7:44 ` Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 14/20] ppc/xics: introduce a helper to insert a new ics Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 15/20] ppc/xics: Add "native" XICS subclass Cédric Le Goater
2016-10-14 6:10 ` David Gibson
2016-10-14 9:40 ` Cédric Le Goater
2016-10-16 23:51 ` David Gibson
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 16/20] ppc/pnv: add a XICS native to each PowerNV chip Cédric Le Goater
2016-10-14 6:18 ` David Gibson
2016-10-18 14:47 ` Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 17/20] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt Cédric Le Goater
2016-10-14 6:32 ` David Gibson
2016-10-14 7:13 ` Benjamin Herrenschmidt
2016-10-14 8:07 ` Cédric Le Goater
2016-10-16 23:52 ` David Gibson
2016-10-17 8:17 ` Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 18/20] ppc/pnv: Add OCC model stub with interrupt support Cédric Le Goater
2016-10-14 6:34 ` David Gibson
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 19/20] ppc/pnv: Add Naples chip support for LPC interrupts Cédric Le Goater
2016-10-14 6:36 ` David Gibson
2016-10-14 7:47 ` Cédric Le Goater
2016-10-03 7:24 ` [Qemu-devel] [PATCH v4 20/20] ppc/pnv: add support for POWER9 LPC Controller Cédric Le Goater
2016-10-14 6:43 ` David Gibson
2016-10-03 7:59 ` [Qemu-devel] [PATCH v4 00/20] ppc/pnv: booting the kernel and reaching user space no-reply
2016-10-03 8:21 ` Cédric Le Goater
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