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[173.73.95.180]) by smtp.gmail.com with ESMTPSA id c3-20020a05620a268300b006b5d9a1d326sm3304568qkp.83.2022.08.12.21.25.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 Aug 2022 21:25:16 -0700 (PDT) Subject: Re: [PATCH 25/31] clk: mediatek: add CLK_XTAL support for clock driver To: Weijie Gao , u-boot@lists.denx.de Cc: GSS_MTK_Uboot_upstream , Lukasz Majewski References: <5c31c620ecdaa423c2761a633c7869b4af3fbf89.1659581119.git.weijie.gao@mediatek.com> From: Sean Anderson Message-ID: Date: Sat, 13 Aug 2022 00:25:16 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <5c31c620ecdaa423c2761a633c7869b4af3fbf89.1659581119.git.weijie.gao@mediatek.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 8/3/22 11:36 PM, Weijie Gao wrote: > This add CLK_XTAL macro and flag to mediatek clock driver common part, > to make thi SoC that has clock directlly connect to XTAL working. nit: this.. directly But I'm having trouble reading your commit message. Perhaps something like > This adds the CLK_XTAL macro/flag to allow modeling clocks which are > directly connected to a fixed-rate clock. > > Signed-off-by: Weijie Gao > --- > drivers/clk/mediatek/clk-mtk.c | 3 +++ > drivers/clk/mediatek/clk-mtk.h | 3 ++- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c > index be3846c85b..5a4650d137 100644 > --- a/drivers/clk/mediatek/clk-mtk.c > +++ b/drivers/clk/mediatek/clk-mtk.c > @@ -296,6 +296,7 @@ static ulong mtk_topckgen_get_factor_rate(struct clk > *clk, u32 off) > rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); > break; > > + case CLK_PARENT_XTAL: > default: > rate = priv->tree->xtal_rate; > } > @@ -314,6 +315,8 @@ static ulong mtk_infrasys_get_factor_rate(struct clk > *clk, u32 off) > rate = mtk_clk_find_parent_rate(clk, fdiv->parent, > priv->parent); > break; > + case CLK_PARENT_XTAL: > + rate = priv->tree->xtal_rate; > default: > rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); > } > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h > index 8536275671..211356697b 100644 > --- a/drivers/clk/mediatek/clk-mtk.h > +++ b/drivers/clk/mediatek/clk-mtk.h > @@ -26,7 +26,8 @@ > #define CLK_PARENT_APMIXED BIT(4) > #define CLK_PARENT_TOPCKGEN BIT(5) > #define CLK_PARENT_INFRASYS BIT(6) > -#define CLK_PARENT_MASK GENMASK(6, 4) > +#define CLK_PARENT_XTAL BIT(7) > +#define CLK_PARENT_MASK GENMASK(7, 4) > > #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34 > >