[PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work

[PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work

[Mauro Carvalho Chehab]

Hi Rob,

After our discussions, I'm opting to submit first the DT bindings for the
Kirin 970 PCIe support.

Patch 1 is there just because patch 2 needs. You already acked on it.

Patch 5 is also there just as an example of the entire stuff added to
the DTS file.

The core of this series are patches 2 to 4. They contain the conversion
of the kirin-pcie.txt file to the DT schema, and adds the needed
bindings.

Currently, it generates some warnings:

   Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: pcie@4,0:compatible: None of ['pciclass,0604'] are valid under the given schema
	From schema: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
	
  Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@4,0: reset-gpios: [[4294967295, 1, 0]] is too short

Not sure how/where to fix those. Perhaps at the pci-bus.yaml?

Please review.

Thanks!
Mauro

Manivannan Sadhasivam (1):
  arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller
    hardware

Mauro Carvalho Chehab (4):
  dt-bindings: PCI: kirin: Fix compatible string
  dt-bindings: PCI: kirin: convert kirin-pcie.txt to yaml
  dt-bindings: PCI: kirin: Add support for Kirin970
  dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY

 .../bindings/pci/hisilicon,kirin-pcie.yaml    | 145 ++++++++++++++++++
 .../devicetree/bindings/pci/kirin-pcie.txt    |  50 ------
 .../devicetree/bindings/pci/snps,dw-pcie.yaml |   2 +-
 .../phy/hisilicon,phy-hi3670-pcie.yaml        |  86 +++++++++++
 MAINTAINERS                                   |   2 +-
 arch/arm64/boot/dts/hisilicon/hi3670.dtsi     |  99 ++++++++++++
 6 files changed, 332 insertions(+), 52 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
 delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml

-- 
2.31.1

[PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work

[Mauro Carvalho Chehab]

Hi Rob,

After our discussions, I'm opting to submit first the DT bindings for the
Kirin 970 PCIe support.

Patch 1 is there just because patch 2 needs. You already acked on it.

Patch 5 is also there just as an example of the entire stuff added to
the DTS file.

The core of this series are patches 2 to 4. They contain the conversion
of the kirin-pcie.txt file to the DT schema, and adds the needed
bindings.

Currently, it generates some warnings:

   Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: pcie@4,0:compatible: None of ['pciclass,0604'] are valid under the given schema
	From schema: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
	
  Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@4,0: reset-gpios: [[4294967295, 1, 0]] is too short

Not sure how/where to fix those. Perhaps at the pci-bus.yaml?

Please review.

Thanks!
Mauro

Manivannan Sadhasivam (1):
  arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller
    hardware

Mauro Carvalho Chehab (4):
  dt-bindings: PCI: kirin: Fix compatible string
  dt-bindings: PCI: kirin: convert kirin-pcie.txt to yaml
  dt-bindings: PCI: kirin: Add support for Kirin970
  dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY

 .../bindings/pci/hisilicon,kirin-pcie.yaml    | 145 ++++++++++++++++++
 .../devicetree/bindings/pci/kirin-pcie.txt    |  50 ------
 .../devicetree/bindings/pci/snps,dw-pcie.yaml |   2 +-
 .../phy/hisilicon,phy-hi3670-pcie.yaml        |  86 +++++++++++
 MAINTAINERS                                   |   2 +-
 arch/arm64/boot/dts/hisilicon/hi3670.dtsi     |  99 ++++++++++++
 6 files changed, 332 insertions(+), 52 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
 delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml

-- 
2.31.1



-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work

[Mauro Carvalho Chehab]

Hi Rob,

After our discussions, I'm opting to submit first the DT bindings for the
Kirin 970 PCIe support.

Patch 1 is there just because patch 2 needs. You already acked on it.

Patch 5 is also there just as an example of the entire stuff added to
the DTS file.

The core of this series are patches 2 to 4. They contain the conversion
of the kirin-pcie.txt file to the DT schema, and adds the needed
bindings.

Currently, it generates some warnings:

   Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: pcie@4,0:compatible: None of ['pciclass,0604'] are valid under the given schema
	From schema: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
	
  Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@4,0: reset-gpios: [[4294967295, 1, 0]] is too short

Not sure how/where to fix those. Perhaps at the pci-bus.yaml?

Please review.

Thanks!
Mauro

Manivannan Sadhasivam (1):
  arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller
    hardware

Mauro Carvalho Chehab (4):
  dt-bindings: PCI: kirin: Fix compatible string
  dt-bindings: PCI: kirin: convert kirin-pcie.txt to yaml
  dt-bindings: PCI: kirin: Add support for Kirin970
  dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY

 .../bindings/pci/hisilicon,kirin-pcie.yaml    | 145 ++++++++++++++++++
 .../devicetree/bindings/pci/kirin-pcie.txt    |  50 ------
 .../devicetree/bindings/pci/snps,dw-pcie.yaml |   2 +-
 .../phy/hisilicon,phy-hi3670-pcie.yaml        |  86 +++++++++++
 MAINTAINERS                                   |   2 +-
 arch/arm64/boot/dts/hisilicon/hi3670.dtsi     |  99 ++++++++++++
 6 files changed, 332 insertions(+), 52 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
 delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml

-- 
2.31.1



_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 1/5] dt-bindings: PCI: kirin: Fix compatible string

[Mauro Carvalho Chehab]

The pcie-kirin driver doesn't declare a hisilicon,kirin-pcie.
Also, remove the useless comment after the description, as other
compat will be supported by the same driver in the future.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
 Documentation/devicetree/bindings/pci/kirin-pcie.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
index 7db30534498f..7adab8999a6a 100644
--- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -9,7 +9,7 @@ Additional properties are described here:
 
 Required properties
 - compatible:
-	"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
+	"hisilicon,kirin960-pcie"
 - reg: Should contain rc_dbi, apb, phy, config registers location and length.
 - reg-names: Must include the following entries:
   "dbi": controller configuration registers;
@@ -23,7 +23,7 @@ Optional properties:
 Example based on kirin960:
 
 	pcie@f4000000 {
-		compatible = "hisilicon,kirin-pcie";
+		compatible = "hisilicon,kirin960-pcie";
 		reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
 		      <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
 		reg-names = "dbi","apb","phy", "config";
-- 
2.31.1

[PATCH 2/5] dt-bindings: PCI: kirin: convert kirin-pcie.txt to yaml

[Mauro Carvalho Chehab]

Convert the file into a JSON description at the yaml format.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
 .../bindings/pci/hisilicon,kirin-pcie.yaml    | 86 +++++++++++++++++++
 .../devicetree/bindings/pci/kirin-pcie.txt    | 50 -----------
 .../devicetree/bindings/pci/snps,dw-pcie.yaml |  2 +-
 MAINTAINERS                                   |  2 +-
 4 files changed, 88 insertions(+), 52 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
 delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
new file mode 100644
index 000000000000..90cab09e8d4b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Kirin SoCs PCIe host DT description
+
+maintainers:
+  - Xiaowei Song <songxiaowei@hisilicon.com>
+  - Binghui Wang <wangbinghui@hisilicon.com>
+
+description: |
+  Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
+  It shares common functions with the PCIe DesignWare core driver and
+  inherits common properties defined in
+  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
+
+allOf:
+  - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+properties:
+  compatible:
+    contains:
+      enum:
+        - hisilicon,kirin960-pcie
+
+  reg:
+    description: |
+      Should contain dbi, apb, config registers location and length.
+      For HiKey960, it should also contain phy.
+    minItems: 3
+    maxItems: 4
+
+  reg-names:
+    minItems: 3
+    maxItems: 4
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/hi3660-clock.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pcie@f4000000 {
+        compatible = "hisilicon,kirin960-pcie";
+        reg = <0x0 0xf4000000 0x0 0x1000>,
+              <0x0 0xff3fe000 0x0 0x1000>,
+              <0x0 0xf3f20000 0x0 0x40000>,
+              <0x0 0xf5000000 0x0 0x2000>;
+        reg-names = "dbi", "apb", "phy", "config";
+        bus-range = <0x0  0x1>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        device_type = "pci";
+        ranges = <0x02000000 0x0 0x00000000
+                  0x0 0xf6000000
+                  0x0 0x02000000>;
+        num-lanes = <1>;
+        #interrupt-cells = <1>;
+        interrupts = <0 283 4>;
+        interrupt-names = "msi";
+        interrupt-map-mask = <0xf800 0 0 7>;
+        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+                 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+                 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+                 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+                 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+        clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
+                      "pcie_apb_sys", "pcie_aclk";
+      };
+    };
diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
deleted file mode 100644
index 7adab8999a6a..000000000000
--- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-HiSilicon Kirin SoCs PCIe host DT description
-
-Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
-It shares common functions with the PCIe DesignWare core driver and
-inherits common properties defined in
-Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
-
-Additional properties are described here:
-
-Required properties
-- compatible:
-	"hisilicon,kirin960-pcie"
-- reg: Should contain rc_dbi, apb, phy, config registers location and length.
-- reg-names: Must include the following entries:
-  "dbi": controller configuration registers;
-  "apb": apb Ctrl register defined by Kirin;
-  "phy": apb PHY register defined by Kirin;
-  "config": PCIe configuration space registers.
-- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
-
-Optional properties:
-
-Example based on kirin960:
-
-	pcie@f4000000 {
-		compatible = "hisilicon,kirin960-pcie";
-		reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
-		      <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
-		reg-names = "dbi","apb","phy", "config";
-		bus-range = <0x0  0x1>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
-		num-lanes = <1>;
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0xf800 0 0 7>;
-		interrupt-map = <0x0 0 0 1 &gic 0 0 0  282 4>,
-				<0x0 0 0 2 &gic 0 0 0  283 4>,
-				<0x0 0 0 3 &gic 0 0 0  284 4>,
-				<0x0 0 0 4 &gic 0 0 0  285 4>;
-		clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
-			 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
-			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
-			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
-			 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
-		clock-names = "pcie_phy_ref", "pcie_aux",
-			      "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
-		reset-gpios = <&gpio11 1 0 >;
-	};
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
index a8c1db879fb9..6c7501b8df01 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
@@ -34,7 +34,7 @@ properties:
     minItems: 2
     maxItems: 5
     items:
-      enum: [dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link]
+      enum: [dbi, dbi2, config, atu, apb, app, elbi, mgmt, ctrl, parf, cfg, link, phy]
 
   num-lanes:
     description: |
diff --git a/MAINTAINERS b/MAINTAINERS
index 672299764ec7..3e2d849b4f7d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14413,7 +14413,7 @@ M:	Xiaowei Song <songxiaowei@hisilicon.com>
 M:	Binghui Wang <wangbinghui@hisilicon.com>
 L:	linux-pci@vger.kernel.org
 S:	Maintained
-F:	Documentation/devicetree/bindings/pci/kirin-pcie.txt
+F:	Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
 F:	drivers/pci/controller/dwc/pcie-kirin.c
 
 PCIE DRIVER FOR HISILICON STB
-- 
2.31.1

[PATCH 3/5] dt-bindings: PCI: kirin: Add support for Kirin970

[Mauro Carvalho Chehab]

Add a new compatible, plus the new bindings needed by
HiKey970 board.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
 .../bindings/pci/hisilicon,kirin-pcie.yaml    | 61 ++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
index 90cab09e8d4b..bb0c3a081d68 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
@@ -24,11 +24,13 @@ properties:
     contains:
       enum:
         - hisilicon,kirin960-pcie
+        - hisilicon,kirin970-pcie
 
   reg:
     description: |
       Should contain dbi, apb, config registers location and length.
-      For HiKey960, it should also contain phy.
+      For HiKey960, it should also contain phy. All other devices
+      should use a separate phy driver.
     minItems: 3
     maxItems: 4
 
@@ -47,6 +49,7 @@ examples:
   - |
     #include <dt-bindings/interrupt-controller/arm-gic.h>
     #include <dt-bindings/clock/hi3660-clock.h>
+    #include <dt-bindings/clock/hi3670-clock.h>
 
     soc {
       #address-cells = <2>;
@@ -83,4 +86,60 @@ examples:
         clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
                       "pcie_apb_sys", "pcie_aclk";
       };
+
+      pcie@f5000000 {
+        compatible = "hisilicon,kirin970-pcie";
+        reg = <0x0 0xf4000000 0x0 0x1000000>,
+              <0x0 0xfc180000 0x0 0x1000>,
+              <0x0 0xf5000000 0x0 0x2000>;
+        reg-names = "dbi", "apb", "config";
+        bus-range = <0x0  0x1>;
+        msi-parent = <&its_pcie>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        device_type = "pci";
+        phys = <&pcie_phy>;
+        ranges = <0x02000000 0x0 0x00000000
+                  0x0 0xf6000000
+                  0x0 0x02000000>;
+        num-lanes = <1>;
+        #interrupt-cells = <1>;
+        interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "msi";
+        interrupt-map-mask = <0 0 0 7>;
+        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+        pcie@4,0 { // Lane 4: M.2
+          reg = <0 0 0 0 0>;
+          compatible = "pciclass,0604";
+          device_type = "pci";
+          reset-gpios = <&gpio7 1 0>;
+          clkreq-gpios = <&gpio27 3 0 >;
+          #address-cells = <3>;
+          #size-cells = <2>;
+          ranges;
+        };
+        pcie@5,0 { // Lane 5: Mini PCIe
+          reg = <0 0 0 0 0>;
+          compatible = "pciclass,0604";
+          device_type = "pci";
+          reset-gpios = <&gpio7 2 0>;
+          clkreq-gpios = <&gpio17 0 0 >;
+          #address-cells = <3>;
+          #size-cells = <2>;
+          ranges;
+        };
+        pcie@7,0 { // Lane 7: Ethernet
+          reg = <0 0 0 0 0>;
+          compatible = "pciclass,0604";
+          device_type = "pci";
+          reset-gpios = <&gpio7 3 0>;
+          clkreq-gpios = <&gpio20 0 0 >;
+          #address-cells = <3>;
+          #size-cells = <2>;
+          ranges;
+        };
+      };
     };
-- 
2.31.1

Re: [PATCH 3/5] dt-bindings: PCI: kirin: Add support for Kirin970

[Rob Herring]

On Thu, Jul 29, 2021 at 5:56 AM Mauro Carvalho Chehab
<mchehab+huawei@kernel.org> wrote:
>
> Add a new compatible, plus the new bindings needed by
> HiKey970 board.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> ---
>  .../bindings/pci/hisilicon,kirin-pcie.yaml    | 61 ++++++++++++++++++-
>  1 file changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> index 90cab09e8d4b..bb0c3a081d68 100644
> --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> @@ -24,11 +24,13 @@ properties:
>      contains:
>        enum:
>          - hisilicon,kirin960-pcie
> +        - hisilicon,kirin970-pcie
>
>    reg:
>      description: |
>        Should contain dbi, apb, config registers location and length.
> -      For HiKey960, it should also contain phy.
> +      For HiKey960, it should also contain phy. All other devices
> +      should use a separate phy driver.
>      minItems: 3
>      maxItems: 4
>
> @@ -47,6 +49,7 @@ examples:
>    - |
>      #include <dt-bindings/interrupt-controller/arm-gic.h>
>      #include <dt-bindings/clock/hi3660-clock.h>
> +    #include <dt-bindings/clock/hi3670-clock.h>
>
>      soc {
>        #address-cells = <2>;
> @@ -83,4 +86,60 @@ examples:
>          clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
>                        "pcie_apb_sys", "pcie_aclk";
>        };
> +
> +      pcie@f5000000 {
> +        compatible = "hisilicon,kirin970-pcie";
> +        reg = <0x0 0xf4000000 0x0 0x1000000>,
> +              <0x0 0xfc180000 0x0 0x1000>,
> +              <0x0 0xf5000000 0x0 0x2000>;
> +        reg-names = "dbi", "apb", "config";
> +        bus-range = <0x0  0x1>;
> +        msi-parent = <&its_pcie>;
> +        #address-cells = <3>;
> +        #size-cells = <2>;
> +        device_type = "pci";
> +        phys = <&pcie_phy>;
> +        ranges = <0x02000000 0x0 0x00000000
> +                  0x0 0xf6000000
> +                  0x0 0x02000000>;
> +        num-lanes = <1>;
> +        #interrupt-cells = <1>;
> +        interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-names = "msi";
> +        interrupt-map-mask = <0 0 0 7>;
> +        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> +                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> +                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> +                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
> +        pcie@4,0 { // Lane 4: M.2

You are missing a level here. You need the upstream bridge device. I
figured this out for you, why am I having to correct it?

Isn't this supposed to be Device 1 as 1 and 4 are swapped in terms of
lane number and device number.

> +          reg = <0 0 0 0 0>;

Not the right address. I would have expected a dtc warning on this.

> +          compatible = "pciclass,0604";
> +          device_type = "pci";
> +          reset-gpios = <&gpio7 1 0>;
> +          clkreq-gpios = <&gpio27 3 0 >;
> +          #address-cells = <3>;
> +          #size-cells = <2>;
> +          ranges;
> +        };
> +        pcie@5,0 { // Lane 5: Mini PCIe

It's device 5 not lane 5.


> +          reg = <0 0 0 0 0>;
> +          compatible = "pciclass,0604";
> +          device_type = "pci";
> +          reset-gpios = <&gpio7 2 0>;
> +          clkreq-gpios = <&gpio17 0 0 >;
> +          #address-cells = <3>;
> +          #size-cells = <2>;
> +          ranges;
> +        };
> +        pcie@7,0 { // Lane 7: Ethernet
> +          reg = <0 0 0 0 0>;
> +          compatible = "pciclass,0604";
> +          device_type = "pci";
> +          reset-gpios = <&gpio7 3 0>;
> +          clkreq-gpios = <&gpio20 0 0 >;
> +          #address-cells = <3>;
> +          #size-cells = <2>;
> +          ranges;
> +        };
> +      };
>      };
> --
> 2.31.1
>

Re: [PATCH 3/5] dt-bindings: PCI: kirin: Add support for Kirin970

[Rob Herring]

On Thu, Jul 29, 2021 at 5:56 AM Mauro Carvalho Chehab
<mchehab+huawei@kernel.org> wrote:
>
> Add a new compatible, plus the new bindings needed by
> HiKey970 board.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> ---
>  .../bindings/pci/hisilicon,kirin-pcie.yaml    | 61 ++++++++++++++++++-
>  1 file changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> index 90cab09e8d4b..bb0c3a081d68 100644
> --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> @@ -24,11 +24,13 @@ properties:
>      contains:
>        enum:
>          - hisilicon,kirin960-pcie
> +        - hisilicon,kirin970-pcie
>
>    reg:
>      description: |
>        Should contain dbi, apb, config registers location and length.
> -      For HiKey960, it should also contain phy.
> +      For HiKey960, it should also contain phy. All other devices
> +      should use a separate phy driver.
>      minItems: 3
>      maxItems: 4
>
> @@ -47,6 +49,7 @@ examples:
>    - |
>      #include <dt-bindings/interrupt-controller/arm-gic.h>
>      #include <dt-bindings/clock/hi3660-clock.h>
> +    #include <dt-bindings/clock/hi3670-clock.h>
>
>      soc {
>        #address-cells = <2>;
> @@ -83,4 +86,60 @@ examples:
>          clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
>                        "pcie_apb_sys", "pcie_aclk";
>        };
> +
> +      pcie@f5000000 {
> +        compatible = "hisilicon,kirin970-pcie";
> +        reg = <0x0 0xf4000000 0x0 0x1000000>,
> +              <0x0 0xfc180000 0x0 0x1000>,
> +              <0x0 0xf5000000 0x0 0x2000>;
> +        reg-names = "dbi", "apb", "config";
> +        bus-range = <0x0  0x1>;
> +        msi-parent = <&its_pcie>;
> +        #address-cells = <3>;
> +        #size-cells = <2>;
> +        device_type = "pci";
> +        phys = <&pcie_phy>;
> +        ranges = <0x02000000 0x0 0x00000000
> +                  0x0 0xf6000000
> +                  0x0 0x02000000>;
> +        num-lanes = <1>;
> +        #interrupt-cells = <1>;
> +        interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-names = "msi";
> +        interrupt-map-mask = <0 0 0 7>;
> +        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> +                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> +                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> +                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
> +        pcie@4,0 { // Lane 4: M.2
> +          reg = <0 0 0 0 0>;
> +          compatible = "pciclass,0604";
> +          device_type = "pci";
> +          reset-gpios = <&gpio7 1 0>;
> +          clkreq-gpios = <&gpio27 3 0 >;

Looking at the schematics some more, this is not right. CLKREQ# is an
input from the device, and they are not connected to any GPIO (just
pulled high) on hikey970. These GPIOs are simply clock enables and
very much specific to hikey. So I'd call this 'hisilicon,clken-gpios'
and you can just stick them in the host bridge node.

I think the way the board should have been designed is the CLKREQ#
signals to the clock driver chip OE signals. Then there'd be no s/w
control needed.

Rob

Re: [PATCH 3/5] dt-bindings: PCI: kirin: Add support for Kirin970

[Mauro Carvalho Chehab]

Em Thu, 29 Jul 2021 09:20:15 -0600
Rob Herring <robh@kernel.org> escreveu:

> On Thu, Jul 29, 2021 at 5:56 AM Mauro Carvalho Chehab
> <mchehab+huawei@kernel.org> wrote:
> >
> > Add a new compatible, plus the new bindings needed by
> > HiKey970 board.
> >
> > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> > ---
> >  .../bindings/pci/hisilicon,kirin-pcie.yaml    | 61 ++++++++++++++++++-
> >  1 file changed, 60 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> > index 90cab09e8d4b..bb0c3a081d68 100644
> > --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> > @@ -24,11 +24,13 @@ properties:
> >      contains:
> >        enum:
> >          - hisilicon,kirin960-pcie
> > +        - hisilicon,kirin970-pcie
> >
> >    reg:
> >      description: |
> >        Should contain dbi, apb, config registers location and length.
> > -      For HiKey960, it should also contain phy.
> > +      For HiKey960, it should also contain phy. All other devices
> > +      should use a separate phy driver.
> >      minItems: 3
> >      maxItems: 4
> >
> > @@ -47,6 +49,7 @@ examples:
> >    - |
> >      #include <dt-bindings/interrupt-controller/arm-gic.h>
> >      #include <dt-bindings/clock/hi3660-clock.h>
> > +    #include <dt-bindings/clock/hi3670-clock.h>
> >
> >      soc {
> >        #address-cells = <2>;
> > @@ -83,4 +86,60 @@ examples:
> >          clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
> >                        "pcie_apb_sys", "pcie_aclk";
> >        };
> > +
> > +      pcie@f5000000 {
> > +        compatible = "hisilicon,kirin970-pcie";
> > +        reg = <0x0 0xf4000000 0x0 0x1000000>,
> > +              <0x0 0xfc180000 0x0 0x1000>,
> > +              <0x0 0xf5000000 0x0 0x2000>;
> > +        reg-names = "dbi", "apb", "config";
> > +        bus-range = <0x0  0x1>;
> > +        msi-parent = <&its_pcie>;
> > +        #address-cells = <3>;
> > +        #size-cells = <2>;
> > +        device_type = "pci";
> > +        phys = <&pcie_phy>;
> > +        ranges = <0x02000000 0x0 0x00000000
> > +                  0x0 0xf6000000
> > +                  0x0 0x02000000>;
> > +        num-lanes = <1>;
> > +        #interrupt-cells = <1>;
> > +        interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
> > +        interrupt-names = "msi";
> > +        interrupt-map-mask = <0 0 0 7>;
> > +        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> > +                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> > +                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> > +                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
> > +        pcie@4,0 { // Lane 4: M.2
> > +          reg = <0 0 0 0 0>;
> > +          compatible = "pciclass,0604";
> > +          device_type = "pci";
> > +          reset-gpios = <&gpio7 1 0>;
> > +          clkreq-gpios = <&gpio27 3 0 >;  
> 
> Looking at the schematics some more, this is not right. CLKREQ# is an
> input from the device, and they are not connected to any GPIO (just
> pulled high) on hikey970. These GPIOs are simply clock enables and
> very much specific to hikey. So I'd call this 'hisilicon,clken-gpios'
> and you can just stick them in the host bridge node.
> 

Ok. If I understood your review, the schema will then be:

      pcie@f4000000 {
        compatible = "hisilicon,kirin970-pcie";
        reg = <0x0 0xf4000000 0x0 0x1000000>,
              <0x0 0xfc180000 0x0 0x1000>,
              <0x0 0xf5000000 0x0 0x2000>;
        reg-names = "dbi", "apb", "config";
        bus-range = <0x0  0x1>;
        msi-parent = <&its_pcie>;
        #address-cells = <3>;
        #size-cells = <2>;
        device_type = "pci";
        phys = <&pcie_phy>;
        ranges = <0x02000000 0x0 0x00000000
                  0x0 0xf6000000
                  0x0 0x02000000>;
        num-lanes = <1>;
        #interrupt-cells = <1>;
        interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "msi";
        interrupt-map-mask = <0 0 0 7>;
        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
        reset-gpios = <&gpio7 0 0>;

        pcie@0 { // Lane 0: upstream
          reg = <0 0 0 0 0>;
          compatible = "pciclass,0604";
          device_type = "pci";
          #address-cells = <3>;
          #size-cells = <2>;
          hisilicon,clken-gpios = <&gpio27 3 0 >, <&gpio17 0 0 >, <&gpio20 6 0 >;
          ranges;

          pcie@1,0 { // Lane 4: M.2
            reg = <0x800 0 0 0 0>;
            compatible = "pciclass,0604";
            device_type = "pci";
            reset-gpios = <&gpio3 1 0>;
            #address-cells = <3>;
            #size-cells = <2>;
            ranges;
          };

          pcie@5,0 { // Lane 5: Mini PCIe
            reg = <0x2800 0 0 0 0>;
            compatible = "pciclass,0604";
            device_type = "pci";
            reset-gpios = <&gpio27 4 0 >;
            #address-cells = <3>;
            #size-cells = <2>;
            ranges;
          };

          pcie@7,0 { // Lane 7: Ethernet
            reg = <0x3800 0 0 0 0>;
            compatible = "pciclass,0604";
            device_type = "pci";
            reset-gpios = <&gpio25 2 0 >;
            #address-cells = <3>;
            #size-cells = <2>;
            ranges;
          };
        };
      };
    };

Right?

After updating the dt-schema from your git tree, the above doesn't 
generate warnings anymore.

Thanks,
Mauro

Re: [PATCH 3/5] dt-bindings: PCI: kirin: Add support for Kirin970

[Rob Herring]

On Thu, Jul 29, 2021 at 09:03:37PM +0200, Mauro Carvalho Chehab wrote:
> Em Thu, 29 Jul 2021 09:20:15 -0600
> Rob Herring <robh@kernel.org> escreveu:
> 
> > On Thu, Jul 29, 2021 at 5:56 AM Mauro Carvalho Chehab
> > <mchehab+huawei@kernel.org> wrote:
> > >
> > > Add a new compatible, plus the new bindings needed by
> > > HiKey970 board.
> > >
> > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> > > ---
> > >  .../bindings/pci/hisilicon,kirin-pcie.yaml    | 61 ++++++++++++++++++-
> > >  1 file changed, 60 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> > > index 90cab09e8d4b..bb0c3a081d68 100644
> > > --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> > > +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> > > @@ -24,11 +24,13 @@ properties:
> > >      contains:
> > >        enum:
> > >          - hisilicon,kirin960-pcie
> > > +        - hisilicon,kirin970-pcie
> > >
> > >    reg:
> > >      description: |
> > >        Should contain dbi, apb, config registers location and length.
> > > -      For HiKey960, it should also contain phy.
> > > +      For HiKey960, it should also contain phy. All other devices
> > > +      should use a separate phy driver.
> > >      minItems: 3
> > >      maxItems: 4
> > >
> > > @@ -47,6 +49,7 @@ examples:
> > >    - |
> > >      #include <dt-bindings/interrupt-controller/arm-gic.h>
> > >      #include <dt-bindings/clock/hi3660-clock.h>
> > > +    #include <dt-bindings/clock/hi3670-clock.h>
> > >
> > >      soc {
> > >        #address-cells = <2>;
> > > @@ -83,4 +86,60 @@ examples:
> > >          clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
> > >                        "pcie_apb_sys", "pcie_aclk";
> > >        };
> > > +
> > > +      pcie@f5000000 {
> > > +        compatible = "hisilicon,kirin970-pcie";
> > > +        reg = <0x0 0xf4000000 0x0 0x1000000>,
> > > +              <0x0 0xfc180000 0x0 0x1000>,
> > > +              <0x0 0xf5000000 0x0 0x2000>;
> > > +        reg-names = "dbi", "apb", "config";
> > > +        bus-range = <0x0  0x1>;
> > > +        msi-parent = <&its_pcie>;
> > > +        #address-cells = <3>;
> > > +        #size-cells = <2>;
> > > +        device_type = "pci";
> > > +        phys = <&pcie_phy>;
> > > +        ranges = <0x02000000 0x0 0x00000000
> > > +                  0x0 0xf6000000
> > > +                  0x0 0x02000000>;
> > > +        num-lanes = <1>;
> > > +        #interrupt-cells = <1>;
> > > +        interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
> > > +        interrupt-names = "msi";
> > > +        interrupt-map-mask = <0 0 0 7>;
> > > +        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> > > +                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> > > +                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> > > +                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
> > > +        pcie@4,0 { // Lane 4: M.2
> > > +          reg = <0 0 0 0 0>;
> > > +          compatible = "pciclass,0604";
> > > +          device_type = "pci";
> > > +          reset-gpios = <&gpio7 1 0>;
> > > +          clkreq-gpios = <&gpio27 3 0 >;  
> > 
> > Looking at the schematics some more, this is not right. CLKREQ# is an
> > input from the device, and they are not connected to any GPIO (just
> > pulled high) on hikey970. These GPIOs are simply clock enables and
> > very much specific to hikey. So I'd call this 'hisilicon,clken-gpios'
> > and you can just stick them in the host bridge node.
> > 
> 
> Ok. If I understood your review, the schema will then be:
> 
>       pcie@f4000000 {
>         compatible = "hisilicon,kirin970-pcie";
>         reg = <0x0 0xf4000000 0x0 0x1000000>,
>               <0x0 0xfc180000 0x0 0x1000>,
>               <0x0 0xf5000000 0x0 0x2000>;
>         reg-names = "dbi", "apb", "config";
>         bus-range = <0x0  0x1>;
>         msi-parent = <&its_pcie>;
>         #address-cells = <3>;
>         #size-cells = <2>;
>         device_type = "pci";
>         phys = <&pcie_phy>;
>         ranges = <0x02000000 0x0 0x00000000
>                   0x0 0xf6000000
>                   0x0 0x02000000>;
>         num-lanes = <1>;
>         #interrupt-cells = <1>;
>         interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
>         interrupt-names = "msi";
>         interrupt-map-mask = <0 0 0 7>;
>         interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
>                         <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
>                         <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
>                         <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
>         reset-gpios = <&gpio7 0 0>;
> 
>         pcie@0 { // Lane 0: upstream
>           reg = <0 0 0 0 0>;
>           compatible = "pciclass,0604";
>           device_type = "pci";
>           #address-cells = <3>;
>           #size-cells = <2>;
>           hisilicon,clken-gpios = <&gpio27 3 0 >, <&gpio17 0 0 >, <&gpio20 6 0 >;

Up one more level.

>           ranges;
> 
>           pcie@1,0 { // Lane 4: M.2
>             reg = <0x800 0 0 0 0>;
>             compatible = "pciclass,0604";
>             device_type = "pci";
>             reset-gpios = <&gpio3 1 0>;
>             #address-cells = <3>;
>             #size-cells = <2>;
>             ranges;
>           };
> 
>           pcie@5,0 { // Lane 5: Mini PCIe
>             reg = <0x2800 0 0 0 0>;
>             compatible = "pciclass,0604";
>             device_type = "pci";
>             reset-gpios = <&gpio27 4 0 >;
>             #address-cells = <3>;
>             #size-cells = <2>;
>             ranges;
>           };
> 
>           pcie@7,0 { // Lane 7: Ethernet

Port 7 is lane 6 and Port 9 is lane 7. So I think it should be 'Lane 6'. 

>             reg = <0x3800 0 0 0 0>;
>             compatible = "pciclass,0604";
>             device_type = "pci";
>             reset-gpios = <&gpio25 2 0 >;
>             #address-cells = <3>;
>             #size-cells = <2>;
>             ranges;
>           };
>         };
>       };
>     };
> 
> Right?
> 
> After updating the dt-schema from your git tree, the above doesn't 
> generate warnings anymore.
> 
> Thanks,
> Mauro
> 

Re: [PATCH 3/5] dt-bindings: PCI: kirin: Add support for Kirin970

[Mauro Carvalho Chehab]

Em Mon, 2 Aug 2021 16:50:53 -0600
Rob Herring <robh@kernel.org> escreveu:

> On Thu, Jul 29, 2021 at 09:03:37PM +0200, Mauro Carvalho Chehab wrote:
> > Em Thu, 29 Jul 2021 09:20:15 -0600
> > Rob Herring <robh@kernel.org> escreveu:
> >   

> > 
> > Ok. If I understood your review, the schema will then be:
> > 
> >       pcie@f4000000 {
> >         compatible = "hisilicon,kirin970-pcie";
> >         reg = <0x0 0xf4000000 0x0 0x1000000>,
> >               <0x0 0xfc180000 0x0 0x1000>,
> >               <0x0 0xf5000000 0x0 0x2000>;
> >         reg-names = "dbi", "apb", "config";
> >         bus-range = <0x0  0x1>;
> >         msi-parent = <&its_pcie>;
> >         #address-cells = <3>;
> >         #size-cells = <2>;
> >         device_type = "pci";
> >         phys = <&pcie_phy>;
> >         ranges = <0x02000000 0x0 0x00000000
> >                   0x0 0xf6000000
> >                   0x0 0x02000000>;
> >         num-lanes = <1>;
> >         #interrupt-cells = <1>;
> >         interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
> >         interrupt-names = "msi";
> >         interrupt-map-mask = <0 0 0 7>;
> >         interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> >                         <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> >                         <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> >                         <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
> >         reset-gpios = <&gpio7 0 0>;
> > 
> >         pcie@0 { // Lane 0: upstream
> >           reg = <0 0 0 0 0>;
> >           compatible = "pciclass,0604";
> >           device_type = "pci";
> >           #address-cells = <3>;
> >           #size-cells = <2>;
> >           hisilicon,clken-gpios = <&gpio27 3 0 >, <&gpio17 0 0 >, <&gpio20 6 0 >;  
> 
> Up one more level.

Yeah. This is at the upper level at the newer series:

	[PATCH v2 3/4] dt-bindings: PCI: kirin: Add support for Kirin970
	https://lore.kernel.org/lkml/93a42a6317eed3b0eb6a35b6d4c484e106cb2793.1627637448.git.mchehab+huawei@kernel.org/


> >           ranges;
> > 
> >           pcie@1,0 { // Lane 4: M.2
> >             reg = <0x800 0 0 0 0>;
> >             compatible = "pciclass,0604";
> >             device_type = "pci";
> >             reset-gpios = <&gpio3 1 0>;
> >             #address-cells = <3>;
> >             #size-cells = <2>;
> >             ranges;
> >           };
> > 
> >           pcie@5,0 { // Lane 5: Mini PCIe
> >             reg = <0x2800 0 0 0 0>;
> >             compatible = "pciclass,0604";
> >             device_type = "pci";
> >             reset-gpios = <&gpio27 4 0 >;
> >             #address-cells = <3>;
> >             #size-cells = <2>;
> >             ranges;
> >           };
> > 
> >           pcie@7,0 { // Lane 7: Ethernet  
> 
> Port 7 is lane 6 and Port 9 is lane 7. So I think it should be 'Lane 6'. 

True. I'll fix it on v3.

> 
> >             reg = <0x3800 0 0 0 0>;
> >             compatible = "pciclass,0604";
> >             device_type = "pci";
> >             reset-gpios = <&gpio25 2 0 >;
> >             #address-cells = <3>;
> >             #size-cells = <2>;
> >             ranges;
> >           };
> >         };
> >       };
> >     };
> > 
> > Right?
> > 
> > After updating the dt-schema from your git tree, the above doesn't 
> > generate warnings anymore.
> > 
> > Thanks,
> > Mauro
> >   

Thanks,
Mauro

[PATCH 4/5] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY

[Mauro Carvalho Chehab]

Document the bindings for HiKey 970 (hi3670) PCIe PHY
interface, supported via the pcie-kirin driver.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
 .../phy/hisilicon,phy-hi3670-pcie.yaml        | 86 +++++++++++++++++++
 1 file changed, 86 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml

diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
new file mode 100644
index 000000000000..1e0153e4f4a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Kirin970 PCIe PHY
+
+maintainers:
+  - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
+
+description: |+
+  Bindings for PCIe PHY on HiSilicon Kirin 970.
+
+properties:
+  compatible:
+    const: hisilicon,hi970-pcie-phy
+
+  "#phy-cells":
+    const: 0
+
+  reg:
+    maxItems: 1
+    description: PHY Control registers
+
+  phy-supply:
+    description: The PCIe PHY power supply
+
+  clocks:
+    items:
+      - description: PCIe PHY clock
+      - description: PCIe AUX clock
+      - description: PCIe APB PHY clock
+      - description: PCIe APB SYS clock
+      - description: PCIe ACLK clock
+
+  clock-names:
+    items:
+      - const: phy_ref
+      - const: aux
+      - const: apb_phy
+      - const: apb_sys
+      - const: aclk
+
+  clkreq-gpios:
+    description: Clock request GPIOs
+    maxItems: 3
+
+  hisilicon,eye-diagram-param:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: Eye diagram for phy.
+
+required:
+  - "#phy-cells"
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - hisilicon,eye-diagram-param
+  - phy-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/hi3670-clock.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+      pcie_phy: pcie-phy@fc000000 {
+        compatible = "hisilicon,hi970-pcie-phy";
+        reg = <0x0 0xfc000000 0x0 0x80000>;
+        #phy-cells = <0>;
+        phy-supply = <&ldo33>;
+        clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+                 <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+                 <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+                 <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+                 <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+        clock-names = "phy_ref", "aux",
+                      "apb_phy", "apb_sys", "aclk";
+        hisilicon,eye-diagram-param = <0xffffffff 0xffffffff
+                                       0xffffffff 0xffffffff 0xffffffff>;
+      };
+    };
-- 
2.31.1

[PATCH 4/5] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY

[Mauro Carvalho Chehab]

Document the bindings for HiKey 970 (hi3670) PCIe PHY
interface, supported via the pcie-kirin driver.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
 .../phy/hisilicon,phy-hi3670-pcie.yaml        | 86 +++++++++++++++++++
 1 file changed, 86 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml

diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
new file mode 100644
index 000000000000..1e0153e4f4a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Kirin970 PCIe PHY
+
+maintainers:
+  - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
+
+description: |+
+  Bindings for PCIe PHY on HiSilicon Kirin 970.
+
+properties:
+  compatible:
+    const: hisilicon,hi970-pcie-phy
+
+  "#phy-cells":
+    const: 0
+
+  reg:
+    maxItems: 1
+    description: PHY Control registers
+
+  phy-supply:
+    description: The PCIe PHY power supply
+
+  clocks:
+    items:
+      - description: PCIe PHY clock
+      - description: PCIe AUX clock
+      - description: PCIe APB PHY clock
+      - description: PCIe APB SYS clock
+      - description: PCIe ACLK clock
+
+  clock-names:
+    items:
+      - const: phy_ref
+      - const: aux
+      - const: apb_phy
+      - const: apb_sys
+      - const: aclk
+
+  clkreq-gpios:
+    description: Clock request GPIOs
+    maxItems: 3
+
+  hisilicon,eye-diagram-param:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: Eye diagram for phy.
+
+required:
+  - "#phy-cells"
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - hisilicon,eye-diagram-param
+  - phy-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/hi3670-clock.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+      pcie_phy: pcie-phy@fc000000 {
+        compatible = "hisilicon,hi970-pcie-phy";
+        reg = <0x0 0xfc000000 0x0 0x80000>;
+        #phy-cells = <0>;
+        phy-supply = <&ldo33>;
+        clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+                 <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+                 <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+                 <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+                 <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+        clock-names = "phy_ref", "aux",
+                      "apb_phy", "apb_sys", "aclk";
+        hisilicon,eye-diagram-param = <0xffffffff 0xffffffff
+                                       0xffffffff 0xffffffff 0xffffffff>;
+      };
+    };
-- 
2.31.1


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[PATCH 5/5] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware

[Mauro Carvalho Chehab]

From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Add DTS bindings for the HiKey 970 board's PCIe hardware.

Co-developed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
 arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 99 +++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 20698cfd0637..2cf19c8960f3 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -176,6 +176,12 @@ sctrl: sctrl@fff0a000 {
 			#clock-cells = <1>;
 		};
 
+		pmctrl: pmctrl@fff31000 {
+			compatible = "hisilicon,hi3670-pmctrl", "syscon";
+			reg = <0x0 0xfff31000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
 		iomcu: iomcu@ffd7e000 {
 			compatible = "hisilicon,hi3670-iomcu", "syscon";
 			reg = <0x0 0xffd7e000 0x0 0x1000>;
@@ -659,6 +665,99 @@ gpio28: gpio@fff1d000 {
 			clock-names = "apb_pclk";
 		};
 
+		its_pcie: interrupt-controller@f4000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0xf5100000 0x0 0x100000>;
+		};
+
+		pcie_phy: pcie-phy@fc000000 {
+			compatible = "hisilicon,hi970-pcie-phy";
+			reg = <0x0 0xfc000000 0x0 0x80000>;
+
+			phy-supply = <&ldo33>;
+
+			clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+				 <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+				 <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+				 <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+				 <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+			clock-names = "phy_ref", "aux",
+				      "apb_phy", "apb_sys",
+				      "aclk";
+
+			/* vboost iboost pre post main */
+			hisilicon,eye-diagram-param = <0xffffffff 0xffffffff
+						       0xffffffff 0xffffffff
+						       0xffffffff>;
+
+			#phy-cells = <0>;
+		};
+
+		pcie@f4000000 {
+			compatible = "hisilicon,kirin970-pcie";
+			reg = <0x0 0xf4000000 0x0 0x1000000>,
+			      <0x0 0xfc180000 0x0 0x1000>,
+			      <0x0 0xf5000000 0x0 0x2000>;
+			reg-names = "dbi", "apb", "config";
+			bus-range = <0x0  0x1>;
+			msi-parent = <&its_pcie>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			phys = <&pcie_phy>;
+			ranges = <0x02000000 0x0 0x00000000
+				  0x0 0xf6000000
+				  0x0 0x02000000>;
+			num-lanes = <1>;
+			#interrupt-cells = <1>;
+			interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0x0 0 0 1
+					 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0 0 0 2
+					 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0 0 0 3
+					 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0 0 0 4
+					 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+			reset-gpios = <&gpio7 0 0 >;
+
+			pcie@4,0 { // Lane 4: M.2
+				reg = <0 0 0 0 0>;
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reset-gpios = <&gpio7 1 0>;
+				clkreq-gpios = <&gpio27 3 0 >;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+
+			pcie@5,0 { // Lane 5: Mini PCIe
+				reg = <0 0 0 0 0>;
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reset-gpios = <&gpio7 2 0>;
+				clkreq-gpios = <&gpio17 0 0 >;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+
+			pcie@7,0 { // Lane 7: Ethernet
+				reg = <0 0 0 0 0>;
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reset-gpios = <&gpio7 3 0>;
+				clkreq-gpios = <&gpio20 0 0 >;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+		};
+
 		/* UFS */
 		ufs: ufs@ff3c0000 {
 			compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
-- 
2.31.1

[PATCH 5/5] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware

[Mauro Carvalho Chehab]

From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Add DTS bindings for the HiKey 970 board's PCIe hardware.

Co-developed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
 arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 99 +++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 20698cfd0637..2cf19c8960f3 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -176,6 +176,12 @@ sctrl: sctrl@fff0a000 {
 			#clock-cells = <1>;
 		};
 
+		pmctrl: pmctrl@fff31000 {
+			compatible = "hisilicon,hi3670-pmctrl", "syscon";
+			reg = <0x0 0xfff31000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
 		iomcu: iomcu@ffd7e000 {
 			compatible = "hisilicon,hi3670-iomcu", "syscon";
 			reg = <0x0 0xffd7e000 0x0 0x1000>;
@@ -659,6 +665,99 @@ gpio28: gpio@fff1d000 {
 			clock-names = "apb_pclk";
 		};
 
+		its_pcie: interrupt-controller@f4000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0xf5100000 0x0 0x100000>;
+		};
+
+		pcie_phy: pcie-phy@fc000000 {
+			compatible = "hisilicon,hi970-pcie-phy";
+			reg = <0x0 0xfc000000 0x0 0x80000>;
+
+			phy-supply = <&ldo33>;
+
+			clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+				 <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+				 <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+				 <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+				 <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+			clock-names = "phy_ref", "aux",
+				      "apb_phy", "apb_sys",
+				      "aclk";
+
+			/* vboost iboost pre post main */
+			hisilicon,eye-diagram-param = <0xffffffff 0xffffffff
+						       0xffffffff 0xffffffff
+						       0xffffffff>;
+
+			#phy-cells = <0>;
+		};
+
+		pcie@f4000000 {
+			compatible = "hisilicon,kirin970-pcie";
+			reg = <0x0 0xf4000000 0x0 0x1000000>,
+			      <0x0 0xfc180000 0x0 0x1000>,
+			      <0x0 0xf5000000 0x0 0x2000>;
+			reg-names = "dbi", "apb", "config";
+			bus-range = <0x0  0x1>;
+			msi-parent = <&its_pcie>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			phys = <&pcie_phy>;
+			ranges = <0x02000000 0x0 0x00000000
+				  0x0 0xf6000000
+				  0x0 0x02000000>;
+			num-lanes = <1>;
+			#interrupt-cells = <1>;
+			interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0x0 0 0 1
+					 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0 0 0 2
+					 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0 0 0 3
+					 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0 0 0 4
+					 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+			reset-gpios = <&gpio7 0 0 >;
+
+			pcie@4,0 { // Lane 4: M.2
+				reg = <0 0 0 0 0>;
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reset-gpios = <&gpio7 1 0>;
+				clkreq-gpios = <&gpio27 3 0 >;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+
+			pcie@5,0 { // Lane 5: Mini PCIe
+				reg = <0 0 0 0 0>;
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reset-gpios = <&gpio7 2 0>;
+				clkreq-gpios = <&gpio17 0 0 >;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+
+			pcie@7,0 { // Lane 7: Ethernet
+				reg = <0 0 0 0 0>;
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				reset-gpios = <&gpio7 3 0>;
+				clkreq-gpios = <&gpio20 0 0 >;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+		};
+
 		/* UFS */
 		ufs: ufs@ff3c0000 {
 			compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
-- 
2.31.1


_______________________________________________
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Re: [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work

[Rob Herring]

On Thu, Jul 29, 2021 at 5:56 AM Mauro Carvalho Chehab
<mchehab+huawei@kernel.org> wrote:
>
> Hi Rob,
>
> After our discussions, I'm opting to submit first the DT bindings for the
> Kirin 970 PCIe support.
>
> Patch 1 is there just because patch 2 needs. You already acked on it.
>
> Patch 5 is also there just as an example of the entire stuff added to
> the DTS file.
>
> The core of this series are patches 2 to 4. They contain the conversion
> of the kirin-pcie.txt file to the DT schema, and adds the needed
> bindings.
>
> Currently, it generates some warnings:
>
>    Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: pcie@4,0:compatible: None of ['pciclass,0604'] are valid under the given schema
>         From schema: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml

This should be fixed now in dtschema master.

>   Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@4,0: reset-gpios: [[4294967295, 1, 0]] is too short

Your proposed change to pci-bus.yaml is wrong. It's requiring 4
entries. You need 'minItems: 1'.

Rob

Re: [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work

[Rob Herring]

On Thu, Jul 29, 2021 at 5:56 AM Mauro Carvalho Chehab
<mchehab+huawei@kernel.org> wrote:
>
> Hi Rob,
>
> After our discussions, I'm opting to submit first the DT bindings for the
> Kirin 970 PCIe support.
>
> Patch 1 is there just because patch 2 needs. You already acked on it.
>
> Patch 5 is also there just as an example of the entire stuff added to
> the DTS file.
>
> The core of this series are patches 2 to 4. They contain the conversion
> of the kirin-pcie.txt file to the DT schema, and adds the needed
> bindings.
>
> Currently, it generates some warnings:
>
>    Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: pcie@4,0:compatible: None of ['pciclass,0604'] are valid under the given schema
>         From schema: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml

This should be fixed now in dtschema master.

>   Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@4,0: reset-gpios: [[4294967295, 1, 0]] is too short

Your proposed change to pci-bus.yaml is wrong. It's requiring 4
entries. You need 'minItems: 1'.

Rob

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Re: [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work

[Rob Herring]

On Thu, Jul 29, 2021 at 5:56 AM Mauro Carvalho Chehab
<mchehab+huawei@kernel.org> wrote:
>
> Hi Rob,
>
> After our discussions, I'm opting to submit first the DT bindings for the
> Kirin 970 PCIe support.
>
> Patch 1 is there just because patch 2 needs. You already acked on it.
>
> Patch 5 is also there just as an example of the entire stuff added to
> the DTS file.
>
> The core of this series are patches 2 to 4. They contain the conversion
> of the kirin-pcie.txt file to the DT schema, and adds the needed
> bindings.
>
> Currently, it generates some warnings:
>
>    Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: pcie@4,0:compatible: None of ['pciclass,0604'] are valid under the given schema
>         From schema: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml

This should be fixed now in dtschema master.

>   Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@4,0: reset-gpios: [[4294967295, 1, 0]] is too short

Your proposed change to pci-bus.yaml is wrong. It's requiring 4
entries. You need 'minItems: 1'.

Rob

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