From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 936E9C38142 for ; Fri, 27 Jan 2023 13:41:47 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2F3EF85749; Fri, 27 Jan 2023 14:41:05 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=collabora.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=collabora.com header.i=@collabora.com header.b="Q2Lm6Q8w"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 338B185509; Fri, 27 Jan 2023 14:33:30 +0100 (CET) Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6F07884954 for ; Fri, 27 Jan 2023 14:33:27 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=collabora.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=eugen.hristev@collabora.com Received: from [192.168.0.125] (unknown [82.76.24.202]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: ehristev) by madras.collabora.co.uk (Postfix) with ESMTPSA id 72F2C6602E8F; Fri, 27 Jan 2023 13:33:26 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674826406; bh=hRkLgE42mAT8Onf6g0WY8KwcsME/aigoA/ek93PEGgU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Q2Lm6Q8wArHXCF37EcYckdKg4R/HEtkrCgscJ/Vwq/41x4+6gZirAPrkAzFQvCQ0y IqqgNbbtL0NpVyfmpERYT107a/O/HRia/HbrZgQQZF+nJgrVDfyEbrBHxDkrt4FfIz eYUPxIPKxxTxusOnCdqsew1QGx5i3cczhRFUYrG+6ytMm1LYtq5wavspM5M0erJrjj U9NLvHB1ElgGQup5Uwy2a1tgFJL2T/nML3Jz1Ow3DUYfOdYw06d26DJrKYqm/iNgA9 pvf5qFi6qpNzTMrbItNx2imLBmCoBOSdvmM1noDIxACc7YDtddvm8CET8S8VCvgTh6 Jk3rryehyiuuQ== Message-ID: Date: Fri, 27 Jan 2023 15:33:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [RFC PATCH 15/16] ARM: dts: rockchip: Add rk3588-u-boot.dtsi Content-Language: en-US To: Jagan Teki , Kever Yang , Simon Glass , Philipp Tomsich , fatorangecat@189.cn Cc: u-boot@lists.denx.de References: <20230125222741.303259-1-jagan@edgeble.ai> <20230125222741.303259-16-jagan@edgeble.ai> From: Eugen Hristev In-Reply-To: <20230125222741.303259-16-jagan@edgeble.ai> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Mailman-Approved-At: Fri, 27 Jan 2023 14:40:58 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hello Jagan, On 1/26/23 00:27, Jagan Teki wrote: > Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties > for Rockchip RK3588 SoC. It appears this file/commit does more than just adding u-boot,* properties > > Signed-off-by: Jagan Teki > --- > arch/arm/dts/rk3588-u-boot.dtsi | 101 ++++++++++++++++++++++++++++++++ > 1 file changed, 101 insertions(+) > create mode 100644 arch/arm/dts/rk3588-u-boot.dtsi > > diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi > new file mode 100644 > index 0000000000..b5cc4dcc60 > --- /dev/null > +++ b/arch/arm/dts/rk3588-u-boot.dtsi > @@ -0,0 +1,101 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. > + */ > + > +#include "rockchip-u-boot.dtsi" > +#include > + > +/ { > + dmc { > + compatible = "rockchip,rk3588-dmc"; > + u-boot,dm-pre-reloc; > + status = "okay"; > + }; > + > + pmu1_grf: syscon@fd58a000 { > + u-boot,dm-pre-reloc; > + compatible = "rockchip,rk3588-pmu1-grf", "syscon"; > + reg = <0x0 0xfd58a000 0x0 0x2000>; > + }; > + > + sdmmc: mmc@fe2c0000 { Just for my understanding, why are you adding here a new node sdmmc, and have it disabled, while you have another node called 'sdhci' which you enable further down in the file ? What is the purpose of this sdmmc node? and defining it here. Eugen > + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; > + reg = <0x0 0xfe2c0000 0x0 0x4000>; > + interrupts = ; > + clocks = <&cru SCLK_SDMMC_SAMPLE>, <&cru SCLK_SDMMC_DRV>, > + <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>; > + clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; > + fifo-depth = <0x100>; > + max-frequency = <200000000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; > + status = "disabled"; > + }; > +}; > + > +&gpio0 { > + u-boot,dm-spl; > + status = "okay"; > +}; > + > +&gpio1 { > + u-boot,dm-pre-reloc; > + status = "okay"; > +}; > + > +&gpio2 { > + u-boot,dm-pre-reloc; > + status = "okay"; > +}; > + > +&gpio3 { > + u-boot,dm-pre-reloc; > + status = "okay"; > +}; > + > +&gpio4 { > + u-boot,dm-pre-reloc; > + status = "okay"; > +}; > + > +&scmi { > + u-boot,dm-spl; > +}; > + > +&scmi_clk { > + u-boot,dm-spl; > +}; > + > +&xin24m { > + u-boot,dm-pre-reloc; > + status = "okay"; > +}; > + > +&cru { > + u-boot,dm-spl; > + status = "okay"; > +}; > + > +&sys_grf { > + u-boot,dm-spl; > + status = "okay"; > +}; > + > +&uart2 { > + clock-frequency = <24000000>; > + u-boot,dm-spl; > + status = "okay"; > +}; > + > +&sdhci { > + bus-width = <8>; > + u-boot,dm-spl; > + mmc-hs200-1_8v; > + non-removable; > + status = "okay"; > +}; > + > +&ioc { > + u-boot,dm-spl; > +};