From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65E54C433EF for ; Fri, 29 Oct 2021 08:49:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 302F161157 for ; Fri, 29 Oct 2021 08:49:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 302F161157 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=cqplus1.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=22eWFWmMlKi2vXX7s+/axugEt69c1LbwaxR8AeIBSp0=; b=FYYueurhCvBNjg zfkkc8lOQN7KkC4D7Wy77dBjXUarYH8Rem0fmM4u8Dd9vYRrU2W92yHnduIwQPO6YbaqPR0TCKUWI QcV5Q7qMUHO1SVFzBYX44hfYwV4qxc1IZMf3Ro4RZ+5dDfM8TH+jwKOYBMzpjxyI4IHqFqCJ5qjnv KqK93g3FmUib+dmVGHTBYE0DIl2E1QXi5SxodoBHknSlb8RqJEULNPvuu4bok0wZdUIquxlDH7PYg Fn4J7ML9wwH5CjzrCedQDvtIdLRZNWhvFK4aqSUq2NJmq+DAc2uB+hxrpLBybovs+270LNchift01 cZRI2FiI6z5oFdi/q4Lw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mgNYa-00ALQV-Is; Fri, 29 Oct 2021 08:48:12 +0000 Received: from [113.204.237.245] (helo=test.cqplus1.com) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mgNX6-00AKs9-5Y for linux-arm-kernel@lists.infradead.org; Fri, 29 Oct 2021 08:46:43 +0000 X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by cqmailgates with MailGates ESMTP Server V5.0(10981:0:AUTH_RELAY) (envelope-from ); Fri, 29 Oct 2021 16:46:00 +0800 (CST) From: Qin Jian To: robh+dt@kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, broonie@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, wells.lu@sunplus.com, Qin Jian Subject: [PATCH v2 4/8] reset: Add Sunplus SP7021 reset driver Date: Fri, 29 Oct 2021 16:44:30 +0800 Message-Id: X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211029_014640_651202_A1251204 X-CRM114-Status: GOOD ( 23.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add reset driver for Sunplus SP7021 SoC. Signed-off-by: Qin Jian --- MAINTAINERS | 1 + drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-sunplus.c | 159 ++++++++++++++++++++++++++++++++++ 4 files changed, 170 insertions(+) create mode 100644 drivers/reset/reset-sunplus.c diff --git a/MAINTAINERS b/MAINTAINERS index 652f42cab..6caffd6d0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2662,6 +2662,7 @@ S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: drivers/reset/reset-sunplus.c F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index be799a5ab..1aec3c8af 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -249,6 +249,15 @@ config RESET_TI_SYSCON you wish to use the reset framework for such memory-mapped devices, say Y here. Otherwise, say N. +config RESET_SUNPLUS + bool "Sunplus SoCs Reset Driver" + default ARCH_PENTAGRAM + help + This enables the reset driver support for Sunplus SP7021 SoC family. + Say Y if you want to control reset signals by the reset controller. + Otherwise, say N. + This driver is selected automatically by platform config. + config RESET_UNIPHIER tristate "Reset controller driver for UniPhier SoCs" depends on ARCH_UNIPHIER || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 21d46d886..f03403e97 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o +obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o diff --git a/drivers/reset/reset-sunplus.c b/drivers/reset/reset-sunplus.c new file mode 100644 index 000000000..696efd75e --- /dev/null +++ b/drivers/reset/reset-sunplus.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * SP7021 reset driver + * + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SOC_SP7021) +#include +#elif defined(CONFIG_SOC_Q645) +#include +#endif + +#define BITASSERT(id, val) ((1 << (16 + id)) | (val << id)) + + +struct sp_reset_data { + struct reset_controller_dev rcdev; + void __iomem *membase; +} sp_reset; + + +static inline struct sp_reset_data * +to_sp_reset_data(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct sp_reset_data, rcdev); +} + +static int sp_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct sp_reset_data *data = to_sp_reset_data(rcdev); + int reg_width = sizeof(u32)/2; + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); + void __iomem *addr; + + addr = data->membase + (bank * 4); + + if (assert) + writel(BITASSERT(offset, 1), addr); + else + writel(BITASSERT(offset, 0), addr); + + return 0; +} + +static int sp_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return sp_reset_update(rcdev, id, true); +} + + +static int sp_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return sp_reset_update(rcdev, id, false); +} + +static int sp_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct sp_reset_data *data = to_sp_reset_data(rcdev); + int reg_width = sizeof(u32)/2; + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); + u32 reg; + + reg = readl(data->membase + (bank * 4)); + + return !!(reg & BIT(offset)); +} + +static int sp_restart(struct notifier_block *this, unsigned long mode, + void *cmd) +{ + sp_reset_assert(&sp_reset.rcdev, RST_SYSTEM); + sp_reset_deassert(&sp_reset.rcdev, RST_SYSTEM); + + return NOTIFY_DONE; +} + +static struct notifier_block sp_restart_nb = { + .notifier_call = sp_restart, + .priority = 192, +}; + +static const struct reset_control_ops sp_reset_ops = { + .assert = sp_reset_assert, + .deassert = sp_reset_deassert, + .status = sp_reset_status, +}; + +static const struct of_device_id sp_reset_dt_ids[] = { + { .compatible = "sunplus,sp7021-reset", }, + { .compatible = "sunplus,q645-reset", }, + { /* sentinel */ }, +}; + +static int sp_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sp_reset_data *data = &sp_reset; + void __iomem *membase; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + membase = devm_ioremap(dev, res->start, resource_size(res)); + if (IS_ERR(membase)) + return PTR_ERR(membase); + + data->membase = membase; + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = RST_MAX; + data->rcdev.ops = &sp_reset_ops; + data->rcdev.of_node = dev->of_node; + register_restart_handler(&sp_restart_nb); + + return devm_reset_controller_register(dev, &data->rcdev); +} + +static struct platform_driver sp_reset_driver = { + .probe = sp_reset_probe, + .driver = { + .name = "sunplus-reset", + .of_match_table = sp_reset_dt_ids, + }, +}; + +static int __init sp_reset_init(void) +{ + return platform_driver_register(&sp_reset_driver); +} +arch_initcall(sp_reset_init); + +MODULE_AUTHOR("Edwin Chiu "); +MODULE_DESCRIPTION("Sunplus Reset Driver"); +MODULE_LICENSE("GPL"); -- 2.33.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6BF6C433EF for ; Fri, 29 Oct 2021 09:11:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ACA77610CB for ; Fri, 29 Oct 2021 09:11:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231641AbhJ2JN1 (ORCPT ); Fri, 29 Oct 2021 05:13:27 -0400 Received: from [113.204.237.245] ([113.204.237.245]:55524 "EHLO test.cqplus1.com" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231436AbhJ2JND (ORCPT ); Fri, 29 Oct 2021 05:13:03 -0400 X-MailGates: (compute_score:DELIVER,40,3) Received: from 172.28.114.216 by cqmailgates with MailGates ESMTP Server V5.0(10981:0:AUTH_RELAY) (envelope-from ); Fri, 29 Oct 2021 16:46:00 +0800 (CST) From: Qin Jian To: robh+dt@kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, broonie@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, wells.lu@sunplus.com, Qin Jian Subject: [PATCH v2 4/8] reset: Add Sunplus SP7021 reset driver Date: Fri, 29 Oct 2021 16:44:30 +0800 Message-Id: X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add reset driver for Sunplus SP7021 SoC. Signed-off-by: Qin Jian --- MAINTAINERS | 1 + drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-sunplus.c | 159 ++++++++++++++++++++++++++++++++++ 4 files changed, 170 insertions(+) create mode 100644 drivers/reset/reset-sunplus.c diff --git a/MAINTAINERS b/MAINTAINERS index 652f42cab..6caffd6d0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2662,6 +2662,7 @@ S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: drivers/reset/reset-sunplus.c F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index be799a5ab..1aec3c8af 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -249,6 +249,15 @@ config RESET_TI_SYSCON you wish to use the reset framework for such memory-mapped devices, say Y here. Otherwise, say N. +config RESET_SUNPLUS + bool "Sunplus SoCs Reset Driver" + default ARCH_PENTAGRAM + help + This enables the reset driver support for Sunplus SP7021 SoC family. + Say Y if you want to control reset signals by the reset controller. + Otherwise, say N. + This driver is selected automatically by platform config. + config RESET_UNIPHIER tristate "Reset controller driver for UniPhier SoCs" depends on ARCH_UNIPHIER || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 21d46d886..f03403e97 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o +obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o diff --git a/drivers/reset/reset-sunplus.c b/drivers/reset/reset-sunplus.c new file mode 100644 index 000000000..696efd75e --- /dev/null +++ b/drivers/reset/reset-sunplus.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * SP7021 reset driver + * + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SOC_SP7021) +#include +#elif defined(CONFIG_SOC_Q645) +#include +#endif + +#define BITASSERT(id, val) ((1 << (16 + id)) | (val << id)) + + +struct sp_reset_data { + struct reset_controller_dev rcdev; + void __iomem *membase; +} sp_reset; + + +static inline struct sp_reset_data * +to_sp_reset_data(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct sp_reset_data, rcdev); +} + +static int sp_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct sp_reset_data *data = to_sp_reset_data(rcdev); + int reg_width = sizeof(u32)/2; + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); + void __iomem *addr; + + addr = data->membase + (bank * 4); + + if (assert) + writel(BITASSERT(offset, 1), addr); + else + writel(BITASSERT(offset, 0), addr); + + return 0; +} + +static int sp_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return sp_reset_update(rcdev, id, true); +} + + +static int sp_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return sp_reset_update(rcdev, id, false); +} + +static int sp_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct sp_reset_data *data = to_sp_reset_data(rcdev); + int reg_width = sizeof(u32)/2; + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); + u32 reg; + + reg = readl(data->membase + (bank * 4)); + + return !!(reg & BIT(offset)); +} + +static int sp_restart(struct notifier_block *this, unsigned long mode, + void *cmd) +{ + sp_reset_assert(&sp_reset.rcdev, RST_SYSTEM); + sp_reset_deassert(&sp_reset.rcdev, RST_SYSTEM); + + return NOTIFY_DONE; +} + +static struct notifier_block sp_restart_nb = { + .notifier_call = sp_restart, + .priority = 192, +}; + +static const struct reset_control_ops sp_reset_ops = { + .assert = sp_reset_assert, + .deassert = sp_reset_deassert, + .status = sp_reset_status, +}; + +static const struct of_device_id sp_reset_dt_ids[] = { + { .compatible = "sunplus,sp7021-reset", }, + { .compatible = "sunplus,q645-reset", }, + { /* sentinel */ }, +}; + +static int sp_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sp_reset_data *data = &sp_reset; + void __iomem *membase; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + membase = devm_ioremap(dev, res->start, resource_size(res)); + if (IS_ERR(membase)) + return PTR_ERR(membase); + + data->membase = membase; + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = RST_MAX; + data->rcdev.ops = &sp_reset_ops; + data->rcdev.of_node = dev->of_node; + register_restart_handler(&sp_restart_nb); + + return devm_reset_controller_register(dev, &data->rcdev); +} + +static struct platform_driver sp_reset_driver = { + .probe = sp_reset_probe, + .driver = { + .name = "sunplus-reset", + .of_match_table = sp_reset_dt_ids, + }, +}; + +static int __init sp_reset_init(void) +{ + return platform_driver_register(&sp_reset_driver); +} +arch_initcall(sp_reset_init); + +MODULE_AUTHOR("Edwin Chiu "); +MODULE_DESCRIPTION("Sunplus Reset Driver"); +MODULE_LICENSE("GPL"); -- 2.33.1