From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87C44C433F5 for ; Wed, 4 May 2022 08:06:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346021AbiEDIJu (ORCPT ); Wed, 4 May 2022 04:09:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238588AbiEDIJp (ORCPT ); Wed, 4 May 2022 04:09:45 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49591220DC; Wed, 4 May 2022 01:06:04 -0700 (PDT) X-UUID: cdfc2389b2034d31a6b07f80195c7111-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:17060d19-c653-499a-879c-289a6448ce38,OB:10,L OB:10,IP:0,URL:8,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,A CTION:release,TS:53 X-CID-INFO: VERSION:1.1.4,REQID:17060d19-c653-499a-879c-289a6448ce38,OB:10,LOB :10,IP:0,URL:8,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:53 X-CID-META: VersionHash:faefae9,CLOUDID:1d2ea92f-6199-437e-8ab4-9920b4bc5b76,C OID:a9dbf60cbf27,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: cdfc2389b2034d31a6b07f80195c7111-20220504 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1990241526; Wed, 04 May 2022 16:05:59 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 4 May 2022 16:05:58 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 16:05:58 +0800 Message-ID: Subject: Re: [PATCH v5 1/4] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml From: Rex-BC Chen To: Rob Herring CC: , , , , , , , , , , , , Date: Wed, 4 May 2022 16:05:58 +0800 In-Reply-To: References: <20220428133753.8348-1-rex-bc.chen@mediatek.com> <20220428133753.8348-2-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2022-05-03 at 13:01 -0500, Rob Herring wrote: > On Thu, Apr 28, 2022 at 09:37:50PM +0800, Rex-BC Chen wrote: > > From: Xinlei Lee > > > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > > > Signed-off-by: Xinlei Lee > > Signed-off-by: Rex-BC Chen > > --- > > .../display/mediatek/mediatek,dsi.txt | 62 --------- > > .../display/mediatek/mediatek,dsi.yaml | 122 > > ++++++++++++++++++ > > 2 files changed, 122 insertions(+), 62 deletions(-) > > delete mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > > l > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > deleted file mode 100644 > > index 36b01458f45c..000000000000 > > --- > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > +++ /dev/null > > @@ -1,62 +0,0 @@ > > -Mediatek DSI Device > > -=================== > > - > > -The Mediatek DSI function block is a sink of the display subsystem > > and can > > -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > > for dual- > > -channel output. > > - > > -Required properties: > > -- compatible: "mediatek,-dsi" > > -- the supported chips are mt2701, mt7623, mt8167, mt8173 and > > mt8183. > > -- reg: Physical base address and length of the controller's > > registers > > -- interrupts: The interrupt signal from the function block. > > -- clocks: device clocks > > - See Documentation/devicetree/bindings/clock/clock-bindings.txt > > for details. > > -- clock-names: must contain "engine", "digital", and "hs" > > -- phys: phandle link to the MIPI D-PHY controller. > > -- phy-names: must contain "dphy" > > -- port: Output port node with endpoint definitions as described in > > - Documentation/devicetree/bindings/graph.txt. This port should be > > connected > > - to the input port of an attached DSI panel or DSI-to-eDP encoder > > chip. > > - > > -Optional properties: > > -- resets: list of phandle + reset specifier pair, as described in > > [1]. > > - > > -[1] Documentation/devicetree/bindings/reset/reset.txt > > - > > -MIPI TX Configuration Module > > -============================ > > - > > -See phy/mediatek,dsi-phy.yaml > > - > > -Example: > > - > > -mipi_tx0: mipi-dphy@10215000 { > > - compatible = "mediatek,mt8173-mipi-tx"; > > - reg = <0 0x10215000 0 0x1000>; > > - clocks = <&clk26m>; > > - clock-output-names = "mipi_tx0_pll"; > > - #clock-cells = <0>; > > - #phy-cells = <0>; > > - drive-strength-microamp = <4600>; > > - nvmem-cells= <&mipi_tx_calibration>; > > - nvmem-cell-names = "calibration-data"; > > -}; > > - > > -dsi0: dsi@1401b000 { > > - compatible = "mediatek,mt8173-dsi"; > > - reg = <0 0x1401b000 0 0x1000>; > > - interrupts = ; > > - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, > > - <&mipi_tx0>; > > - clock-names = "engine", "digital", "hs"; > > - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; > > - phys = <&mipi_tx0>; > > - phy-names = "dphy"; > > - > > - port { > > - dsi0_out: endpoint { > > - remote-endpoint = <&panel_in>; > > - }; > > - }; > > -}; > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > new file mode 100644 > > index 000000000000..2ca9229ef69e > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > @@ -0,0 +1,122 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml*__;Iw!!CTRNKA9wMg0ARbw!w60__6oza0dggkQt6zWF-ZnYUKobclO7i3x9kiS1CETGQlCVcifs6UfqytY8vunKIJlM$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!w60__6oza0dggkQt6zWF-ZnYUKobclO7i3x9kiS1CETGQlCVcifs6UfqytY8vns85I56$ > > > > + > > +title: MediaTek DSI Controller Device Tree Bindings > > + > > +maintainers: > > + - Chun-Kuang Hu > > + - Philipp Zabel > > + - Jitao Shi > > + - Xinlei Lee > > + > > +description: | > > + The MediaTek DSI function block is a sink of the display > > subsystem and can > > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > > for dual- > > + channel output. > > + > > +allOf: > > + - $ref: /schemas/display/dsi-controller.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - mediatek,mt2701-dsi > > + - mediatek,mt7623-dsi > > + - mediatek,mt8167-dsi > > + - mediatek,mt8173-dsi > > + - mediatek,mt8183-dsi > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Engine Clock > > + - description: Digital Clock > > + - description: HS Clock > > + > > + clock-names: > > + items: > > + - const: engine > > + - const: digital > > + - const: hs > > + > > + resets: > > + maxItems: 1 > > + > > + phys: > > + maxItems: 1 > > + > > + phy-names: > > + items: > > + - const: dphy > > + > > + port: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: > > + Output port node. This port should be connected to the input > > + port of an attached DSI panel or DSI-to-eDP encoder chip. > > + > > + > > 1 blank line Hello Rob, Thanks for your review. ok. I will do this in next version. > > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > Did you try adding these? Because they are wrong and will contradict > dsi-controller.yaml. > We have some mistake. There will not be any sub node for mediatek dsi, so I will drop this modification in next version. BRs, Rex > Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1B69C433F5 for ; Wed, 4 May 2022 08:06:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3923210F4D9; Wed, 4 May 2022 08:06:06 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA02410F4D9 for ; Wed, 4 May 2022 08:06:04 +0000 (UTC) X-UUID: cdfc2389b2034d31a6b07f80195c7111-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:17060d19-c653-499a-879c-289a6448ce38, OB:10, L OB:10,IP:0,URL:8,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,A CTION:release,TS:53 X-CID-INFO: VERSION:1.1.4, REQID:17060d19-c653-499a-879c-289a6448ce38, OB:10, LOB :10,IP:0,URL:8,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:53 X-CID-META: VersionHash:faefae9, CLOUDID:1d2ea92f-6199-437e-8ab4-9920b4bc5b76, C OID:a9dbf60cbf27,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: cdfc2389b2034d31a6b07f80195c7111-20220504 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1990241526; Wed, 04 May 2022 16:05:59 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 4 May 2022 16:05:58 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 16:05:58 +0800 Message-ID: Subject: Re: [PATCH v5 1/4] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml From: Rex-BC Chen To: Rob Herring Date: Wed, 4 May 2022 16:05:58 +0800 In-Reply-To: References: <20220428133753.8348-1-rex-bc.chen@mediatek.com> <20220428133753.8348-2-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chunkuang.hu@kernel.org, jitao.shi@mediatek.com, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, airlied@linux.ie, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org, xinlei.lee@mediatek.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, 2022-05-03 at 13:01 -0500, Rob Herring wrote: > On Thu, Apr 28, 2022 at 09:37:50PM +0800, Rex-BC Chen wrote: > > From: Xinlei Lee > > > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > > > Signed-off-by: Xinlei Lee > > Signed-off-by: Rex-BC Chen > > --- > > .../display/mediatek/mediatek,dsi.txt | 62 --------- > > .../display/mediatek/mediatek,dsi.yaml | 122 > > ++++++++++++++++++ > > 2 files changed, 122 insertions(+), 62 deletions(-) > > delete mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > > l > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > deleted file mode 100644 > > index 36b01458f45c..000000000000 > > --- > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > +++ /dev/null > > @@ -1,62 +0,0 @@ > > -Mediatek DSI Device > > -=================== > > - > > -The Mediatek DSI function block is a sink of the display subsystem > > and can > > -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > > for dual- > > -channel output. > > - > > -Required properties: > > -- compatible: "mediatek,-dsi" > > -- the supported chips are mt2701, mt7623, mt8167, mt8173 and > > mt8183. > > -- reg: Physical base address and length of the controller's > > registers > > -- interrupts: The interrupt signal from the function block. > > -- clocks: device clocks > > - See Documentation/devicetree/bindings/clock/clock-bindings.txt > > for details. > > -- clock-names: must contain "engine", "digital", and "hs" > > -- phys: phandle link to the MIPI D-PHY controller. > > -- phy-names: must contain "dphy" > > -- port: Output port node with endpoint definitions as described in > > - Documentation/devicetree/bindings/graph.txt. This port should be > > connected > > - to the input port of an attached DSI panel or DSI-to-eDP encoder > > chip. > > - > > -Optional properties: > > -- resets: list of phandle + reset specifier pair, as described in > > [1]. > > - > > -[1] Documentation/devicetree/bindings/reset/reset.txt > > - > > -MIPI TX Configuration Module > > -============================ > > - > > -See phy/mediatek,dsi-phy.yaml > > - > > -Example: > > - > > -mipi_tx0: mipi-dphy@10215000 { > > - compatible = "mediatek,mt8173-mipi-tx"; > > - reg = <0 0x10215000 0 0x1000>; > > - clocks = <&clk26m>; > > - clock-output-names = "mipi_tx0_pll"; > > - #clock-cells = <0>; > > - #phy-cells = <0>; > > - drive-strength-microamp = <4600>; > > - nvmem-cells= <&mipi_tx_calibration>; > > - nvmem-cell-names = "calibration-data"; > > -}; > > - > > -dsi0: dsi@1401b000 { > > - compatible = "mediatek,mt8173-dsi"; > > - reg = <0 0x1401b000 0 0x1000>; > > - interrupts = ; > > - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, > > - <&mipi_tx0>; > > - clock-names = "engine", "digital", "hs"; > > - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; > > - phys = <&mipi_tx0>; > > - phy-names = "dphy"; > > - > > - port { > > - dsi0_out: endpoint { > > - remote-endpoint = <&panel_in>; > > - }; > > - }; > > -}; > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > new file mode 100644 > > index 000000000000..2ca9229ef69e > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > @@ -0,0 +1,122 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml*__;Iw!!CTRNKA9wMg0ARbw!w60__6oza0dggkQt6zWF-ZnYUKobclO7i3x9kiS1CETGQlCVcifs6UfqytY8vunKIJlM$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!w60__6oza0dggkQt6zWF-ZnYUKobclO7i3x9kiS1CETGQlCVcifs6UfqytY8vns85I56$ > > > > + > > +title: MediaTek DSI Controller Device Tree Bindings > > + > > +maintainers: > > + - Chun-Kuang Hu > > + - Philipp Zabel > > + - Jitao Shi > > + - Xinlei Lee > > + > > +description: | > > + The MediaTek DSI function block is a sink of the display > > subsystem and can > > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > > for dual- > > + channel output. > > + > > +allOf: > > + - $ref: /schemas/display/dsi-controller.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - mediatek,mt2701-dsi > > + - mediatek,mt7623-dsi > > + - mediatek,mt8167-dsi > > + - mediatek,mt8173-dsi > > + - mediatek,mt8183-dsi > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Engine Clock > > + - description: Digital Clock > > + - description: HS Clock > > + > > + clock-names: > > + items: > > + - const: engine > > + - const: digital > > + - const: hs > > + > > + resets: > > + maxItems: 1 > > + > > + phys: > > + maxItems: 1 > > + > > + phy-names: > > + items: > > + - const: dphy > > + > > + port: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: > > + Output port node. This port should be connected to the input > > + port of an attached DSI panel or DSI-to-eDP encoder chip. > > + > > + > > 1 blank line Hello Rob, Thanks for your review. ok. I will do this in next version. > > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > Did you try adding these? Because they are wrong and will contradict > dsi-controller.yaml. > We have some mistake. There will not be any sub node for mediatek dsi, so I will drop this modification in next version. BRs, Rex > Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4336EC433F5 for ; Wed, 4 May 2022 08:11:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gbOZqTeJn7oV3s6zANbah2x+SL7PaAJig1+gqtbNygA=; b=PyHb8Mh8k0de+z QsIvdTKkTe99iUTLBM7OnYnBISQj9d1ioWtY3DSQUvrWFXEthBRAMZl9pmOKfmRuSKShQ8Qge0ikD sK93JXRzPThJ/zMzo4MX/Umr+JOr6BDd8hf5MjdEpTXsHE4ajKGXWBu3nYd0b3Kd2HWK2fUyQVULN OylpoxJXJgy+7IJnY2XCEePZYFLCYoMKX8sDSkI0YQnVNWUQ3TlVEGuwIl3KmZ6RNX4y3bpkA2s9X YUPV1vhbjjl28ZzTo7fJj6YiISYaK0u4aSjeOoP11c77jOWRjcLobxg2U72YzJaAC2XdAEz9O0CBM rNy78aWtSNY4MlRIYn0g==; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Tue, 2022-05-03 at 13:01 -0500, Rob Herring wrote: > On Thu, Apr 28, 2022 at 09:37:50PM +0800, Rex-BC Chen wrote: > > From: Xinlei Lee > > > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > > > Signed-off-by: Xinlei Lee > > Signed-off-by: Rex-BC Chen > > --- > > .../display/mediatek/mediatek,dsi.txt | 62 --------- > > .../display/mediatek/mediatek,dsi.yaml | 122 > > ++++++++++++++++++ > > 2 files changed, 122 insertions(+), 62 deletions(-) > > delete mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > > l > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > deleted file mode 100644 > > index 36b01458f45c..000000000000 > > --- > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > +++ /dev/null > > @@ -1,62 +0,0 @@ > > -Mediatek DSI Device > > -=================== > > - > > -The Mediatek DSI function block is a sink of the display subsystem > > and can > > -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > > for dual- > > -channel output. > > - > > -Required properties: > > -- compatible: "mediatek,-dsi" > > -- the supported chips are mt2701, mt7623, mt8167, mt8173 and > > mt8183. > > -- reg: Physical base address and length of the controller's > > registers > > -- interrupts: The interrupt signal from the function block. > > -- clocks: device clocks > > - See Documentation/devicetree/bindings/clock/clock-bindings.txt > > for details. > > -- clock-names: must contain "engine", "digital", and "hs" > > -- phys: phandle link to the MIPI D-PHY controller. > > -- phy-names: must contain "dphy" > > -- port: Output port node with endpoint definitions as described in > > - Documentation/devicetree/bindings/graph.txt. This port should be > > connected > > - to the input port of an attached DSI panel or DSI-to-eDP encoder > > chip. > > - > > -Optional properties: > > -- resets: list of phandle + reset specifier pair, as described in > > [1]. > > - > > -[1] Documentation/devicetree/bindings/reset/reset.txt > > - > > -MIPI TX Configuration Module > > -============================ > > - > > -See phy/mediatek,dsi-phy.yaml > > - > > -Example: > > - > > -mipi_tx0: mipi-dphy@10215000 { > > - compatible = "mediatek,mt8173-mipi-tx"; > > - reg = <0 0x10215000 0 0x1000>; > > - clocks = <&clk26m>; > > - clock-output-names = "mipi_tx0_pll"; > > - #clock-cells = <0>; > > - #phy-cells = <0>; > > - drive-strength-microamp = <4600>; > > - nvmem-cells= <&mipi_tx_calibration>; > > - nvmem-cell-names = "calibration-data"; > > -}; > > - > > -dsi0: dsi@1401b000 { > > - compatible = "mediatek,mt8173-dsi"; > > - reg = <0 0x1401b000 0 0x1000>; > > - interrupts = ; > > - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, > > - <&mipi_tx0>; > > - clock-names = "engine", "digital", "hs"; > > - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; > > - phys = <&mipi_tx0>; > > - phy-names = "dphy"; > > - > > - port { > > - dsi0_out: endpoint { > > - remote-endpoint = <&panel_in>; > > - }; > > - }; > > -}; > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > new file mode 100644 > > index 000000000000..2ca9229ef69e > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > @@ -0,0 +1,122 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml*__;Iw!!CTRNKA9wMg0ARbw!w60__6oza0dggkQt6zWF-ZnYUKobclO7i3x9kiS1CETGQlCVcifs6UfqytY8vunKIJlM$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!w60__6oza0dggkQt6zWF-ZnYUKobclO7i3x9kiS1CETGQlCVcifs6UfqytY8vns85I56$ > > > > + > > +title: MediaTek DSI Controller Device Tree Bindings > > + > > +maintainers: > > + - Chun-Kuang Hu > > + - Philipp Zabel > > + - Jitao Shi > > + - Xinlei Lee > > + > > +description: | > > + The MediaTek DSI function block is a sink of the display > > subsystem and can > > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > > for dual- > > + channel output. > > + > > +allOf: > > + - $ref: /schemas/display/dsi-controller.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - mediatek,mt2701-dsi > > + - mediatek,mt7623-dsi > > + - mediatek,mt8167-dsi > > + - mediatek,mt8173-dsi > > + - mediatek,mt8183-dsi > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Engine Clock > > + - description: Digital Clock > > + - description: HS Clock > > + > > + clock-names: > > + items: > > + - const: engine > > + - const: digital > > + - const: hs > > + > > + resets: > > + maxItems: 1 > > + > > + phys: > > + maxItems: 1 > > + > > + phy-names: > > + items: > > + - const: dphy > > + > > + port: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: > > + Output port node. This port should be connected to the input > > + port of an attached DSI panel or DSI-to-eDP encoder chip. > > + > > + > > 1 blank line Hello Rob, Thanks for your review. ok. I will do this in next version. > > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > Did you try adding these? Because they are wrong and will contradict > dsi-controller.yaml. > We have some mistake. There will not be any sub node for mediatek dsi, so I will drop this modification in next version. BRs, Rex > Rob _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1DA6EC433F5 for ; Wed, 4 May 2022 08:12:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Wed, 04 May 2022 01:11:00 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 4 May 2022 01:05:59 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 4 May 2022 16:05:58 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 16:05:58 +0800 Message-ID: Subject: Re: [PATCH v5 1/4] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml From: Rex-BC Chen To: Rob Herring CC: , , , , , , , , , , , , Date: Wed, 4 May 2022 16:05:58 +0800 In-Reply-To: References: <20220428133753.8348-1-rex-bc.chen@mediatek.com> <20220428133753.8348-2-rex-bc.chen@mediatek.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_011108_019984_C8569EE7 X-CRM114-Status: GOOD ( 30.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 2022-05-03 at 13:01 -0500, Rob Herring wrote: > On Thu, Apr 28, 2022 at 09:37:50PM +0800, Rex-BC Chen wrote: > > From: Xinlei Lee > > > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format > > > > Signed-off-by: Xinlei Lee > > Signed-off-by: Rex-BC Chen > > --- > > .../display/mediatek/mediatek,dsi.txt | 62 --------- > > .../display/mediatek/mediatek,dsi.yaml | 122 > > ++++++++++++++++++ > > 2 files changed, 122 insertions(+), 62 deletions(-) > > delete mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > > l > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > deleted file mode 100644 > > index 36b01458f45c..000000000000 > > --- > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t > > xt > > +++ /dev/null > > @@ -1,62 +0,0 @@ > > -Mediatek DSI Device > > -=================== > > - > > -The Mediatek DSI function block is a sink of the display subsystem > > and can > > -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > > for dual- > > -channel output. > > - > > -Required properties: > > -- compatible: "mediatek,-dsi" > > -- the supported chips are mt2701, mt7623, mt8167, mt8173 and > > mt8183. > > -- reg: Physical base address and length of the controller's > > registers > > -- interrupts: The interrupt signal from the function block. > > -- clocks: device clocks > > - See Documentation/devicetree/bindings/clock/clock-bindings.txt > > for details. > > -- clock-names: must contain "engine", "digital", and "hs" > > -- phys: phandle link to the MIPI D-PHY controller. > > -- phy-names: must contain "dphy" > > -- port: Output port node with endpoint definitions as described in > > - Documentation/devicetree/bindings/graph.txt. This port should be > > connected > > - to the input port of an attached DSI panel or DSI-to-eDP encoder > > chip. > > - > > -Optional properties: > > -- resets: list of phandle + reset specifier pair, as described in > > [1]. > > - > > -[1] Documentation/devicetree/bindings/reset/reset.txt > > - > > -MIPI TX Configuration Module > > -============================ > > - > > -See phy/mediatek,dsi-phy.yaml > > - > > -Example: > > - > > -mipi_tx0: mipi-dphy@10215000 { > > - compatible = "mediatek,mt8173-mipi-tx"; > > - reg = <0 0x10215000 0 0x1000>; > > - clocks = <&clk26m>; > > - clock-output-names = "mipi_tx0_pll"; > > - #clock-cells = <0>; > > - #phy-cells = <0>; > > - drive-strength-microamp = <4600>; > > - nvmem-cells= <&mipi_tx_calibration>; > > - nvmem-cell-names = "calibration-data"; > > -}; > > - > > -dsi0: dsi@1401b000 { > > - compatible = "mediatek,mt8173-dsi"; > > - reg = <0 0x1401b000 0 0x1000>; > > - interrupts = ; > > - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, > > - <&mipi_tx0>; > > - clock-names = "engine", "digital", "hs"; > > - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; > > - phys = <&mipi_tx0>; > > - phy-names = "dphy"; > > - > > - port { > > - dsi0_out: endpoint { > > - remote-endpoint = <&panel_in>; > > - }; > > - }; > > -}; > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > new file mode 100644 > > index 000000000000..2ca9229ef69e > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y > > aml > > @@ -0,0 +1,122 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml*__;Iw!!CTRNKA9wMg0ARbw!w60__6oza0dggkQt6zWF-ZnYUKobclO7i3x9kiS1CETGQlCVcifs6UfqytY8vunKIJlM$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!w60__6oza0dggkQt6zWF-ZnYUKobclO7i3x9kiS1CETGQlCVcifs6UfqytY8vns85I56$ > > > > + > > +title: MediaTek DSI Controller Device Tree Bindings > > + > > +maintainers: > > + - Chun-Kuang Hu > > + - Philipp Zabel > > + - Jitao Shi > > + - Xinlei Lee > > + > > +description: | > > + The MediaTek DSI function block is a sink of the display > > subsystem and can > > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > > for dual- > > + channel output. > > + > > +allOf: > > + - $ref: /schemas/display/dsi-controller.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - mediatek,mt2701-dsi > > + - mediatek,mt7623-dsi > > + - mediatek,mt8167-dsi > > + - mediatek,mt8173-dsi > > + - mediatek,mt8183-dsi > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Engine Clock > > + - description: Digital Clock > > + - description: HS Clock > > + > > + clock-names: > > + items: > > + - const: engine > > + - const: digital > > + - const: hs > > + > > + resets: > > + maxItems: 1 > > + > > + phys: > > + maxItems: 1 > > + > > + phy-names: > > + items: > > + - const: dphy > > + > > + port: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: > > + Output port node. This port should be connected to the input > > + port of an attached DSI panel or DSI-to-eDP encoder chip. > > + > > + > > 1 blank line Hello Rob, Thanks for your review. ok. I will do this in next version. > > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > Did you try adding these? Because they are wrong and will contradict > dsi-controller.yaml. > We have some mistake. There will not be any sub node for mediatek dsi, so I will drop this modification in next version. BRs, Rex > Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel