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charset="us-ascii"; Format="flowed" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Arcturus callbacks were dropped in another patch in this series. Instead of dropping, better to keep the callbacks and use the specific reg offsets. Thanks, Lijo On 7/7/2021 7:26 AM, Evan Quan wrote: > These registers have different address from other SMU V11 ASICs. > > Change-Id: Iaeb0438331eed9b0313933da25622f8e4c048fab > Signed-off-by: Evan Quan > --- > .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 104 +++++++++++++----- > 1 file changed, 78 insertions(+), 26 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c > index 319bd7689df4..414c8674e32f 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c > @@ -79,6 +79,24 @@ MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin"); > #define mmTHM_BACO_CNTL_ARCT 0xA7 > #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0 > > +#define mmCG_FDO_CTRL0_ARCT 0x8B > +#define mmCG_FDO_CTRL0_ARCT_BASE_IDX 0 > + > +#define mmCG_FDO_CTRL1_ARCT 0x8C > +#define mmCG_FDO_CTRL1_ARCT_BASE_IDX 0 > + > +#define mmCG_FDO_CTRL2_ARCT 0x8D > +#define mmCG_FDO_CTRL2_ARCT_BASE_IDX 0 > + > +#define mmCG_TACH_CTRL_ARCT 0x8E > +#define mmCG_TACH_CTRL_ARCT_BASE_IDX 0 > + > +#define mmCG_TACH_STATUS_ARCT 0x8F > +#define mmCG_TACH_STATUS_ARCT_BASE_IDX 0 > + > +#define mmCG_THERMAL_STATUS_ARCT 0x90 > +#define mmCG_THERMAL_STATUS_ARCT_BASE_IDX 0 > + > int smu_v11_0_init_microcode(struct smu_context *smu) > { > struct amdgpu_device *adev = smu->adev; > @@ -1174,12 +1192,21 @@ smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) > { > struct amdgpu_device *adev = smu->adev; > > - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, > - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), > - CG_FDO_CTRL2, TMIN, 0)); > - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, > - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), > - CG_FDO_CTRL2, FDO_PWM_MODE, mode)); > + if (adev->asic_type == CHIP_ARCTURUS) { > + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT, > + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT), > + CG_FDO_CTRL2, TMIN, 0)); > + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT, > + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT), > + CG_FDO_CTRL2, FDO_PWM_MODE, mode)); > + } else { > + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, > + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), > + CG_FDO_CTRL2, TMIN, 0)); > + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, > + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), > + CG_FDO_CTRL2, FDO_PWM_MODE, mode)); > + } > > return 0; > } > @@ -1194,8 +1221,12 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) > if (speed > 255) > speed = 255; > > - duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), > - CG_FDO_CTRL1, FMAX_DUTY100); > + if (adev->asic_type == CHIP_ARCTURUS) > + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT), > + CG_FDO_CTRL1, FMAX_DUTY100); > + else > + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), > + CG_FDO_CTRL1, FMAX_DUTY100); > if (!duty100) > return -EINVAL; > > @@ -1203,9 +1234,14 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) > do_div(tmp64, 255); > duty = (uint32_t)tmp64; > > - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, > - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), > - CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); > + if (adev->asic_type == CHIP_ARCTURUS) > + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT, > + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT), > + CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); > + else > + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, > + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), > + CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); > > return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); > } > @@ -1214,13 +1250,14 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu, > uint32_t speed) > { > struct amdgpu_device *adev = smu->adev; > - uint32_t tach_period, crystal_clock_freq; > - > /* > * crystal_clock_freq div by 4 is required since the fan control > * module refers to 25MHz > + * crystal_clock_freq used for fan speed rpm calculation is > + * always 25Mhz. So, hardcode it as 2500(in 10K unit). > */ > - crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4; > + uint32_t crystal_clock_freq = 2500; > + uint32_t tach_period; > > /* > * To prevent from possible overheat, some ASICs may have requirement > @@ -1231,10 +1268,16 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu, > * lower than 500 RPM. > */ > tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); > - WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, > - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), > - CG_TACH_CTRL, TARGET_PERIOD, > - tach_period)); > + if (adev->asic_type == CHIP_ARCTURUS) > + WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT, > + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT), > + CG_TACH_CTRL, TARGET_PERIOD, > + tach_period)); > + else > + WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, > + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), > + CG_TACH_CTRL, TARGET_PERIOD, > + tach_period)); > > return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); > } > @@ -1257,10 +1300,17 @@ int smu_v11_0_get_fan_speed_percent(struct smu_context *smu, > return 0; > } > > - duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), > - CG_FDO_CTRL1, FMAX_DUTY100); > - duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), > - CG_THERMAL_STATUS, FDO_PWM_DUTY); > + if (adev->asic_type == CHIP_ARCTURUS) { > + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT), > + CG_FDO_CTRL1, FMAX_DUTY100); > + duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT), > + CG_THERMAL_STATUS, FDO_PWM_DUTY); > + } else { > + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), > + CG_FDO_CTRL1, FMAX_DUTY100); > + duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), > + CG_THERMAL_STATUS, FDO_PWM_DUTY); > + } > if (!duty100) > return -EINVAL; > > @@ -1278,7 +1328,8 @@ int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu, > uint32_t *speed) > { > struct amdgpu_device *adev = smu->adev; > - uint32_t tach_status, crystal_clock_freq; > + uint32_t crystal_clock_freq = 2500; > + uint32_t tach_status; > uint64_t tmp64; > > /* > @@ -1292,10 +1343,11 @@ int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu, > return 0; > } > > - crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4; > tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000; > - > - tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS); > + if (adev->asic_type == CHIP_ARCTURUS) > + tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT); > + else > + tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS); > do_div(tmp64, tach_status); > *speed = (uint32_t)tmp64; > > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx