* [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders
@ 2020-11-06 10:14 Gwan-gyeong Mun
2020-11-06 10:14 ` [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs Gwan-gyeong Mun
` (9 more replies)
0 siblings, 10 replies; 17+ messages in thread
From: Gwan-gyeong Mun @ 2020-11-06 10:14 UTC (permalink / raw)
To: intel-gfx
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handling routine for supporting
multiple transcoders. But it does not change the scenario and timing of
enabling and disabling PSR.
v2: Fix indentation and add comments
v3: Remove Blank line
v4: Rebased
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +
drivers/gpu/drm/i915/display/intel_display.c | 4 -
.../drm/i915/display/intel_display_debugfs.c | 111 ++--
.../drm/i915/display/intel_display_types.h | 38 ++
drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
drivers/gpu/drm/i915/display/intel_psr.c | 585 ++++++++++--------
drivers/gpu/drm/i915/display/intel_psr.h | 14 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 38 --
drivers/gpu/drm/i915/i915_irq.c | 47 +-
10 files changed, 491 insertions(+), 380 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 19b16517a502..983781ce3683 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4127,7 +4127,10 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
intel_ddi_set_dp_msa(crtc_state, conn_state);
+ //TODO: move PSR related functions into intel_psr_update()
+ intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
intel_psr_update(intel_dp, crtc_state, conn_state);
+
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_update(intel_dp, crtc_state);
@@ -5275,6 +5278,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
goto err;
dig_port->hpd_pulse = intel_dp_hpd_pulse;
+
+ intel_psr_init(&dig_port->dp);
}
/* In theory we don't need the encoder->type check, but leave it just in
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8c4687b19814..466923a54370 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15506,8 +15506,6 @@ static void commit_pipe_config(struct intel_atomic_state *state,
if (new_crtc_state->update_pipe)
intel_pipe_fastset(old_crtc_state, new_crtc_state);
-
- intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
}
if (dev_priv->display.atomic_update_watermarks)
@@ -17435,8 +17433,6 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_dvo_init(dev_priv);
}
- intel_psr_init(dev_priv);
-
for_each_intel_encoder(&dev_priv->drm, encoder) {
encoder->base.possible_crtcs =
intel_encoder_possible_crtcs(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cfb4c1474982..8402e6ac9f76 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -248,18 +248,17 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
"sink internal error",
};
struct drm_connector *connector = m->private;
- struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
int ret;
- if (!CAN_PSR(dev_priv)) {
- seq_puts(m, "PSR Unsupported\n");
+ if (connector->status != connector_status_connected)
return -ENODEV;
- }
- if (connector->status != connector_status_connected)
+ if (!CAN_PSR(intel_dp)) {
+ seq_puts(m, "PSR Unsupported\n");
return -ENODEV;
+ }
ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
@@ -279,12 +278,13 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
static void
-psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
+psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
{
u32 val, status_val;
const char *status = "unknown";
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (dev_priv->psr.psr2_enabled) {
+ if (intel_dp->psr.psr2_enabled) {
static const char * const live_status[] = {
"IDLE",
"CAPTURE",
@@ -299,7 +299,7 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
"TG_ON"
};
val = intel_de_read(dev_priv,
- EDP_PSR2_STATUS(dev_priv->psr.transcoder));
+ EDP_PSR2_STATUS(intel_dp->psr.transcoder));
status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
EDP_PSR2_STATUS_STATE_SHIFT;
if (status_val < ARRAY_SIZE(live_status))
@@ -316,7 +316,7 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
"SRDENT_ON",
};
val = intel_de_read(dev_priv,
- EDP_PSR_STATUS(dev_priv->psr.transcoder));
+ EDP_PSR_STATUS(intel_dp->psr.transcoder));
status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
EDP_PSR_STATUS_STATE_SHIFT;
if (status_val < ARRAY_SIZE(live_status))
@@ -326,21 +326,18 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
}
-static int i915_edp_psr_status(struct seq_file *m, void *data)
+static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct i915_psr *psr = &dev_priv->psr;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_psr *psr = &intel_dp->psr;
intel_wakeref_t wakeref;
const char *status;
bool enabled;
u32 val;
- if (!HAS_PSR(dev_priv))
- return -ENODEV;
-
seq_printf(m, "Sink support: %s", yesno(psr->sink_support));
- if (psr->dp)
- seq_printf(m, " [0x%02x]", psr->dp->psr_dpcd[0]);
+ if (psr->sink_support)
+ seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
seq_puts(m, "\n");
if (!psr->sink_support)
@@ -364,16 +361,16 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
if (psr->psr2_enabled) {
val = intel_de_read(dev_priv,
- EDP_PSR2_CTL(dev_priv->psr.transcoder));
+ EDP_PSR2_CTL(intel_dp->psr.transcoder));
enabled = val & EDP_PSR2_ENABLE;
} else {
val = intel_de_read(dev_priv,
- EDP_PSR_CTL(dev_priv->psr.transcoder));
+ EDP_PSR_CTL(intel_dp->psr.transcoder));
enabled = val & EDP_PSR_ENABLE;
}
seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
enableddisabled(enabled), val);
- psr_source_status(dev_priv, m);
+ psr_source_status(intel_dp, m);
seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
psr->busy_frontbuffer_bits);
@@ -382,7 +379,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
*/
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
val = intel_de_read(dev_priv,
- EDP_PSR_PERF_CNT(dev_priv->psr.transcoder));
+ EDP_PSR_PERF_CNT(intel_dp->psr.transcoder));
val &= EDP_PSR_PERF_CNT_MASK;
seq_printf(m, "Performance counter: %u\n", val);
}
@@ -403,7 +400,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
*/
for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
val = intel_de_read(dev_priv,
- PSR2_SU_STATUS(dev_priv->psr.transcoder, frame));
+ PSR2_SU_STATUS(intel_dp->psr.transcoder, frame));
su_frames_val[frame / 3] = val;
}
@@ -429,23 +426,57 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
return 0;
}
+static int i915_edp_psr_status(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp = NULL;
+
+ if (!HAS_PSR(dev_priv))
+ return -ENODEV;
+
+ /* Find the first EDP */
+ for_each_intel_dp(&dev_priv->drm, encoder) {
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ intel_dp = enc_to_intel_dp(encoder);
+ break;
+ }
+ }
+
+ if (!intel_dp)
+ return -ENODEV;
+
+ return intel_psr_status(m, intel_dp);
+}
+
static int
i915_edp_psr_debug_set(void *data, u64 val)
{
struct drm_i915_private *dev_priv = data;
intel_wakeref_t wakeref;
- int ret;
+ int ret = -ENODEV;
+ struct intel_encoder *encoder;
- if (!CAN_PSR(dev_priv))
- return -ENODEV;
+ if (!HAS_PSR(dev_priv))
+ return ret;
- drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val);
+ for_each_intel_dp(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
+ if (!CAN_PSR(intel_dp))
+ continue;
- ret = intel_psr_debug_set(dev_priv, val);
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val);
- intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
+ wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
+
+ // TODO: split to each transcoder's PSR debug state
+ ret = intel_psr_debug_set(intel_dp, val);
+
+ intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
+ }
+ }
return ret;
}
@@ -454,12 +485,25 @@ static int
i915_edp_psr_debug_get(void *data, u64 *val)
{
struct drm_i915_private *dev_priv = data;
+ struct intel_encoder *encoder;
- if (!CAN_PSR(dev_priv))
+ if (!HAS_PSR(dev_priv))
return -ENODEV;
- *val = READ_ONCE(dev_priv->psr.debug);
- return 0;
+ for_each_intel_dp(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ if (!CAN_PSR(intel_dp))
+ continue;
+
+ // TODO: split to each transcoder's PSR debug state
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ *val = READ_ONCE(intel_dp->psr.debug);
+ return 0;
+ }
+ }
+
+ return -ENODEV;
}
DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
@@ -1103,9 +1147,6 @@ static void drrs_status_per_crtc(struct seq_file *m,
/* disable_drrs() will make drrs->dp NULL */
if (!drrs->dp) {
seq_puts(m, "Idleness DRRS: Disabled\n");
- if (dev_priv->psr.enabled)
- seq_puts(m,
- "\tAs PSR is enabled, DRRS is not enabled\n");
mutex_unlock(&drrs->mutex);
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..2e40fcbab2aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1286,6 +1286,42 @@ struct intel_dp_compliance {
u8 test_lane_count;
};
+struct intel_psr {
+ /* Mutex for PSR state of the transcoder */
+ struct mutex lock;
+
+#define I915_PSR_DEBUG_MODE_MASK 0x0f
+#define I915_PSR_DEBUG_DEFAULT 0x00
+#define I915_PSR_DEBUG_DISABLE 0x01
+#define I915_PSR_DEBUG_ENABLE 0x02
+#define I915_PSR_DEBUG_FORCE_PSR1 0x03
+#define I915_PSR_DEBUG_IRQ 0x10
+
+ u32 debug;
+ bool sink_support;
+ bool enabled;
+ enum pipe pipe;
+ enum transcoder transcoder;
+ bool active;
+ struct work_struct work;
+ unsigned int busy_frontbuffer_bits;
+ bool sink_psr2_support;
+ bool link_standby;
+ bool colorimetry_support;
+ bool psr2_enabled;
+ bool psr2_sel_fetch_enabled;
+ u8 sink_sync_latency;
+ ktime_t last_entry_attempt;
+ ktime_t last_exit;
+ bool sink_not_reliable;
+ bool irq_aux_error;
+ u16 su_x_granularity;
+ bool dc3co_enabled;
+ u32 dc3co_exit_delay;
+ struct delayed_work dc3co_work;
+ struct drm_dp_vsc_sdp vsc;
+};
+
struct intel_dp {
i915_reg_t output_reg;
u32 DP;
@@ -1406,6 +1442,8 @@ struct intel_dp {
bool hobl_failed;
bool hobl_active;
+
+ struct intel_psr psr;
};
enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3b0dbda5919a..64abc9d037f8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2640,12 +2640,10 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
const struct drm_connector_state *conn_state,
struct drm_dp_vsc_sdp *vsc)
{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
vsc->sdp_type = DP_SDP_VSC;
- if (dev_priv->psr.psr2_enabled) {
- if (dev_priv->psr.colorimetry_support &&
+ if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.colorimetry_support &&
intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
/* [PSR2, +Colorimetry] */
intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
@@ -3778,7 +3776,7 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
return false;
}
- if (CAN_PSR(i915) && intel_dp_is_edp(intel_dp)) {
+ if (CAN_PSR(intel_dp) && intel_dp_is_edp(intel_dp)) {
drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
crtc_state->uapi.mode_changed = true;
return false;
@@ -7978,6 +7976,17 @@ static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
drm_kms_helper_hotplug_event(connector->dev);
}
+static void intel_dp_update_pipe(struct intel_atomic_state *state,
+ struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
+ intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
+}
+
bool
intel_dp_init_connector(struct intel_digital_port *dig_port,
struct intel_connector *intel_connector)
@@ -8133,7 +8142,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->get_config = intel_dp_get_config;
intel_encoder->sync_state = intel_dp_sync_state;
intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
- intel_encoder->update_pipe = intel_panel_update_backlight;
+ intel_encoder->update_pipe = intel_dp_update_pipe;
intel_encoder->suspend = intel_dp_encoder_suspend;
intel_encoder->shutdown = intel_dp_encoder_shutdown;
if (IS_CHERRYVIEW(dev_priv)) {
@@ -8220,6 +8229,8 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
if (!intel_dp_init_connector(dig_port, intel_connector))
goto err_init_connector;
+ intel_psr_init(&dig_port->dp);
+
return true;
err_init_connector:
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b3631b722de3..8d858d56c736 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -79,11 +79,13 @@
* use page flips.
*/
-static bool psr_global_enabled(struct drm_i915_private *i915)
+static bool psr_global_enabled(struct intel_dp *intel_dp)
{
- switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_DEFAULT:
- return i915->params.enable_psr;
+ return dev_priv->params.enable_psr;
case I915_PSR_DEBUG_DISABLE:
return false;
default:
@@ -91,9 +93,9 @@ static bool psr_global_enabled(struct drm_i915_private *i915)
}
}
-static bool psr2_global_enabled(struct drm_i915_private *dev_priv)
+static bool psr2_global_enabled(struct intel_dp *intel_dp)
{
- switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
+ switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_DISABLE:
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
@@ -102,11 +104,12 @@ static bool psr2_global_enabled(struct drm_i915_private *dev_priv)
}
}
-static void psr_irq_control(struct drm_i915_private *dev_priv)
+static void psr_irq_control(struct intel_dp *intel_dp)
{
enum transcoder trans_shift;
u32 mask, val;
i915_reg_t imr_reg;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
/*
* gen12+ has registers relative to transcoder and one per transcoder
@@ -115,14 +118,14 @@ static void psr_irq_control(struct drm_i915_private *dev_priv)
*/
if (INTEL_GEN(dev_priv) >= 12) {
trans_shift = 0;
- imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
+ imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
} else {
- trans_shift = dev_priv->psr.transcoder;
+ trans_shift = intel_dp->psr.transcoder;
imr_reg = EDP_PSR_IMR;
}
mask = EDP_PSR_ERROR(trans_shift);
- if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
+ if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
mask |= EDP_PSR_POST_EXIT(trans_shift) |
EDP_PSR_PRE_ENTRY(trans_shift);
@@ -171,38 +174,37 @@ static void psr_event_print(struct drm_i915_private *i915,
drm_dbg_kms(&i915->drm, "\tPSR disabled\n");
}
-void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
+void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
{
- enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
enum transcoder trans_shift;
i915_reg_t imr_reg;
ktime_t time_ns = ktime_get();
if (INTEL_GEN(dev_priv) >= 12) {
trans_shift = 0;
- imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
+ imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
} else {
- trans_shift = dev_priv->psr.transcoder;
+ trans_shift = intel_dp->psr.transcoder;
imr_reg = EDP_PSR_IMR;
}
if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
- dev_priv->psr.last_entry_attempt = time_ns;
- drm_dbg_kms(&dev_priv->drm,
- "[transcoder %s] PSR entry attempt in 2 vblanks\n",
- transcoder_name(cpu_transcoder));
+ intel_dp->psr.last_entry_attempt = time_ns;
+ DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
+ transcoder_name(cpu_transcoder));
}
if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
- dev_priv->psr.last_exit = time_ns;
- drm_dbg_kms(&dev_priv->drm,
- "[transcoder %s] PSR exit completed\n",
- transcoder_name(cpu_transcoder));
+ intel_dp->psr.last_exit = time_ns;
+ DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
+ transcoder_name(cpu_transcoder));
if (INTEL_GEN(dev_priv) >= 9) {
u32 val = intel_de_read(dev_priv,
PSR_EVENT(cpu_transcoder));
- bool psr2_enabled = dev_priv->psr.psr2_enabled;
+ bool psr2_enabled = intel_dp->psr.psr2_enabled;
intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder),
val);
@@ -213,10 +215,10 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
u32 val;
- drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
+ DRM_WARN("[transcoder %s] PSR aux error\n",
transcoder_name(cpu_transcoder));
- dev_priv->psr.irq_aux_error = true;
+ intel_dp->psr.irq_aux_error = true;
/*
* If this interruption is not masked it will keep
@@ -230,7 +232,7 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
val |= EDP_PSR_ERROR(trans_shift);
intel_de_write(dev_priv, imr_reg, val);
- schedule_work(&dev_priv->psr.work);
+ schedule_work(&intel_dp->psr.work);
}
}
@@ -291,12 +293,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv =
to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
- if (dev_priv->psr.dp) {
- drm_warn(&dev_priv->drm,
- "More than one eDP panel found, PSR support should be extended\n");
- return;
- }
-
drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
sizeof(intel_dp->psr_dpcd));
@@ -317,12 +313,10 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
return;
}
- dev_priv->psr.sink_support = true;
- dev_priv->psr.sink_sync_latency =
+ intel_dp->psr.sink_support = true;
+ intel_dp->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);
- dev_priv->psr.dp = intel_dp;
-
if (INTEL_GEN(dev_priv) >= 9 &&
(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
bool y_req = intel_dp->psr_dpcd[1] &
@@ -340,14 +334,14 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
* Y-coordinate requirement panels we would need to enable
* GTC first.
*/
- dev_priv->psr.sink_psr2_support = y_req && alpm;
+ intel_dp->psr.sink_psr2_support = y_req && alpm;
drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
- dev_priv->psr.sink_psr2_support ? "" : "not ");
+ intel_dp->psr.sink_psr2_support ? "" : "not ");
- if (dev_priv->psr.sink_psr2_support) {
- dev_priv->psr.colorimetry_support =
+ if (intel_dp->psr.sink_psr2_support) {
+ intel_dp->psr.colorimetry_support =
intel_dp_get_colorimetry_status(intel_dp);
- dev_priv->psr.su_x_granularity =
+ intel_dp->psr.su_x_granularity =
intel_dp_get_su_x_granulartiy(intel_dp);
}
}
@@ -373,7 +367,7 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
BUILD_BUG_ON(sizeof(aux_msg) > 20);
for (i = 0; i < sizeof(aux_msg); i += 4)
intel_de_write(dev_priv,
- EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2),
+ EDP_PSR_AUX_DATA(intel_dp->psr.transcoder, i >> 2),
intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
@@ -384,7 +378,7 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
/* Select only valid bits for SRD_AUX_CTL */
aux_ctl &= psr_aux_mask;
- intel_de_write(dev_priv, EDP_PSR_AUX_CTL(dev_priv->psr.transcoder),
+ intel_de_write(dev_priv, EDP_PSR_AUX_CTL(intel_dp->psr.transcoder),
aux_ctl);
}
@@ -394,14 +388,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
u8 dpcd_val = DP_PSR_ENABLE;
/* Enable ALPM at sink for psr2 */
- if (dev_priv->psr.psr2_enabled) {
+ if (intel_dp->psr.psr2_enabled) {
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE |
DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
} else {
- if (dev_priv->psr.link_standby)
+ if (intel_dp->psr.link_standby)
dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
if (INTEL_GEN(dev_priv) >= 8)
@@ -464,7 +458,7 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
* off-by-one issue that HW has in some cases.
*/
idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
- idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+ idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
idle_frames = 0xf;
@@ -484,7 +478,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
if (IS_HASWELL(dev_priv))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
- if (dev_priv->psr.link_standby)
+ if (intel_dp->psr.link_standby)
val |= EDP_PSR_LINK_STANDBY;
val |= intel_psr1_get_tp_time(intel_dp);
@@ -492,9 +486,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
if (INTEL_GEN(dev_priv) >= 8)
val |= EDP_PSR_CRC_ENABLE;
- val |= (intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) &
+ val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &
EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
- intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), val);
+ intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val);
}
static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
@@ -529,7 +523,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
val |= EDP_Y_COORDINATE_ENABLE;
- val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
+ val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
val |= intel_psr2_get_tp_time(intel_dp);
if (INTEL_GEN(dev_priv) >= 12) {
@@ -548,7 +542,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= EDP_PSR2_FAST_WAKE(7);
}
- if (dev_priv->psr.psr2_sel_fetch_enabled) {
+ if (intel_dp->psr.psr2_sel_fetch_enabled) {
/* WA 1408330847 */
if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
@@ -557,20 +551,20 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
DIS_RAM_BYPASS_PSR2_MAN_TRACK);
intel_de_write(dev_priv,
- PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder),
+ PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
PSR2_MAN_TRK_CTL_ENABLE);
} else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
intel_de_write(dev_priv,
- PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0);
+ PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
}
/*
* PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
* recommending keep this bit unset while PSR2 is enabled.
*/
- intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), 0);
+ intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0);
- intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
+ intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
}
static bool
@@ -593,55 +587,58 @@ static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
drm_mode_vrefresh(&cstate->hw.adjusted_mode));
}
-static void psr2_program_idle_frames(struct drm_i915_private *dev_priv,
+static void psr2_program_idle_frames(struct intel_dp *intel_dp,
u32 idle_frames)
{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 val;
idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
- val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder));
+ val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder));
val &= ~EDP_PSR2_IDLE_FRAME_MASK;
val |= idle_frames;
- intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
+ intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
}
-static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv)
+static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
{
- psr2_program_idle_frames(dev_priv, 0);
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ psr2_program_idle_frames(intel_dp, 0);
intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
}
-static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv)
+static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
{
- struct intel_dp *intel_dp = dev_priv->psr.dp;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
- psr2_program_idle_frames(dev_priv, psr_compute_idle_frames(intel_dp));
+ psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
}
static void tgl_dc3co_disable_work(struct work_struct *work)
{
- struct drm_i915_private *dev_priv =
- container_of(work, typeof(*dev_priv), psr.dc3co_work.work);
+ struct intel_dp *intel_dp =
+ container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
- mutex_lock(&dev_priv->psr.lock);
+ mutex_lock(&intel_dp->psr.lock);
/* If delayed work is pending, it is not idle */
- if (delayed_work_pending(&dev_priv->psr.dc3co_work))
+ if (delayed_work_pending(&intel_dp->psr.dc3co_work))
goto unlock;
- tgl_psr2_disable_dc3co(dev_priv);
+ tgl_psr2_disable_dc3co(intel_dp);
unlock:
- mutex_unlock(&dev_priv->psr.lock);
+ mutex_unlock(&intel_dp->psr.lock);
}
-static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
+static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
{
- if (!dev_priv->psr.dc3co_enabled)
+ if (!intel_dp->psr.dc3co_enabled)
return;
- cancel_delayed_work(&dev_priv->psr.dc3co_work);
+ cancel_delayed_work(&intel_dp->psr.dc3co_work);
/* Before PSR2 exit disallow dc3co*/
- tgl_psr2_disable_dc3co(dev_priv);
+ tgl_psr2_disable_dc3co(intel_dp);
}
static void
@@ -714,7 +711,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
- if (!dev_priv->psr.sink_psr2_support)
+ if (!intel_dp->psr.sink_psr2_support)
return false;
if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
@@ -724,7 +721,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
- if (!psr2_global_enabled(dev_priv)) {
+ if (!psr2_global_enabled(intel_dp)) {
drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
return false;
}
@@ -773,10 +770,10 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
* only need to validate the SU block width is a multiple of
* x granularity.
*/
- if (crtc_hdisplay % dev_priv->psr.su_x_granularity) {
+ if (crtc_hdisplay % intel_dp->psr.su_x_granularity) {
drm_dbg_kms(&dev_priv->drm,
"PSR2 not enabled, hdisplay(%d) not multiple of %d\n",
- crtc_hdisplay, dev_priv->psr.su_x_granularity);
+ crtc_hdisplay, intel_dp->psr.su_x_granularity);
return false;
}
@@ -811,13 +808,10 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
&crtc_state->hw.adjusted_mode;
int psr_setup_time;
- if (!CAN_PSR(dev_priv))
- return;
-
- if (intel_dp != dev_priv->psr.dp)
+ if (!CAN_PSR(intel_dp))
return;
- if (!psr_global_enabled(dev_priv)) {
+ if (!psr_global_enabled(intel_dp)) {
drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
return;
}
@@ -834,7 +828,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
- if (dev_priv->psr.sink_not_reliable) {
+ if (intel_dp->psr.sink_not_reliable) {
drm_dbg_kms(&dev_priv->drm,
"PSR sink implementation is not reliable\n");
return;
@@ -870,23 +864,24 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
static void intel_psr_activate(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ enum transcoder transcoder = intel_dp->psr.transcoder;
- if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder))
+ if (transcoder_has_psr2(dev_priv, transcoder))
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
+ intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
- drm_WARN_ON(&dev_priv->drm, dev_priv->psr.active);
- lockdep_assert_held(&dev_priv->psr.lock);
+ intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE);
+ drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
+ lockdep_assert_held(&intel_dp->psr.lock);
/* psr1 and psr2 are mutually exclusive.*/
- if (dev_priv->psr.psr2_enabled)
+ if (intel_dp->psr.psr2_enabled)
hsw_activate_psr2(intel_dp);
else
hsw_activate_psr1(intel_dp);
- dev_priv->psr.active = true;
+ intel_dp->psr.active = true;
}
static void intel_psr_enable_source(struct intel_dp *intel_dp,
@@ -902,7 +897,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
hsw_psr_setup_aux(intel_dp);
- if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
+ if (intel_dp->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv))) {
i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
u32 chicken = intel_de_read(dev_priv, reg);
@@ -926,10 +921,10 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
if (INTEL_GEN(dev_priv) < 11)
mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
- intel_de_write(dev_priv, EDP_PSR_DEBUG(dev_priv->psr.transcoder),
+ intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder),
mask);
- psr_irq_control(dev_priv);
+ psr_irq_control(intel_dp);
if (crtc_state->dc3co_exitline) {
u32 val;
@@ -947,30 +942,30 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
- dev_priv->psr.psr2_sel_fetch_enabled ?
+ intel_dp->psr.psr2_sel_fetch_enabled ?
IGNORE_PSR2_HW_TRACKING : 0);
}
-static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
+static void intel_psr_enable_locked(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- struct intel_dp *intel_dp = dev_priv->psr.dp;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = &dig_port->base;
u32 val;
- drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
+ drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
- dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
- dev_priv->psr.busy_frontbuffer_bits = 0;
- dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
- dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
- dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
+ intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+ intel_dp->psr.busy_frontbuffer_bits = 0;
+ intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+ intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
+ intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
/* DC5/DC6 requires at least 6 idle frames */
val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
- dev_priv->psr.dc3co_exit_delay = val;
- dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
+ intel_dp->psr.dc3co_exit_delay = val;
+ intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
/*
* If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
@@ -982,27 +977,27 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
*/
if (INTEL_GEN(dev_priv) >= 12) {
val = intel_de_read(dev_priv,
- TRANS_PSR_IIR(dev_priv->psr.transcoder));
+ TRANS_PSR_IIR(intel_dp->psr.transcoder));
val &= EDP_PSR_ERROR(0);
} else {
val = intel_de_read(dev_priv, EDP_PSR_IIR);
- val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
+ val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
}
if (val) {
- dev_priv->psr.sink_not_reliable = true;
+ intel_dp->psr.sink_not_reliable = true;
drm_dbg_kms(&dev_priv->drm,
"PSR interruption error set, not enabling PSR\n");
return;
}
drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
- dev_priv->psr.psr2_enabled ? "2" : "1");
+ intel_dp->psr.psr2_enabled ? "2" : "1");
intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
- &dev_priv->psr.vsc);
- intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
+ &intel_dp->psr.vsc);
+ intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp, crtc_state);
- dev_priv->psr.enabled = true;
+ intel_dp->psr.enabled = true;
intel_psr_activate(intel_dp);
}
@@ -1021,7 +1016,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp)
+ if (!CAN_PSR(intel_dp))
return;
if (!crtc_state->has_psr)
@@ -1029,46 +1024,47 @@ void intel_psr_enable(struct intel_dp *intel_dp,
drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
- mutex_lock(&dev_priv->psr.lock);
- intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
- mutex_unlock(&dev_priv->psr.lock);
+ mutex_lock(&intel_dp->psr.lock);
+ intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
+ mutex_unlock(&intel_dp->psr.lock);
}
-static void intel_psr_exit(struct drm_i915_private *dev_priv)
+static void intel_psr_exit(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 val;
- if (!dev_priv->psr.active) {
- if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) {
+ if (!intel_dp->psr.active) {
+ if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) {
val = intel_de_read(dev_priv,
- EDP_PSR2_CTL(dev_priv->psr.transcoder));
+ EDP_PSR2_CTL(intel_dp->psr.transcoder));
drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
}
val = intel_de_read(dev_priv,
- EDP_PSR_CTL(dev_priv->psr.transcoder));
+ EDP_PSR_CTL(intel_dp->psr.transcoder));
drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
return;
}
- if (dev_priv->psr.psr2_enabled) {
- tgl_disallow_dc3co_on_psr2_exit(dev_priv);
+ if (intel_dp->psr.psr2_enabled) {
+ tgl_disallow_dc3co_on_psr2_exit(intel_dp);
val = intel_de_read(dev_priv,
- EDP_PSR2_CTL(dev_priv->psr.transcoder));
+ EDP_PSR2_CTL(intel_dp->psr.transcoder));
drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
val &= ~EDP_PSR2_ENABLE;
intel_de_write(dev_priv,
- EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
+ EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
} else {
val = intel_de_read(dev_priv,
- EDP_PSR_CTL(dev_priv->psr.transcoder));
+ EDP_PSR_CTL(intel_dp->psr.transcoder));
drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
val &= ~EDP_PSR_ENABLE;
intel_de_write(dev_priv,
- EDP_PSR_CTL(dev_priv->psr.transcoder), val);
+ EDP_PSR_CTL(intel_dp->psr.transcoder), val);
}
- dev_priv->psr.active = false;
+ intel_dp->psr.active = false;
}
static void intel_psr_disable_locked(struct intel_dp *intel_dp)
@@ -1077,21 +1073,21 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
i915_reg_t psr_status;
u32 psr_status_mask;
- lockdep_assert_held(&dev_priv->psr.lock);
+ lockdep_assert_held(&intel_dp->psr.lock);
- if (!dev_priv->psr.enabled)
+ if (!intel_dp->psr.enabled)
return;
drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
- dev_priv->psr.psr2_enabled ? "2" : "1");
+ intel_dp->psr.psr2_enabled ? "2" : "1");
- intel_psr_exit(dev_priv);
+ intel_psr_exit(intel_dp);
- if (dev_priv->psr.psr2_enabled) {
- psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
+ if (intel_dp->psr.psr2_enabled) {
+ psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
} else {
- psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder);
+ psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder);
psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
}
@@ -1101,7 +1097,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
/* WA 1408330847 */
- if (dev_priv->psr.psr2_sel_fetch_enabled &&
+ if (intel_dp->psr.psr2_sel_fetch_enabled &&
(IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
@@ -1110,10 +1106,10 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
/* Disable PSR on Sink */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
- if (dev_priv->psr.psr2_enabled)
+ if (intel_dp->psr.psr2_enabled)
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
- dev_priv->psr.enabled = false;
+ intel_dp->psr.enabled = false;
}
/**
@@ -1131,20 +1127,22 @@ void intel_psr_disable(struct intel_dp *intel_dp,
if (!old_crtc_state->has_psr)
return;
- if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv)))
+ if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp)))
return;
- mutex_lock(&dev_priv->psr.lock);
+ mutex_lock(&intel_dp->psr.lock);
intel_psr_disable_locked(intel_dp);
- mutex_unlock(&dev_priv->psr.lock);
- cancel_work_sync(&dev_priv->psr.work);
- cancel_delayed_work_sync(&dev_priv->psr.dc3co_work);
+ mutex_unlock(&intel_dp->psr.lock);
+ cancel_work_sync(&intel_dp->psr.work);
+ cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
}
-static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
+static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
if (IS_TIGERLAKE(dev_priv))
/*
* Writes to CURSURFLIVE in TGL are causing IOMMU errors and
@@ -1158,7 +1156,7 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
* So using this workaround until this issue is root caused
* and a better fix is found.
*/
- intel_psr_exit(dev_priv);
+ intel_psr_exit(intel_dp);
else if (INTEL_GEN(dev_priv) >= 9)
/*
* Display WA #0884: skl+
@@ -1169,13 +1167,13 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
* but it makes more sense write to the current active
* pipe.
*/
- intel_de_write(dev_priv, CURSURFLIVE(dev_priv->psr.pipe), 0);
+ intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
else
/*
* A write to CURSURFLIVE do not cause HW tracking to exit PSR
* on older gens so doing the manual exit instead.
*/
- intel_psr_exit(dev_priv);
+ intel_psr_exit(intel_dp);
}
void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
@@ -1210,11 +1208,11 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
}
-void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
+void intel_psr2_program_trans_man_trk_ctl(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct i915_psr *psr = &dev_priv->psr;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_psr *psr = &intel_dp->psr;
if (!HAS_PSR2_SEL_FETCH(dev_priv) ||
!crtc_state->enable_psr2_sel_fetch)
@@ -1326,13 +1324,13 @@ void intel_psr_update(struct intel_dp *intel_dp,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct i915_psr *psr = &dev_priv->psr;
+ struct intel_psr *psr = &intel_dp->psr;
bool enable, psr2_enable;
- if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp)
+ if (!CAN_PSR(intel_dp))
return;
- mutex_lock(&dev_priv->psr.lock);
+ mutex_lock(&intel_dp->psr.lock);
enable = crtc_state->has_psr;
psr2_enable = crtc_state->has_psr2;
@@ -1340,15 +1338,15 @@ void intel_psr_update(struct intel_dp *intel_dp,
if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
if (crtc_state->crc_enabled && psr->enabled)
- psr_force_hw_tracking_exit(dev_priv);
+ psr_force_hw_tracking_exit(intel_dp);
else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) {
/*
* Activate PSR again after a force exit when enabling
* CRC in older gens
*/
- if (!dev_priv->psr.active &&
- !dev_priv->psr.busy_frontbuffer_bits)
- schedule_work(&dev_priv->psr.work);
+ if (!intel_dp->psr.active &&
+ !intel_dp->psr.busy_frontbuffer_bits)
+ schedule_work(&intel_dp->psr.work);
}
goto unlock;
@@ -1358,34 +1356,23 @@ void intel_psr_update(struct intel_dp *intel_dp,
intel_psr_disable_locked(intel_dp);
if (enable)
- intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
+ intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
unlock:
- mutex_unlock(&dev_priv->psr.lock);
+ mutex_unlock(&intel_dp->psr.lock);
}
/**
- * intel_psr_wait_for_idle - wait for PSR1 to idle
- * @new_crtc_state: new CRTC state
+ * psr_wait_for_idle - wait for PSR1 to idle
+ * @intel_dp: Intel DP
* @out_value: PSR status in case of failure
*
- * This function is expected to be called from pipe_update_start() where it is
- * not expected to race with PSR enable or disable.
- *
* Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
+ *
*/
-int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
- u32 *out_value)
+static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
- if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
- return 0;
-
- /* FIXME: Update this for PSR2 if we need to wait for idle */
- if (READ_ONCE(dev_priv->psr.psr2_enabled))
- return 0;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
/*
* From bspec: Panel Self Refresh (BDW+)
@@ -1393,32 +1380,67 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
* exit training time + 1.5 ms of aux channel handshake. 50 ms is
* defensive enough to cover everything.
*/
-
return __intel_wait_for_register(&dev_priv->uncore,
- EDP_PSR_STATUS(dev_priv->psr.transcoder),
+ EDP_PSR_STATUS(intel_dp->psr.transcoder),
EDP_PSR_STATUS_STATE_MASK,
EDP_PSR_STATUS_STATE_IDLE, 2, 50,
out_value);
}
-static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
+/**
+ * intel_psr_wait_for_idle - wait for PSR1 to idle
+ * @new_crtc_state: new CRTC state
+ *
+ * This function is expected to be called from pipe_update_start() where it is
+ * not expected to race with PSR enable or disable.
+ */
+void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
+ struct intel_encoder *encoder;
+ u32 psr_status;
+
+ if (!new_crtc_state->has_psr)
+ return;
+
+ for_each_intel_dp(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ if (encoder->type != INTEL_OUTPUT_EDP)
+ continue;
+
+ /* when the PSR1 is enabled */
+ if (intel_dp->psr.enabled && !intel_dp->psr.psr2_enabled) {
+ if (psr_wait_for_idle(intel_dp, &psr_status))
+ drm_err(&dev_priv->drm,
+ "PSR idle timed out 0x%x, atomic update may fail\n",
+ psr_status);
+
+ /* only one trancoder can enable PSR1 */
+ break;
+ }
+ }
+}
+
+static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
{
i915_reg_t reg;
u32 mask;
int err;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (!dev_priv->psr.enabled)
+ if (!intel_dp->psr.enabled)
return false;
- if (dev_priv->psr.psr2_enabled) {
- reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
+ if (intel_dp->psr.psr2_enabled) {
+ reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
mask = EDP_PSR2_STATUS_STATE_MASK;
} else {
- reg = EDP_PSR_STATUS(dev_priv->psr.transcoder);
+ reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);
mask = EDP_PSR_STATUS_STATE_MASK;
}
- mutex_unlock(&dev_priv->psr.lock);
+ mutex_unlock(&intel_dp->psr.lock);
err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
if (err)
@@ -1426,8 +1448,8 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
"Timed out waiting for PSR Idle for re-enable\n");
/* After the unlocked wait, verify that PSR is still wanted! */
- mutex_lock(&dev_priv->psr.lock);
- return err == 0 && dev_priv->psr.enabled;
+ mutex_lock(&intel_dp->psr.lock);
+ return err == 0 && intel_dp->psr.enabled;
}
static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
@@ -1493,11 +1515,12 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
return err;
}
-int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
+int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
{
const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
u32 old_mode;
int ret;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
mode > I915_PSR_DEBUG_FORCE_PSR1) {
@@ -1505,21 +1528,21 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
return -EINVAL;
}
- ret = mutex_lock_interruptible(&dev_priv->psr.lock);
+ ret = mutex_lock_interruptible(&intel_dp->psr.lock);
if (ret)
return ret;
- old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
- dev_priv->psr.debug = val;
+ old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
+ intel_dp->psr.debug = val;
/*
* Do it right away if it's already enabled, otherwise it will be done
* when enabling the source.
*/
- if (dev_priv->psr.enabled)
- psr_irq_control(dev_priv);
+ if (intel_dp->psr.enabled)
+ psr_irq_control(intel_dp);
- mutex_unlock(&dev_priv->psr.lock);
+ mutex_unlock(&intel_dp->psr.lock);
if (old_mode != mode)
ret = intel_psr_fastset_force(dev_priv);
@@ -1527,28 +1550,28 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
return ret;
}
-static void intel_psr_handle_irq(struct drm_i915_private *dev_priv)
+static void intel_psr_handle_irq(struct intel_dp *intel_dp)
{
- struct i915_psr *psr = &dev_priv->psr;
+ struct intel_psr *psr = &intel_dp->psr;
- intel_psr_disable_locked(psr->dp);
+ intel_psr_disable_locked(intel_dp);
psr->sink_not_reliable = true;
/* let's make sure that sink is awaken */
- drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
}
static void intel_psr_work(struct work_struct *work)
{
- struct drm_i915_private *dev_priv =
- container_of(work, typeof(*dev_priv), psr.work);
+ struct intel_dp *intel_dp =
+ container_of(work, typeof(*intel_dp), psr.work);
- mutex_lock(&dev_priv->psr.lock);
+ mutex_lock(&intel_dp->psr.lock);
- if (!dev_priv->psr.enabled)
+ if (!intel_dp->psr.enabled)
goto unlock;
- if (READ_ONCE(dev_priv->psr.irq_aux_error))
- intel_psr_handle_irq(dev_priv);
+ if (READ_ONCE(intel_dp->psr.irq_aux_error))
+ intel_psr_handle_irq(intel_dp);
/*
* We have to make sure PSR is ready for re-enable
@@ -1556,7 +1579,7 @@ static void intel_psr_work(struct work_struct *work)
* PSR might take some time to get fully disabled
* and be ready for re-enable.
*/
- if (!__psr_wait_for_idle_locked(dev_priv))
+ if (!__psr_wait_for_idle_locked(intel_dp))
goto unlock;
/*
@@ -1564,12 +1587,12 @@ static void intel_psr_work(struct work_struct *work)
* recheck. Since psr_flush first clears this and then reschedules we
* won't ever miss a flush when bailing out here.
*/
- if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active)
+ if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
goto unlock;
- intel_psr_activate(dev_priv->psr.dp);
+ intel_psr_activate(intel_dp);
unlock:
- mutex_unlock(&dev_priv->psr.lock);
+ mutex_unlock(&intel_dp->psr.lock);
}
/**
@@ -1588,27 +1611,35 @@ static void intel_psr_work(struct work_struct *work)
void intel_psr_invalidate(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits, enum fb_op_origin origin)
{
- if (!CAN_PSR(dev_priv))
- return;
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp;
- if (origin == ORIGIN_FLIP)
- return;
+ for_each_intel_dp(&dev_priv->drm, encoder) {
- mutex_lock(&dev_priv->psr.lock);
- if (!dev_priv->psr.enabled) {
- mutex_unlock(&dev_priv->psr.lock);
- return;
- }
+ intel_dp = enc_to_intel_dp(encoder);
+ if (encoder->type != INTEL_OUTPUT_EDP)
+ continue;
+ if (!CAN_PSR(intel_dp))
+ continue;
+
+ if (origin == ORIGIN_FLIP)
+ continue;
- frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
- dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
+ mutex_lock(&intel_dp->psr.lock);
+ if (!intel_dp->psr.enabled) {
+ mutex_unlock(&intel_dp->psr.lock);
+ continue;
+ }
- if (frontbuffer_bits)
- intel_psr_exit(dev_priv);
+ frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
+ intel_dp->psr.busy_frontbuffer_bits |= frontbuffer_bits;
- mutex_unlock(&dev_priv->psr.lock);
-}
+ if (frontbuffer_bits)
+ intel_psr_exit(intel_dp);
+ mutex_unlock(&intel_dp->psr.lock);
+ }
+}
/*
* When we will be completely rely on PSR2 S/W tracking in future,
* intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
@@ -1616,15 +1647,15 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv,
* accordingly in future.
*/
static void
-tgl_dc3co_flush(struct drm_i915_private *dev_priv,
- unsigned int frontbuffer_bits, enum fb_op_origin origin)
+tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
+ enum fb_op_origin origin)
{
- mutex_lock(&dev_priv->psr.lock);
+ mutex_lock(&intel_dp->psr.lock);
- if (!dev_priv->psr.dc3co_enabled)
+ if (!intel_dp->psr.dc3co_enabled)
goto unlock;
- if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active)
+ if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
goto unlock;
/*
@@ -1632,15 +1663,15 @@ tgl_dc3co_flush(struct drm_i915_private *dev_priv,
* when delayed work schedules that means display has been idle.
*/
if (!(frontbuffer_bits &
- INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe)))
+ INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
goto unlock;
- tgl_psr2_enable_dc3co(dev_priv);
- mod_delayed_work(system_wq, &dev_priv->psr.dc3co_work,
- dev_priv->psr.dc3co_exit_delay);
+ tgl_psr2_enable_dc3co(intel_dp);
+ mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work,
+ intel_dp->psr.dc3co_exit_delay);
unlock:
- mutex_unlock(&dev_priv->psr.lock);
+ mutex_unlock(&intel_dp->psr.lock);
}
/**
@@ -1659,45 +1690,54 @@ tgl_dc3co_flush(struct drm_i915_private *dev_priv,
void intel_psr_flush(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits, enum fb_op_origin origin)
{
- if (!CAN_PSR(dev_priv))
- return;
-
- if (origin == ORIGIN_FLIP) {
- tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin);
- return;
- }
-
- mutex_lock(&dev_priv->psr.lock);
- if (!dev_priv->psr.enabled) {
- mutex_unlock(&dev_priv->psr.lock);
- return;
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp;
+
+ for_each_intel_dp(&dev_priv->drm, encoder) {
+ intel_dp = enc_to_intel_dp(encoder);
+
+ if (encoder->type == INTEL_OUTPUT_EDP && CAN_PSR(intel_dp)) {
+ if (origin == ORIGIN_FLIP) {
+ tgl_dc3co_flush(intel_dp, frontbuffer_bits, origin);
+ continue;
+ }
+
+ mutex_lock(&intel_dp->psr.lock);
+ if (!intel_dp->psr.enabled) {
+ mutex_unlock(&intel_dp->psr.lock);
+ continue;
+ }
+
+ frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
+ intel_dp->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
+
+ /* By definition flush = invalidate + flush */
+ if (frontbuffer_bits)
+ psr_force_hw_tracking_exit(intel_dp);
+
+ if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
+ schedule_work(&intel_dp->psr.work);
+ mutex_unlock(&intel_dp->psr.lock);
+ }
}
-
- frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
- dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
-
- /* By definition flush = invalidate + flush */
- if (frontbuffer_bits)
- psr_force_hw_tracking_exit(dev_priv);
-
- if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
- schedule_work(&dev_priv->psr.work);
- mutex_unlock(&dev_priv->psr.lock);
}
/**
* intel_psr_init - Init basic PSR work and mutex.
- * @dev_priv: i915 device private
+ * @intel_dp: Intel DP
*
- * This function is called only once at driver load to initialize basic
- * PSR stuff.
+ * This function is called after the initializing connector.
+ * (the initializing of connector treats the handling of connector capabilities)
+ * And it initializes basic PSR stuff for each DP Encoder.
*/
-void intel_psr_init(struct drm_i915_private *dev_priv)
+void intel_psr_init(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
if (!HAS_PSR(dev_priv))
return;
- if (!dev_priv->psr.sink_support)
+ if (!intel_dp->psr.sink_support)
return;
if (IS_HASWELL(dev_priv))
@@ -1715,14 +1755,14 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
/* Set link_standby x link_off defaults */
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
/* HSW and BDW require workarounds that we don't implement. */
- dev_priv->psr.link_standby = false;
+ intel_dp->psr.link_standby = false;
else if (INTEL_GEN(dev_priv) < 12)
/* For new platforms up to TGL let's respect VBT back again */
- dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
+ intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link;
- INIT_WORK(&dev_priv->psr.work, intel_psr_work);
- INIT_DELAYED_WORK(&dev_priv->psr.dc3co_work, tgl_dc3co_disable_work);
- mutex_init(&dev_priv->psr.lock);
+ INIT_WORK(&intel_dp->psr.work, intel_psr_work);
+ INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
+ mutex_init(&intel_dp->psr.lock);
}
static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
@@ -1748,7 +1788,7 @@ static void psr_alpm_check(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct drm_dp_aux *aux = &intel_dp->aux;
- struct i915_psr *psr = &dev_priv->psr;
+ struct intel_psr *psr = &intel_dp->psr;
u8 val;
int r;
@@ -1775,7 +1815,7 @@ static void psr_alpm_check(struct intel_dp *intel_dp)
static void psr_capability_changed_check(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct i915_psr *psr = &dev_priv->psr;
+ struct intel_psr *psr = &intel_dp->psr;
u8 val;
int r;
@@ -1799,18 +1839,18 @@ static void psr_capability_changed_check(struct intel_dp *intel_dp)
void intel_psr_short_pulse(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct i915_psr *psr = &dev_priv->psr;
+ struct intel_psr *psr = &intel_dp->psr;
u8 status, error_status;
const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
DP_PSR_LINK_CRC_ERROR;
- if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
+ if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp))
return;
mutex_lock(&psr->lock);
- if (!psr->enabled || psr->dp != intel_dp)
+ if (!psr->enabled)
goto exit;
if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
@@ -1853,15 +1893,14 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
bool intel_psr_enabled(struct intel_dp *intel_dp)
{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
bool ret;
- if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
+ if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp))
return false;
- mutex_lock(&dev_priv->psr.lock);
- ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled);
- mutex_unlock(&dev_priv->psr.lock);
+ mutex_lock(&intel_dp->psr.lock);
+ ret = intel_dp->psr.enabled;
+ mutex_unlock(&intel_dp->psr.lock);
return ret;
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 0a517978e8af..03eb19547d09 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -18,7 +18,7 @@ struct intel_atomic_state;
struct intel_plane_state;
struct intel_plane;
-#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
+#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && intel_dp->psr.sink_support)
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
void intel_psr_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
@@ -28,24 +28,24 @@ void intel_psr_disable(struct intel_dp *intel_dp,
void intel_psr_update(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
-int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);
+int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);
void intel_psr_invalidate(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits,
enum fb_op_origin origin);
void intel_psr_flush(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits,
enum fb_op_origin origin);
-void intel_psr_init(struct drm_i915_private *dev_priv);
+void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state);
-void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
+void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
void intel_psr_short_pulse(struct intel_dp *intel_dp);
-int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
- u32 *out_value);
+void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
bool intel_psr_enabled(struct intel_dp *intel_dp);
int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
-void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state);
+void intel_psr2_program_trans_man_trk_ctl(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index b6deeb338477..ccd86f168357 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -92,7 +92,6 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
DEFINE_WAIT(wait);
- u32 psr_status;
if (new_crtc_state->uapi.async_flip)
return;
@@ -117,10 +116,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
* VBL interrupts will start the PSR exit and prevent a PSR
* re-entry as well.
*/
- if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
- drm_err(&dev_priv->drm,
- "PSR idle timed out 0x%x, atomic update may fail\n",
- psr_status);
+ intel_psr_wait_for_idle(new_crtc_state);
local_irq_disable();
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 15be8debae54..5a40295260c2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -475,42 +475,6 @@ struct i915_drrs {
enum drrs_support_type type;
};
-struct i915_psr {
- struct mutex lock;
-
-#define I915_PSR_DEBUG_MODE_MASK 0x0f
-#define I915_PSR_DEBUG_DEFAULT 0x00
-#define I915_PSR_DEBUG_DISABLE 0x01
-#define I915_PSR_DEBUG_ENABLE 0x02
-#define I915_PSR_DEBUG_FORCE_PSR1 0x03
-#define I915_PSR_DEBUG_IRQ 0x10
-
- u32 debug;
- bool sink_support;
- bool enabled;
- struct intel_dp *dp;
- enum pipe pipe;
- enum transcoder transcoder;
- bool active;
- struct work_struct work;
- unsigned busy_frontbuffer_bits;
- bool sink_psr2_support;
- bool link_standby;
- bool colorimetry_support;
- bool psr2_enabled;
- bool psr2_sel_fetch_enabled;
- u8 sink_sync_latency;
- ktime_t last_entry_attempt;
- ktime_t last_exit;
- bool sink_not_reliable;
- bool irq_aux_error;
- u16 su_x_granularity;
- bool dc3co_enabled;
- u32 dc3co_exit_delay;
- struct delayed_work dc3co_work;
- struct drm_dp_vsc_sdp vsc;
-};
-
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
@@ -1041,8 +1005,6 @@ struct drm_i915_private {
struct i915_power_domains power_domains;
- struct i915_psr psr;
-
struct i915_gpu_error gpu_error;
struct drm_i915_gem_object *vlv_pctx;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e0eb32bd9607..6d43298c46dd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2057,10 +2057,20 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
ivb_err_int_handler(dev_priv);
if (de_iir & DE_EDP_PSR_INT_HSW) {
- u32 psr_iir = I915_READ(EDP_PSR_IIR);
+ struct intel_encoder *encoder;
- intel_psr_irq_handler(dev_priv, psr_iir);
- I915_WRITE(EDP_PSR_IIR, psr_iir);
+ for_each_intel_dp(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ if (encoder->type == INTEL_OUTPUT_EDP &&
+ CAN_PSR(intel_dp)) {
+ u32 psr_iir = I915_READ(EDP_PSR_IIR);
+
+ intel_psr_irq_handler(intel_dp, psr_iir);
+ I915_WRITE(EDP_PSR_IIR, psr_iir);
+ break;
+ }
+ }
}
if (de_iir & DE_AUX_CHANNEL_A_IVB)
@@ -2268,21 +2278,34 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
}
if (iir & GEN8_DE_EDP_PSR) {
+ struct intel_encoder *encoder;
u32 psr_iir;
i915_reg_t iir_reg;
- if (INTEL_GEN(dev_priv) >= 12)
- iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder);
- else
- iir_reg = EDP_PSR_IIR;
+ for_each_intel_dp(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- psr_iir = I915_READ(iir_reg);
- I915_WRITE(iir_reg, psr_iir);
+ if (INTEL_GEN(dev_priv) >= 12 && CAN_PSR(intel_dp)) {
+ iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder);
+ } else if (encoder->type == INTEL_OUTPUT_EDP &&
+ CAN_PSR(intel_dp)) {
+ iir_reg = EDP_PSR_IIR;
+ } else {
+ continue;
+ }
+
+ psr_iir = I915_READ(iir_reg);
+ I915_WRITE(iir_reg, psr_iir);
+
+ if (psr_iir)
+ found = true;
- if (psr_iir)
- found = true;
+ intel_psr_irq_handler(intel_dp, psr_iir);
- intel_psr_irq_handler(dev_priv, psr_iir);
+ /* prior GEN12 only have one EDP PSR */
+ if (INTEL_GEN(dev_priv) < 12)
+ break;
+ }
}
if (!found)
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
2020-11-06 10:14 [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Gwan-gyeong Mun
@ 2020-11-06 10:14 ` Gwan-gyeong Mun
2020-11-18 11:11 ` Jani Nikula
2020-11-18 11:12 ` Jani Nikula
2020-11-06 12:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders Patchwork
` (8 subsequent siblings)
9 siblings, 2 replies; 17+ messages in thread
From: Gwan-gyeong Mun @ 2020-11-06 10:14 UTC (permalink / raw)
To: intel-gfx
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 8402e6ac9f76..37805615a221 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2093,6 +2093,23 @@ static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_psr_status_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_dp *intel_dp =
+ intel_attached_dp(to_intel_connector(connector));
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (connector->status != connector_status_connected)
+ return -ENODEV;
+
+ if (!HAS_PSR(dev_priv))
+ return -ENODEV;
+
+ return intel_psr_status(m, intel_dp);
+}
+DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
+
#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
seq_puts(m, "LPSP: incapable\n"))
@@ -2268,6 +2285,12 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
connector, &i915_psr_sink_status_fops);
}
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ debugfs_create_file("i915_psr_status", 0444, root,
+ connector, &i915_psr_status_fops);
+ }
+
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders
2020-11-06 10:14 [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Gwan-gyeong Mun
2020-11-06 10:14 ` [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs Gwan-gyeong Mun
@ 2020-11-06 12:12 ` Patchwork
2020-11-06 12:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (7 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-11-06 12:12 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders
URL : https://patchwork.freedesktop.org/series/83577/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
389cbe50c345 drm/i915/display: Support PSR Multiple Transcoders
-:1710: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects?
#1710: FILE: drivers/gpu/drm/i915/display/intel_psr.h:21:
+#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && intel_dp->psr.sink_support)
total: 0 errors, 0 warnings, 1 checks, 1743 lines checked
3c1636027258 drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders
2020-11-06 10:14 [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Gwan-gyeong Mun
2020-11-06 10:14 ` [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs Gwan-gyeong Mun
2020-11-06 12:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders Patchwork
@ 2020-11-06 12:14 ` Patchwork
2020-11-06 12:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (6 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-11-06 12:14 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders
URL : https://patchwork.freedesktop.org/series/83577/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders
2020-11-06 10:14 [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Gwan-gyeong Mun
` (2 preceding siblings ...)
2020-11-06 12:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-11-06 12:40 ` Patchwork
2020-11-06 15:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (5 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-11-06 12:40 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
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== Series Details ==
Series: series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders
URL : https://patchwork.freedesktop.org/series/83577/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9281 -> Patchwork_18866
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/index.html
New tests
---------
New tests have been introduced between CI_DRM_9281 and Patchwork_18866:
### New CI tests (1) ###
* boot:
- Statuses : 39 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18866 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_busy@basic@flip:
- fi-kbl-soraka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/fi-kbl-soraka/igt@kms_busy@basic@flip.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/fi-kbl-soraka/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-skl-lmem: [DMESG-WARN][9] ([i915#2605]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/fi-skl-lmem/igt@i915_module_load@reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/fi-skl-lmem/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gt_timelines:
- fi-apl-guc: [INCOMPLETE][13] ([i915#1635]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
Participating hosts (42 -> 39)
------------------------------
Missing (3): fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9281 -> Patchwork_18866
CI-20190529: 20190529
CI_DRM_9281: f88cfb4c62df91cd9024854d8739c5257e4b6a55 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5836: 4c2ec0ad123b82f42f9fe2297e1a41fec73c9229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18866: 3c163602725810f5d363680af2e11756e58affac @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3c1636027258 drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
389cbe50c345 drm/i915/display: Support PSR Multiple Transcoders
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders
2020-11-06 10:14 [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Gwan-gyeong Mun
` (3 preceding siblings ...)
2020-11-06 12:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-11-06 15:13 ` Patchwork
2020-11-10 19:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders (rev2) Patchwork
` (4 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-11-06 15:13 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 20633 bytes --]
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders
URL : https://patchwork.freedesktop.org/series/83577/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9281_full -> Patchwork_18866_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18866_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18866_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18866_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-iclb7/igt@gem_exec_whisper@basic-queues-forked-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-iclb8/igt@gem_exec_whisper@basic-queues-forked-all.html
* igt@perf_pmu@most-busy-idle-check-all@vcs0:
- shard-snb: [PASS][3] -> [FAIL][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-snb2/igt@perf_pmu@most-busy-idle-check-all@vcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-snb5/igt@perf_pmu@most-busy-idle-check-all@vcs0.html
New tests
---------
New tests have been introduced between CI_DRM_9281_full and Patchwork_18866_full:
### New CI tests (1) ###
* boot:
- Statuses : 174 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18866_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_exec_whisper@basic-normal-all:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-glk1/igt@gem_exec_whisper@basic-normal-all.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-glk7/igt@gem_exec_whisper@basic-normal-all.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge:
- shard-tglb: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-tglb3/igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-tglb1/igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2346])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-tglb1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#2346])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#52] / [i915#54])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-skl3/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-skl2/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled.html
* igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-iclb2/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-iclb5/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-tglb: [PASS][19] -> [FAIL][20] ([i915#2598])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-tglb6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#1635] / [i915#1982]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a1:
- shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-glk5/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-glk3/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#49])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-glk4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-glk4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render:
- shard-skl: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +9 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][29] -> [FAIL][30] ([i915#1188])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-skl7/igt@kms_hdr@bpc-switch.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-skl7/igt@kms_hdr@bpc-switch.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-snb: [PASS][31] -> [DMESG-WARN][32] ([i915#42])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-snb7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-snb7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-a:
- shard-kbl: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-kbl2/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-kbl6/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: [PASS][39] -> [INCOMPLETE][40] ([i915#198])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-skl1/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-skl9/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@sysfs_heartbeat_interval@mixed@vcs0:
- shard-kbl: [PASS][41] -> [INCOMPLETE][42] ([i915#1731])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-kbl7/igt@sysfs_heartbeat_interval@mixed@vcs0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-kbl4/igt@sysfs_heartbeat_interval@mixed@vcs0.html
#### Possible fixes ####
* igt@core_hotunplug@hotunbind-rebind:
- shard-iclb: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-iclb4/igt@core_hotunplug@hotunbind-rebind.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-iclb4/igt@core_hotunplug@hotunbind-rebind.html
* igt@gem_eio@unwedge-stress:
- shard-skl: [FAIL][45] -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-skl4/igt@gem_eio@unwedge-stress.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-skl5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_store@dword@vecs0:
- shard-skl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-skl9/igt@gem_exec_store@dword@vecs0.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-skl8/igt@gem_exec_store@dword@vecs0.html
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-tglb: [INCOMPLETE][49] -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-tglb2/igt@gem_ppgtt@blt-vs-render-ctx0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-tglb3/igt@gem_ppgtt@blt-vs-render-ctx0.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [INCOMPLETE][51] ([i915#82]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-snb2/igt@gem_userptr_blits@sync-unmap-cycles.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-snb2/igt@gem_userptr_blits@sync-unmap-cycles.html
* {igt@kms_async_flips@alternate-sync-async-flip}:
- shard-kbl: [FAIL][53] ([i915#2521]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-kbl3/igt@kms_async_flips@alternate-sync-async-flip.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-kbl6/igt@kms_async_flips@alternate-sync-async-flip.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-glk: [FAIL][55] ([i915#2521]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-glk3/igt@kms_async_flips@async-flip-with-page-flip-events.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-glk1/igt@kms_async_flips@async-flip-with-page-flip-events.html
- shard-apl: [FAIL][57] ([i915#1635] / [i915#2521]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-apl7/igt@kms_async_flips@async-flip-with-page-flip-events.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-apl6/igt@kms_async_flips@async-flip-with-page-flip-events.html
* {igt@kms_async_flips@test-time-stamp}:
- shard-tglb: [FAIL][59] ([i915#2597]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-tglb6/igt@kms_async_flips@test-time-stamp.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-tglb8/igt@kms_async_flips@test-time-stamp.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
- shard-skl: [FAIL][61] ([i915#54]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
* igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge:
- shard-tglb: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-tglb3/igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-tglb1/igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-glk: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-glk7/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-glk2/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [FAIL][67] ([i915#2598]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-tglb2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-WARN][69] ([i915#180]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][71] ([fdo#108145] / [i915#265]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][73] ([fdo#109642] / [fdo#111068]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][75] ([fdo#109441]) -> [PASS][76] +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-a:
- shard-apl: [DMESG-WARN][77] ([i915#1635] / [i915#1982]) -> [PASS][78] +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-apl1/igt@kms_universal_plane@disable-primary-vs-flip-pipe-a.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-apl4/igt@kms_universal_plane@disable-primary-vs-flip-pipe-a.html
* igt@kms_vblank@pipe-c-wait-busy:
- shard-kbl: [DMESG-WARN][79] ([i915#1982]) -> [PASS][80] +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-kbl1/igt@kms_vblank@pipe-c-wait-busy.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-kbl2/igt@kms_vblank@pipe-c-wait-busy.html
* igt@perf@polling-parameterized:
- shard-glk: [FAIL][81] ([i915#1542]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-glk4/igt@perf@polling-parameterized.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-glk4/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-glk: [SKIP][83] ([fdo#109271] / [i915#658]) -> [SKIP][84] ([fdo#109271])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-glk9/igt@i915_pm_dc@dc3co-vpb-simulation.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-glk5/igt@i915_pm_dc@dc3co-vpb-simulation.html
- shard-apl: [SKIP][85] ([fdo#109271] / [i915#1635] / [i915#658]) -> [SKIP][86] ([fdo#109271] / [i915#1635])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-apl6/igt@i915_pm_dc@dc3co-vpb-simulation.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-apl3/igt@i915_pm_dc@dc3co-vpb-simulation.html
- shard-kbl: [SKIP][87] ([fdo#109271] / [i915#658]) -> [SKIP][88] ([fdo#109271])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-kbl1/igt@i915_pm_dc@dc3co-vpb-simulation.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-kbl1/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [DMESG-FAIL][89] ([i915#1982]) -> [DMESG-WARN][90] ([i915#1982])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9281/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2597]: https://gitlab.freedesktop.org/drm/intel/issues/2597
[i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9281 -> Patchwork_18866
CI-20190529: 20190529
CI_DRM_9281: f88cfb4c62df91cd9024854d8739c5257e4b6a55 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5836: 4c2ec0ad123b82f42f9fe2297e1a41fec73c9229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18866: 3c163602725810f5d363680af2e11756e58affac @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18866/index.html
[-- Attachment #1.2: Type: text/html, Size: 24582 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders (rev2)
2020-11-06 10:14 [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Gwan-gyeong Mun
` (4 preceding siblings ...)
2020-11-06 15:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-11-10 19:52 ` Patchwork
2020-11-10 19:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-11-10 19:52 UTC (permalink / raw)
To: Mun, Gwan-gyeong; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders (rev2)
URL : https://patchwork.freedesktop.org/series/83577/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b591a9c76336 drm/i915/display: Support PSR Multiple Transcoders
-:1710: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects?
#1710: FILE: drivers/gpu/drm/i915/display/intel_psr.h:21:
+#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && intel_dp->psr.sink_support)
total: 0 errors, 0 warnings, 1 checks, 1743 lines checked
78b61540ef10 drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders (rev2)
2020-11-06 10:14 [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Gwan-gyeong Mun
` (5 preceding siblings ...)
2020-11-10 19:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders (rev2) Patchwork
@ 2020-11-10 19:53 ` Patchwork
2020-11-10 20:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-11-10 19:53 UTC (permalink / raw)
To: Mun, Gwan-gyeong; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders (rev2)
URL : https://patchwork.freedesktop.org/series/83577/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders (rev2)
2020-11-06 10:14 [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Gwan-gyeong Mun
` (6 preceding siblings ...)
2020-11-10 19:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-11-10 20:22 ` Patchwork
2020-11-10 23:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-12-04 16:38 ` [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Anshuman Gupta
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-11-10 20:22 UTC (permalink / raw)
To: Mun, Gwan-gyeong; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 8599 bytes --]
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders (rev2)
URL : https://patchwork.freedesktop.org/series/83577/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9304 -> Patchwork_18875
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18875:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@primary_mmap_gtt:
- {fi-tgl-dsi}: [SKIP][1] ([fdo#110189]) -> [SKIP][2] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
New tests
---------
New tests have been introduced between CI_DRM_9304 and Patchwork_18875:
### New CI tests (1) ###
* boot:
- Statuses : 42 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18875 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@gem_mmap_gtt@basic:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-tgl-y/igt@gem_mmap_gtt@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-tgl-y/igt@gem_mmap_gtt@basic.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-n3050: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-bsw-n3050: [PASS][9] -> [DMESG-FAIL][10] ([i915#541])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-bsw-n3050/igt@i915_selftest@live@gt_heartbeat.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-bsw-n3050/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_busy@basic@flip:
- fi-kbl-soraka: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-kbl-soraka/igt@kms_busy@basic@flip.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-kbl-soraka/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-snb-2520m: [PASS][15] -> [DMESG-WARN][16] ([i915#1982])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-snb-2520m/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-snb-2520m/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@i915_module_load@reload:
- {fi-tgl-dsi}: [DMESG-WARN][19] ([i915#1982] / [k.org#205379]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-tgl-dsi/igt@i915_module_load@reload.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-tgl-dsi/igt@i915_module_load@reload.html
- fi-kbl-soraka: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-kbl-soraka/igt@i915_module_load@reload.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-kbl-soraka/igt@i915_module_load@reload.html
- fi-tgl-u2: [DMESG-WARN][23] ([i915#1982] / [k.org#205379]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-tgl-u2/igt@i915_module_load@reload.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-tgl-u2/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-glk-dsi: [DMESG-WARN][25] ([i915#1982]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-glk-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-glk-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_busy@basic@flip:
- {fi-tgl-dsi}: [DMESG-WARN][27] ([i915#1982]) -> [PASS][28] +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-tgl-dsi/igt@kms_busy@basic@flip.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-tgl-dsi/igt@kms_busy@basic@flip.html
- fi-tgl-y: [DMESG-WARN][29] ([i915#1982]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-tgl-y/igt@kms_busy@basic@flip.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-tgl-y/igt@kms_busy@basic@flip.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [DMESG-WARN][31] ([i915#402]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [DMESG-WARN][33] ([i915#2411]) -> [DMESG-WARN][34] ([i915#2411] / [i915#402])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-tgl-y: [DMESG-WARN][35] ([i915#1982] / [i915#2411]) -> [DMESG-WARN][36] ([i915#2411])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/fi-tgl-y/igt@i915_pm_rpm@basic-pci-d3-state.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/fi-tgl-y/igt@i915_pm_rpm@basic-pci-d3-state.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (47 -> 42)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9304 -> Patchwork_18875
CI-20190529: 20190529
CI_DRM_9304: dd49914f9e07f649be2e23beefe3248b0f5d617c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5845: 48bf21fabbf7a5d8a9458fe449394f190c3f2331 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18875: 78b61540ef10f963f9c4caadfbcbef8223c62eba @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
78b61540ef10 drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
b591a9c76336 drm/i915/display: Support PSR Multiple Transcoders
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/index.html
[-- Attachment #1.2: Type: text/html, Size: 10863 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders (rev2)
2020-11-06 10:14 [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Gwan-gyeong Mun
` (7 preceding siblings ...)
2020-11-10 20:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-11-10 23:22 ` Patchwork
2020-12-04 16:38 ` [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Anshuman Gupta
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-11-10 23:22 UTC (permalink / raw)
To: Mun, Gwan-gyeong; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 21166 bytes --]
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders (rev2)
URL : https://patchwork.freedesktop.org/series/83577/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9304_full -> Patchwork_18875_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18875_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18875_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18875_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_schedule@pi-userfault@vcs0:
- shard-iclb: NOTRUN -> [FAIL][1] +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-iclb4/igt@gem_exec_schedule@pi-userfault@vcs0.html
* igt@gem_exec_whisper@basic-normal:
- shard-hsw: [PASS][2] -> [FAIL][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-hsw4/igt@gem_exec_whisper@basic-normal.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-hsw2/igt@gem_exec_whisper@basic-normal.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1:
- shard-hsw: [PASS][4] -> [INCOMPLETE][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-hsw1/igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-hsw7/igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1.html
New tests
---------
New tests have been introduced between CI_DRM_9304_full and Patchwork_18875_full:
### New CI tests (1) ###
* boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18875_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][6] -> [DMESG-WARN][7] ([i915#1436] / [i915#716])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl2/igt@gen9_exec_parse@allowed-single.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl4/igt@gen9_exec_parse@allowed-single.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-random:
- shard-skl: [PASS][8] -> [FAIL][9] ([i915#54]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
* igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge:
- shard-hsw: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-hsw6/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-hsw6/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-apl: [PASS][12] -> [DMESG-WARN][13] ([i915#1635] / [i915#1982]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][14] -> [FAIL][15] ([i915#79]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [PASS][16] -> [FAIL][17] ([i915#2122])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl1/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
- shard-kbl: [PASS][18] -> [DMESG-WARN][19] ([i915#1982]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-tglb: [PASS][20] -> [DMESG-WARN][21] ([i915#1982])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-tglb5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-skl: [PASS][22] -> [DMESG-WARN][23] ([i915#1982]) +7 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-skl: [PASS][24] -> [INCOMPLETE][25] ([i915#648])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][26] -> [FAIL][27] ([fdo#108145] / [i915#265])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][28] -> [SKIP][29] ([fdo#109441]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][30] -> [FAIL][31] ([i915#1542])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl7/igt@perf@polling-parameterized.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl10/igt@perf@polling-parameterized.html
#### Possible fixes ####
* igt@core_hotunplug@hotrebind-lateclose:
- shard-snb: [INCOMPLETE][32] -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-snb2/igt@core_hotunplug@hotrebind-lateclose.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-snb2/igt@core_hotunplug@hotrebind-lateclose.html
* igt@gem_exec_whisper@basic-contexts-all:
- shard-glk: [DMESG-WARN][34] ([i915#118] / [i915#95]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-glk5/igt@gem_exec_whisper@basic-contexts-all.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-glk4/igt@gem_exec_whisper@basic-contexts-all.html
* igt@gem_exec_whisper@basic-normal:
- shard-glk: [FAIL][36] -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-glk9/igt@gem_exec_whisper@basic-normal.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-glk4/igt@gem_exec_whisper@basic-normal.html
* igt@gem_workarounds@suspend-resume-context:
- shard-skl: [INCOMPLETE][38] ([i915#198]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl3/igt@gem_workarounds@suspend-resume-context.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl5/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_module_load@reload:
- shard-iclb: [DMESG-WARN][40] ([i915#1982]) -> [PASS][41] +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-iclb1/igt@i915_module_load@reload.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-iclb2/igt@i915_module_load@reload.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-hsw: [WARN][42] ([i915#1519]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-hsw6/igt@i915_pm_rc6_residency@rc6-fence.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-hsw6/igt@i915_pm_rc6_residency@rc6-fence.html
* {igt@kms_async_flips@test-time-stamp}:
- shard-tglb: [FAIL][44] ([i915#2597]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-tglb3/igt@kms_async_flips@test-time-stamp.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-tglb6/igt@kms_async_flips@test-time-stamp.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-180:
- shard-skl: [DMESG-WARN][46] ([i915#1982]) -> [PASS][47] +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl6/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl6/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-0:
- shard-kbl: [DMESG-WARN][48] ([i915#1982]) -> [PASS][49] +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-kbl4/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-kbl2/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html
* igt@kms_color@pipe-b-degamma:
- shard-skl: [FAIL][50] ([i915#71]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl7/igt@kms_color@pipe-b-degamma.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl6/igt@kms_color@pipe-b-degamma.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-random:
- shard-skl: [FAIL][52] ([i915#54]) -> [PASS][53] +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][54] ([i915#96]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [FAIL][56] ([i915#2598]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-tglb2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-tglb2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-tglb: [DMESG-WARN][58] ([i915#1982]) -> [PASS][59] +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][60] ([fdo#108145] / [i915#265]) -> [PASS][61] +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][62] ([fdo#109441]) -> [PASS][63] +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@perf_pmu@module-unload:
- shard-apl: [DMESG-WARN][64] ([i915#1635] / [i915#1982]) -> [PASS][65] +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-apl7/igt@perf_pmu@module-unload.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-apl2/igt@perf_pmu@module-unload.html
* igt@prime_vgem@sync@rcs0:
- shard-iclb: [INCOMPLETE][66] ([i915#409]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-iclb5/igt@prime_vgem@sync@rcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-iclb4/igt@prime_vgem@sync@rcs0.html
* igt@sysfs_heartbeat_interval@mixed@rcs0:
- shard-skl: [FAIL][68] ([i915#1731]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl5/igt@sysfs_heartbeat_interval@mixed@rcs0.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl10/igt@sysfs_heartbeat_interval@mixed@rcs0.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-glk: [SKIP][70] ([fdo#109271] / [i915#658]) -> [SKIP][71] ([fdo#109271])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-glk5/igt@i915_pm_dc@dc3co-vpb-simulation.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-glk6/igt@i915_pm_dc@dc3co-vpb-simulation.html
- shard-apl: [SKIP][72] ([fdo#109271] / [i915#1635] / [i915#658]) -> [SKIP][73] ([fdo#109271] / [i915#1635])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-apl1/igt@i915_pm_dc@dc3co-vpb-simulation.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-apl4/igt@i915_pm_dc@dc3co-vpb-simulation.html
- shard-kbl: [SKIP][74] ([fdo#109271] / [i915#658]) -> [SKIP][75] ([fdo#109271])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-kbl3/igt@i915_pm_dc@dc3co-vpb-simulation.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-kbl6/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-skl: [FAIL][76] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][77] ([fdo#108145] / [i915#1982])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
- shard-apl: [FAIL][78] ([fdo#108145] / [i915#1635] / [i915#265]) -> [DMESG-FAIL][79] ([fdo#108145] / [i915#1635] / [i915#1982])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-apl4/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@runner@aborted:
- shard-hsw: [FAIL][80] -> [FAIL][81] ([i915#483])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-hsw7/igt@runner@aborted.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-hsw1/igt@runner@aborted.html
- shard-iclb: ([FAIL][82], [FAIL][83], [FAIL][84]) ([i915#2426] / [i915#2439] / [i915#409] / [i915#483]) -> ([FAIL][85], [FAIL][86]) ([i915#2439] / [i915#483])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-iclb6/igt@runner@aborted.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-iclb5/igt@runner@aborted.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-iclb4/igt@runner@aborted.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-iclb4/igt@runner@aborted.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-iclb5/igt@runner@aborted.html
- shard-glk: ([FAIL][87], [FAIL][88], [FAIL][89], [FAIL][90]) ([i915#1611] / [i915#1814] / [i915#2439] / [k.org#202321]) -> ([FAIL][91], [FAIL][92]) ([i915#1611] / [i915#2439] / [k.org#202321])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-glk6/igt@runner@aborted.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-glk8/igt@runner@aborted.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-glk4/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-glk8/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-glk9/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-glk2/igt@runner@aborted.html
- shard-skl: [FAIL][93] ([i915#1611] / [i915#2439]) -> ([FAIL][94], [FAIL][95]) ([i915#1436] / [i915#1611] / [i915#2439] / [i915#483])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9304/shard-skl10/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl4/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/shard-skl5/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#2597]: https://gitlab.freedesktop.org/drm/intel/issues/2597
[i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#71]: https://gitlab.freedesktop.org/drm/intel/issues/71
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9304 -> Patchwork_18875
CI-20190529: 20190529
CI_DRM_9304: dd49914f9e07f649be2e23beefe3248b0f5d617c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5845: 48bf21fabbf7a5d8a9458fe449394f190c3f2331 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18875: 78b61540ef10f963f9c4caadfbcbef8223c62eba @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18875/index.html
[-- Attachment #1.2: Type: text/html, Size: 26256 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
2020-11-06 10:14 ` [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs Gwan-gyeong Mun
@ 2020-11-18 11:11 ` Jani Nikula
2020-12-11 10:45 ` Mun, Gwan-gyeong
2020-11-18 11:12 ` Jani Nikula
1 sibling, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2020-11-18 11:11 UTC (permalink / raw)
To: Gwan-gyeong Mun, intel-gfx
On Fri, 06 Nov 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
> In order to support the PSR state of each transcoder, it adds
> i915_psr_status to sub-directory of each transcoder.
>
> v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
> permissions '0444'
>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 23 +++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 8402e6ac9f76..37805615a221 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2093,6 +2093,23 @@ static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
> }
> DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
>
> +static int i915_psr_status_show(struct seq_file *m, void *data)
> +{
> + struct drm_connector *connector = m->private;
> + struct intel_dp *intel_dp =
> + intel_attached_dp(to_intel_connector(connector));
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (connector->status != connector_status_connected)
> + return -ENODEV;
> +
> + if (!HAS_PSR(dev_priv))
> + return -ENODEV;
> +
> + return intel_psr_status(m, intel_dp);
> +}
> +DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
> +
> #define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
> seq_puts(m, "LPSP: incapable\n"))
>
> @@ -2268,6 +2285,12 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
> connector, &i915_psr_sink_status_fops);
> }
>
> + if (INTEL_GEN(dev_priv) >= 12 &&
I'd add this for all generations to unify the debugfs, and eventually
phase out the non connector specific debugfs file.
And I'd add HAS_PSR() check here to not create the file if it's not
possible instead of having the check in i915_psr_status_show().
BR,
Jani.
> + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> + debugfs_create_file("i915_psr_status", 0444, root,
> + connector, &i915_psr_status_fops);
> + }
> +
> if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
2020-11-06 10:14 ` [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs Gwan-gyeong Mun
2020-11-18 11:11 ` Jani Nikula
@ 2020-11-18 11:12 ` Jani Nikula
2020-12-04 16:06 ` Anshuman Gupta
1 sibling, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2020-11-18 11:12 UTC (permalink / raw)
To: Gwan-gyeong Mun, intel-gfx
On Fri, 06 Nov 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
> In order to support the PSR state of each transcoder, it adds
> i915_psr_status to sub-directory of each transcoder.
>
> v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
> permissions '0444'
>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 23 +++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 8402e6ac9f76..37805615a221 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2093,6 +2093,23 @@ static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
> }
> DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
>
> +static int i915_psr_status_show(struct seq_file *m, void *data)
> +{
> + struct drm_connector *connector = m->private;
> + struct intel_dp *intel_dp =
> + intel_attached_dp(to_intel_connector(connector));
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (connector->status != connector_status_connected)
How's this possible for eDP, btw?
BR,
Jani.
> + return -ENODEV;
> +
> + if (!HAS_PSR(dev_priv))
> + return -ENODEV;
> +
> + return intel_psr_status(m, intel_dp);
> +}
> +DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
> +
> #define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
> seq_puts(m, "LPSP: incapable\n"))
>
> @@ -2268,6 +2285,12 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
> connector, &i915_psr_sink_status_fops);
> }
>
> + if (INTEL_GEN(dev_priv) >= 12 &&
> + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> + debugfs_create_file("i915_psr_status", 0444, root,
> + connector, &i915_psr_status_fops);
> + }
> +
> if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
2020-11-18 11:12 ` Jani Nikula
@ 2020-12-04 16:06 ` Anshuman Gupta
2020-12-11 10:50 ` Mun, Gwan-gyeong
0 siblings, 1 reply; 17+ messages in thread
From: Anshuman Gupta @ 2020-12-04 16:06 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On 2020-11-18 at 16:42:29 +0530, Jani Nikula wrote:
> On Fri, 06 Nov 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> wrote:
> > In order to support the PSR state of each transcoder, it adds
> > i915_psr_status to sub-directory of each transcoder.
> >
> > v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
> > permissions '0444'
> >
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > .../drm/i915/display/intel_display_debugfs.c | 23 +++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 8402e6ac9f76..37805615a221 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -2093,6 +2093,23 @@ static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
> > }
> > DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
> >
> > +static int i915_psr_status_show(struct seq_file *m, void *data)
> > +{
> > + struct drm_connector *connector = m->private;
> > + struct intel_dp *intel_dp =
> > + intel_attached_dp(to_intel_connector(connector));
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + if (connector->status != connector_status_connected)
>
> How's this possible for eDP, btw?
>
> BR,
> Jani.
>
> > + return -ENODEV;
> > +
> > + if (!HAS_PSR(dev_priv))
> > + return -ENODEV;
> > +
> > + return intel_psr_status(m, intel_dp);
> > +}
> > +DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
> > +
> > #define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
> > seq_puts(m, "LPSP: incapable\n"))
> >
> > @@ -2268,6 +2285,12 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
> > connector, &i915_psr_sink_status_fops);
> > }
> >
> > + if (INTEL_GEN(dev_priv) >= 12 &&
> > + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
Hi GG
IMHO this should connector->connector_type == DRM_MODE_CONNECTOR_eDP || connector->connector_type == DRM_MODE_SUBCONNECTOR_DisplayPort
to support DP Panel Reply, i read somewere DP panel reply is PSR with Link Full ON ?
I believe this would be the reason to keep file name as "i915_psr_status" instead of i915_edp_psr_status?
Thanks,
Anshuman.
> > + debugfs_create_file("i915_psr_status", 0444, root,
> > + connector, &i915_psr_status_fops);
> > + }
> > +
> > if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> > connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> > connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
>
> --
> Jani Nikula, Intel Open Source Graphics Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders
2020-11-06 10:14 [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Gwan-gyeong Mun
` (8 preceding siblings ...)
2020-11-10 23:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-12-04 16:38 ` Anshuman Gupta
2020-12-11 10:22 ` Mun, Gwan-gyeong
9 siblings, 1 reply; 17+ messages in thread
From: Anshuman Gupta @ 2020-12-04 16:38 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
On 2020-11-06 at 15:44:42 +0530, Gwan-gyeong Mun wrote:
> It is a preliminary work for supporting multiple EDP PSR and
> DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> supportable PSR.
> And this moves and renames the i915_psr structure of drm_i915_private's to
> intel_dp's intel_psr structure.
> It also causes changes in PSR interrupt handling routine for supporting
> multiple transcoders. But it does not change the scenario and timing of
> enabling and disabling PSR.
Could you please break this patch, it can be break in following parts.
1. psr init path
2. atomic commit path
3. irq path
3. debugfs path
There are couple of comments, see below.
>
> v2: Fix indentation and add comments
> v3: Remove Blank line
> v4: Rebased
>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 5 +
> drivers/gpu/drm/i915/display/intel_display.c | 4 -
> .../drm/i915/display/intel_display_debugfs.c | 111 ++--
> .../drm/i915/display/intel_display_types.h | 38 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 585 ++++++++++--------
> drivers/gpu/drm/i915/display/intel_psr.h | 14 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
> drivers/gpu/drm/i915/i915_drv.h | 38 --
> drivers/gpu/drm/i915/i915_irq.c | 47 +-
> 10 files changed, 491 insertions(+), 380 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 19b16517a502..983781ce3683 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4127,7 +4127,10 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
>
> intel_ddi_set_dp_msa(crtc_state, conn_state);
>
> + //TODO: move PSR related functions into intel_psr_update()
> + intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
> intel_psr_update(intel_dp, crtc_state, conn_state);
> +
> intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> intel_edp_drrs_update(intel_dp, crtc_state);
>
> @@ -5275,6 +5278,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> goto err;
>
> dig_port->hpd_pulse = intel_dp_hpd_pulse;
> +
> + intel_psr_init(&dig_port->dp);
IMHO this should be called from intel_dp_init_connector.
> }
>
> /* In theory we don't need the encoder->type check, but leave it just in
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8c4687b19814..466923a54370 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15506,8 +15506,6 @@ static void commit_pipe_config(struct intel_atomic_state *state,
>
> if (new_crtc_state->update_pipe)
> intel_pipe_fastset(old_crtc_state, new_crtc_state);
> -
> - intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
> }
>
> if (dev_priv->display.atomic_update_watermarks)
> @@ -17435,8 +17433,6 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> intel_dvo_init(dev_priv);
> }
>
> - intel_psr_init(dev_priv);
> -
> for_each_intel_encoder(&dev_priv->drm, encoder) {
> encoder->base.possible_crtcs =
> intel_encoder_possible_crtcs(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index cfb4c1474982..8402e6ac9f76 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -248,18 +248,17 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
> "sink internal error",
> };
> struct drm_connector *connector = m->private;
> - struct drm_i915_private *dev_priv = to_i915(connector->dev);
> struct intel_dp *intel_dp =
> intel_attached_dp(to_intel_connector(connector));
> int ret;
>
> - if (!CAN_PSR(dev_priv)) {
> - seq_puts(m, "PSR Unsupported\n");
> + if (connector->status != connector_status_connected)
> return -ENODEV;
> - }
>
> - if (connector->status != connector_status_connected)
> + if (!CAN_PSR(intel_dp)) {
> + seq_puts(m, "PSR Unsupported\n");
> return -ENODEV;
> + }
>
> ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
>
> @@ -279,12 +278,13 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
> DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
>
> static void
> -psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
> +psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
> {
> u32 val, status_val;
> const char *status = "unknown";
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - if (dev_priv->psr.psr2_enabled) {
> + if (intel_dp->psr.psr2_enabled) {
> static const char * const live_status[] = {
> "IDLE",
> "CAPTURE",
> @@ -299,7 +299,7 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
> "TG_ON"
> };
> val = intel_de_read(dev_priv,
> - EDP_PSR2_STATUS(dev_priv->psr.transcoder));
> + EDP_PSR2_STATUS(intel_dp->psr.transcoder));
> status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> EDP_PSR2_STATUS_STATE_SHIFT;
> if (status_val < ARRAY_SIZE(live_status))
> @@ -316,7 +316,7 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
> "SRDENT_ON",
> };
> val = intel_de_read(dev_priv,
> - EDP_PSR_STATUS(dev_priv->psr.transcoder));
> + EDP_PSR_STATUS(intel_dp->psr.transcoder));
> status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
> EDP_PSR_STATUS_STATE_SHIFT;
> if (status_val < ARRAY_SIZE(live_status))
> @@ -326,21 +326,18 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
> seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
> }
>
> -static int i915_edp_psr_status(struct seq_file *m, void *data)
> +static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - struct i915_psr *psr = &dev_priv->psr;
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_psr *psr = &intel_dp->psr;
> intel_wakeref_t wakeref;
> const char *status;
> bool enabled;
> u32 val;
>
> - if (!HAS_PSR(dev_priv))
> - return -ENODEV;
> -
> seq_printf(m, "Sink support: %s", yesno(psr->sink_support));
> - if (psr->dp)
> - seq_printf(m, " [0x%02x]", psr->dp->psr_dpcd[0]);
> + if (psr->sink_support)
> + seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
> seq_puts(m, "\n");
>
> if (!psr->sink_support)
> @@ -364,16 +361,16 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>
> if (psr->psr2_enabled) {
> val = intel_de_read(dev_priv,
> - EDP_PSR2_CTL(dev_priv->psr.transcoder));
> + EDP_PSR2_CTL(intel_dp->psr.transcoder));
> enabled = val & EDP_PSR2_ENABLE;
> } else {
> val = intel_de_read(dev_priv,
> - EDP_PSR_CTL(dev_priv->psr.transcoder));
> + EDP_PSR_CTL(intel_dp->psr.transcoder));
> enabled = val & EDP_PSR_ENABLE;
> }
> seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
> enableddisabled(enabled), val);
> - psr_source_status(dev_priv, m);
> + psr_source_status(intel_dp, m);
> seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
> psr->busy_frontbuffer_bits);
>
> @@ -382,7 +379,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
> */
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> val = intel_de_read(dev_priv,
> - EDP_PSR_PERF_CNT(dev_priv->psr.transcoder));
> + EDP_PSR_PERF_CNT(intel_dp->psr.transcoder));
> val &= EDP_PSR_PERF_CNT_MASK;
> seq_printf(m, "Performance counter: %u\n", val);
> }
> @@ -403,7 +400,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
> */
> for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
> val = intel_de_read(dev_priv,
> - PSR2_SU_STATUS(dev_priv->psr.transcoder, frame));
> + PSR2_SU_STATUS(intel_dp->psr.transcoder, frame));
> su_frames_val[frame / 3] = val;
> }
>
> @@ -429,23 +426,57 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
> return 0;
> }
>
> +static int i915_edp_psr_status(struct seq_file *m, void *data)
> +{
> + struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_encoder *encoder;
> + struct intel_dp *intel_dp = NULL;
> +
> + if (!HAS_PSR(dev_priv))
> + return -ENODEV;
> +
> + /* Find the first EDP */
> + for_each_intel_dp(&dev_priv->drm, encoder) {
> + if (encoder->type == INTEL_OUTPUT_EDP) {
> + intel_dp = enc_to_intel_dp(encoder);
> + break;
> + }
> + }
> +
> + if (!intel_dp)
> + return -ENODEV;
> +
> + return intel_psr_status(m, intel_dp);
> +}
> +
> static int
> i915_edp_psr_debug_set(void *data, u64 val)
> {
> struct drm_i915_private *dev_priv = data;
> intel_wakeref_t wakeref;
> - int ret;
> + int ret = -ENODEV;
> + struct intel_encoder *encoder;
>
> - if (!CAN_PSR(dev_priv))
> - return -ENODEV;
> + if (!HAS_PSR(dev_priv))
> + return ret;
>
> - drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val);
> + for_each_intel_dp(&dev_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> - wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> + if (!CAN_PSR(intel_dp))
> + continue;
>
> - ret = intel_psr_debug_set(dev_priv, val);
> + if (encoder->type == INTEL_OUTPUT_EDP) {
> + drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val);
>
> - intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> + wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> +
> + // TODO: split to each transcoder's PSR debug state
> + ret = intel_psr_debug_set(intel_dp, val);
> +
> + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> + }
> + }
>
> return ret;
> }
> @@ -454,12 +485,25 @@ static int
> i915_edp_psr_debug_get(void *data, u64 *val)
> {
> struct drm_i915_private *dev_priv = data;
> + struct intel_encoder *encoder;
>
> - if (!CAN_PSR(dev_priv))
> + if (!HAS_PSR(dev_priv))
> return -ENODEV;
>
> - *val = READ_ONCE(dev_priv->psr.debug);
> - return 0;
> + for_each_intel_dp(&dev_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + if (!CAN_PSR(intel_dp))
> + continue;
> +
> + // TODO: split to each transcoder's PSR debug state
> + if (encoder->type == INTEL_OUTPUT_EDP) {
> + *val = READ_ONCE(intel_dp->psr.debug);
> + return 0;
> + }
> + }
> +
> + return -ENODEV;
> }
>
> DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
> @@ -1103,9 +1147,6 @@ static void drrs_status_per_crtc(struct seq_file *m,
> /* disable_drrs() will make drrs->dp NULL */
> if (!drrs->dp) {
> seq_puts(m, "Idleness DRRS: Disabled\n");
> - if (dev_priv->psr.enabled)
> - seq_puts(m,
> - "\tAs PSR is enabled, DRRS is not enabled\n");
> mutex_unlock(&drrs->mutex);
> return;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f6f0626649e0..2e40fcbab2aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1286,6 +1286,42 @@ struct intel_dp_compliance {
> u8 test_lane_count;
> };
>
> +struct intel_psr {
> + /* Mutex for PSR state of the transcoder */
> + struct mutex lock;
> +
> +#define I915_PSR_DEBUG_MODE_MASK 0x0f
> +#define I915_PSR_DEBUG_DEFAULT 0x00
> +#define I915_PSR_DEBUG_DISABLE 0x01
> +#define I915_PSR_DEBUG_ENABLE 0x02
> +#define I915_PSR_DEBUG_FORCE_PSR1 0x03
> +#define I915_PSR_DEBUG_IRQ 0x10
> +
> + u32 debug;
> + bool sink_support;
> + bool enabled;
> + enum pipe pipe;
> + enum transcoder transcoder;
> + bool active;
> + struct work_struct work;
> + unsigned int busy_frontbuffer_bits;
> + bool sink_psr2_support;
> + bool link_standby;
> + bool colorimetry_support;
> + bool psr2_enabled;
> + bool psr2_sel_fetch_enabled;
> + u8 sink_sync_latency;
> + ktime_t last_entry_attempt;
> + ktime_t last_exit;
> + bool sink_not_reliable;
> + bool irq_aux_error;
> + u16 su_x_granularity;
> + bool dc3co_enabled;
> + u32 dc3co_exit_delay;
> + struct delayed_work dc3co_work;
> + struct drm_dp_vsc_sdp vsc;
> +};
> +
> struct intel_dp {
> i915_reg_t output_reg;
> u32 DP;
> @@ -1406,6 +1442,8 @@ struct intel_dp {
>
> bool hobl_failed;
> bool hobl_active;
> +
> + struct intel_psr psr;
> };
>
> enum lspcon_vendor {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3b0dbda5919a..64abc9d037f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2640,12 +2640,10 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> const struct drm_connector_state *conn_state,
> struct drm_dp_vsc_sdp *vsc)
> {
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> vsc->sdp_type = DP_SDP_VSC;
>
> - if (dev_priv->psr.psr2_enabled) {
> - if (dev_priv->psr.colorimetry_support &&
> + if (intel_dp->psr.psr2_enabled) {
> + if (intel_dp->psr.colorimetry_support &&
> intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> /* [PSR2, +Colorimetry] */
> intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> @@ -3778,7 +3776,7 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> return false;
> }
>
> - if (CAN_PSR(i915) && intel_dp_is_edp(intel_dp)) {
> + if (CAN_PSR(intel_dp) && intel_dp_is_edp(intel_dp)) {
> drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
> crtc_state->uapi.mode_changed = true;
> return false;
> @@ -7978,6 +7976,17 @@ static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
> drm_kms_helper_hotplug_event(connector->dev);
> }
>
> +static void intel_dp_update_pipe(struct intel_atomic_state *state,
> + struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
> + intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
> +}
> +
> bool
> intel_dp_init_connector(struct intel_digital_port *dig_port,
> struct intel_connector *intel_connector)
> @@ -8133,7 +8142,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> intel_encoder->get_config = intel_dp_get_config;
> intel_encoder->sync_state = intel_dp_sync_state;
> intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> - intel_encoder->update_pipe = intel_panel_update_backlight;
> + intel_encoder->update_pipe = intel_dp_update_pipe;
> intel_encoder->suspend = intel_dp_encoder_suspend;
> intel_encoder->shutdown = intel_dp_encoder_shutdown;
> if (IS_CHERRYVIEW(dev_priv)) {
> @@ -8220,6 +8229,8 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> if (!intel_dp_init_connector(dig_port, intel_connector))
> goto err_init_connector;
>
> + intel_psr_init(&dig_port->dp);
IMHO this will not get called for DDI encoder intel_dp_init_connector is correcr place
to initialize it.
Thanks,
Anshuman Gupta.
> +
> return true;
>
> err_init_connector:
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index b3631b722de3..8d858d56c736 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -79,11 +79,13 @@
> * use page flips.
> */
>
> -static bool psr_global_enabled(struct drm_i915_private *i915)
> +static bool psr_global_enabled(struct intel_dp *intel_dp)
> {
> - switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> case I915_PSR_DEBUG_DEFAULT:
> - return i915->params.enable_psr;
> + return dev_priv->params.enable_psr;
> case I915_PSR_DEBUG_DISABLE:
> return false;
> default:
> @@ -91,9 +93,9 @@ static bool psr_global_enabled(struct drm_i915_private *i915)
> }
> }
>
> -static bool psr2_global_enabled(struct drm_i915_private *dev_priv)
> +static bool psr2_global_enabled(struct intel_dp *intel_dp)
> {
> - switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> + switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> case I915_PSR_DEBUG_DISABLE:
> case I915_PSR_DEBUG_FORCE_PSR1:
> return false;
> @@ -102,11 +104,12 @@ static bool psr2_global_enabled(struct drm_i915_private *dev_priv)
> }
> }
>
> -static void psr_irq_control(struct drm_i915_private *dev_priv)
> +static void psr_irq_control(struct intel_dp *intel_dp)
> {
> enum transcoder trans_shift;
> u32 mask, val;
> i915_reg_t imr_reg;
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> /*
> * gen12+ has registers relative to transcoder and one per transcoder
> @@ -115,14 +118,14 @@ static void psr_irq_control(struct drm_i915_private *dev_priv)
> */
> if (INTEL_GEN(dev_priv) >= 12) {
> trans_shift = 0;
> - imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
> + imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> } else {
> - trans_shift = dev_priv->psr.transcoder;
> + trans_shift = intel_dp->psr.transcoder;
> imr_reg = EDP_PSR_IMR;
> }
>
> mask = EDP_PSR_ERROR(trans_shift);
> - if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
> + if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
> mask |= EDP_PSR_POST_EXIT(trans_shift) |
> EDP_PSR_PRE_ENTRY(trans_shift);
>
> @@ -171,38 +174,37 @@ static void psr_event_print(struct drm_i915_private *i915,
> drm_dbg_kms(&i915->drm, "\tPSR disabled\n");
> }
>
> -void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
> +void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
> {
> - enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> enum transcoder trans_shift;
> i915_reg_t imr_reg;
> ktime_t time_ns = ktime_get();
>
> if (INTEL_GEN(dev_priv) >= 12) {
> trans_shift = 0;
> - imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
> + imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> } else {
> - trans_shift = dev_priv->psr.transcoder;
> + trans_shift = intel_dp->psr.transcoder;
> imr_reg = EDP_PSR_IMR;
> }
>
> if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
> - dev_priv->psr.last_entry_attempt = time_ns;
> - drm_dbg_kms(&dev_priv->drm,
> - "[transcoder %s] PSR entry attempt in 2 vblanks\n",
> - transcoder_name(cpu_transcoder));
> + intel_dp->psr.last_entry_attempt = time_ns;
> + DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
> + transcoder_name(cpu_transcoder));
> }
>
> if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
> - dev_priv->psr.last_exit = time_ns;
> - drm_dbg_kms(&dev_priv->drm,
> - "[transcoder %s] PSR exit completed\n",
> - transcoder_name(cpu_transcoder));
> + intel_dp->psr.last_exit = time_ns;
> + DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
> + transcoder_name(cpu_transcoder));
>
> if (INTEL_GEN(dev_priv) >= 9) {
> u32 val = intel_de_read(dev_priv,
> PSR_EVENT(cpu_transcoder));
> - bool psr2_enabled = dev_priv->psr.psr2_enabled;
> + bool psr2_enabled = intel_dp->psr.psr2_enabled;
>
> intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder),
> val);
> @@ -213,10 +215,10 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
> if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
> u32 val;
>
> - drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
> + DRM_WARN("[transcoder %s] PSR aux error\n",
> transcoder_name(cpu_transcoder));
>
> - dev_priv->psr.irq_aux_error = true;
> + intel_dp->psr.irq_aux_error = true;
>
> /*
> * If this interruption is not masked it will keep
> @@ -230,7 +232,7 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
> val |= EDP_PSR_ERROR(trans_shift);
> intel_de_write(dev_priv, imr_reg, val);
>
> - schedule_work(&dev_priv->psr.work);
> + schedule_work(&intel_dp->psr.work);
> }
> }
>
> @@ -291,12 +293,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv =
> to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
>
> - if (dev_priv->psr.dp) {
> - drm_warn(&dev_priv->drm,
> - "More than one eDP panel found, PSR support should be extended\n");
> - return;
> - }
> -
> drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
> sizeof(intel_dp->psr_dpcd));
>
> @@ -317,12 +313,10 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> return;
> }
>
> - dev_priv->psr.sink_support = true;
> - dev_priv->psr.sink_sync_latency =
> + intel_dp->psr.sink_support = true;
> + intel_dp->psr.sink_sync_latency =
> intel_dp_get_sink_sync_latency(intel_dp);
>
> - dev_priv->psr.dp = intel_dp;
> -
> if (INTEL_GEN(dev_priv) >= 9 &&
> (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
> bool y_req = intel_dp->psr_dpcd[1] &
> @@ -340,14 +334,14 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> * Y-coordinate requirement panels we would need to enable
> * GTC first.
> */
> - dev_priv->psr.sink_psr2_support = y_req && alpm;
> + intel_dp->psr.sink_psr2_support = y_req && alpm;
> drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
> - dev_priv->psr.sink_psr2_support ? "" : "not ");
> + intel_dp->psr.sink_psr2_support ? "" : "not ");
>
> - if (dev_priv->psr.sink_psr2_support) {
> - dev_priv->psr.colorimetry_support =
> + if (intel_dp->psr.sink_psr2_support) {
> + intel_dp->psr.colorimetry_support =
> intel_dp_get_colorimetry_status(intel_dp);
> - dev_priv->psr.su_x_granularity =
> + intel_dp->psr.su_x_granularity =
> intel_dp_get_su_x_granulartiy(intel_dp);
> }
> }
> @@ -373,7 +367,7 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
> BUILD_BUG_ON(sizeof(aux_msg) > 20);
> for (i = 0; i < sizeof(aux_msg); i += 4)
> intel_de_write(dev_priv,
> - EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2),
> + EDP_PSR_AUX_DATA(intel_dp->psr.transcoder, i >> 2),
> intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
>
> aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
> @@ -384,7 +378,7 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
>
> /* Select only valid bits for SRD_AUX_CTL */
> aux_ctl &= psr_aux_mask;
> - intel_de_write(dev_priv, EDP_PSR_AUX_CTL(dev_priv->psr.transcoder),
> + intel_de_write(dev_priv, EDP_PSR_AUX_CTL(intel_dp->psr.transcoder),
> aux_ctl);
> }
>
> @@ -394,14 +388,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
> u8 dpcd_val = DP_PSR_ENABLE;
>
> /* Enable ALPM at sink for psr2 */
> - if (dev_priv->psr.psr2_enabled) {
> + if (intel_dp->psr.psr2_enabled) {
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
> DP_ALPM_ENABLE |
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
>
> dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> } else {
> - if (dev_priv->psr.link_standby)
> + if (intel_dp->psr.link_standby)
> dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
>
> if (INTEL_GEN(dev_priv) >= 8)
> @@ -464,7 +458,7 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
> * off-by-one issue that HW has in some cases.
> */
> idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> - idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
> + idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
>
> if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
> idle_frames = 0xf;
> @@ -484,7 +478,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
> if (IS_HASWELL(dev_priv))
> val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>
> - if (dev_priv->psr.link_standby)
> + if (intel_dp->psr.link_standby)
> val |= EDP_PSR_LINK_STANDBY;
>
> val |= intel_psr1_get_tp_time(intel_dp);
> @@ -492,9 +486,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
> if (INTEL_GEN(dev_priv) >= 8)
> val |= EDP_PSR_CRC_ENABLE;
>
> - val |= (intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) &
> + val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &
> EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
> - intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), val);
> + intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val);
> }
>
> static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
> @@ -529,7 +523,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> val |= EDP_Y_COORDINATE_ENABLE;
>
> - val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
> + val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
> val |= intel_psr2_get_tp_time(intel_dp);
>
> if (INTEL_GEN(dev_priv) >= 12) {
> @@ -548,7 +542,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> val |= EDP_PSR2_FAST_WAKE(7);
> }
>
> - if (dev_priv->psr.psr2_sel_fetch_enabled) {
> + if (intel_dp->psr.psr2_sel_fetch_enabled) {
> /* WA 1408330847 */
> if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> @@ -557,20 +551,20 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> DIS_RAM_BYPASS_PSR2_MAN_TRACK);
>
> intel_de_write(dev_priv,
> - PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder),
> + PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
> PSR2_MAN_TRK_CTL_ENABLE);
> } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> intel_de_write(dev_priv,
> - PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0);
> + PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
> }
>
> /*
> * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
> * recommending keep this bit unset while PSR2 is enabled.
> */
> - intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), 0);
> + intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0);
>
> - intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
> + intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
> }
>
> static bool
> @@ -593,55 +587,58 @@ static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
> drm_mode_vrefresh(&cstate->hw.adjusted_mode));
> }
>
> -static void psr2_program_idle_frames(struct drm_i915_private *dev_priv,
> +static void psr2_program_idle_frames(struct intel_dp *intel_dp,
> u32 idle_frames)
> {
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> u32 val;
>
> idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
> - val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder));
> + val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder));
> val &= ~EDP_PSR2_IDLE_FRAME_MASK;
> val |= idle_frames;
> - intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
> + intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
> }
>
> -static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv)
> +static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
> {
> - psr2_program_idle_frames(dev_priv, 0);
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + psr2_program_idle_frames(intel_dp, 0);
> intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> }
>
> -static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv)
> +static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
> {
> - struct intel_dp *intel_dp = dev_priv->psr.dp;
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
> - psr2_program_idle_frames(dev_priv, psr_compute_idle_frames(intel_dp));
> + psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
> }
>
> static void tgl_dc3co_disable_work(struct work_struct *work)
> {
> - struct drm_i915_private *dev_priv =
> - container_of(work, typeof(*dev_priv), psr.dc3co_work.work);
> + struct intel_dp *intel_dp =
> + container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
>
> - mutex_lock(&dev_priv->psr.lock);
> + mutex_lock(&intel_dp->psr.lock);
> /* If delayed work is pending, it is not idle */
> - if (delayed_work_pending(&dev_priv->psr.dc3co_work))
> + if (delayed_work_pending(&intel_dp->psr.dc3co_work))
> goto unlock;
>
> - tgl_psr2_disable_dc3co(dev_priv);
> + tgl_psr2_disable_dc3co(intel_dp);
> unlock:
> - mutex_unlock(&dev_priv->psr.lock);
> + mutex_unlock(&intel_dp->psr.lock);
> }
>
> -static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
> +static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
> {
> - if (!dev_priv->psr.dc3co_enabled)
> + if (!intel_dp->psr.dc3co_enabled)
> return;
>
> - cancel_delayed_work(&dev_priv->psr.dc3co_work);
> + cancel_delayed_work(&intel_dp->psr.dc3co_work);
> /* Before PSR2 exit disallow dc3co*/
> - tgl_psr2_disable_dc3co(dev_priv);
> + tgl_psr2_disable_dc3co(intel_dp);
> }
>
> static void
> @@ -714,7 +711,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
>
> - if (!dev_priv->psr.sink_psr2_support)
> + if (!intel_dp->psr.sink_psr2_support)
> return false;
>
> if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
> @@ -724,7 +721,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> return false;
> }
>
> - if (!psr2_global_enabled(dev_priv)) {
> + if (!psr2_global_enabled(intel_dp)) {
> drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
> return false;
> }
> @@ -773,10 +770,10 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> * only need to validate the SU block width is a multiple of
> * x granularity.
> */
> - if (crtc_hdisplay % dev_priv->psr.su_x_granularity) {
> + if (crtc_hdisplay % intel_dp->psr.su_x_granularity) {
> drm_dbg_kms(&dev_priv->drm,
> "PSR2 not enabled, hdisplay(%d) not multiple of %d\n",
> - crtc_hdisplay, dev_priv->psr.su_x_granularity);
> + crtc_hdisplay, intel_dp->psr.su_x_granularity);
> return false;
> }
>
> @@ -811,13 +808,10 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> &crtc_state->hw.adjusted_mode;
> int psr_setup_time;
>
> - if (!CAN_PSR(dev_priv))
> - return;
> -
> - if (intel_dp != dev_priv->psr.dp)
> + if (!CAN_PSR(intel_dp))
> return;
>
> - if (!psr_global_enabled(dev_priv)) {
> + if (!psr_global_enabled(intel_dp)) {
> drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
> return;
> }
> @@ -834,7 +828,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> return;
> }
>
> - if (dev_priv->psr.sink_not_reliable) {
> + if (intel_dp->psr.sink_not_reliable) {
> drm_dbg_kms(&dev_priv->drm,
> "PSR sink implementation is not reliable\n");
> return;
> @@ -870,23 +864,24 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> static void intel_psr_activate(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + enum transcoder transcoder = intel_dp->psr.transcoder;
>
> - if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder))
> + if (transcoder_has_psr2(dev_priv, transcoder))
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
> + intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE);
>
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
> - drm_WARN_ON(&dev_priv->drm, dev_priv->psr.active);
> - lockdep_assert_held(&dev_priv->psr.lock);
> + intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE);
> + drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
> + lockdep_assert_held(&intel_dp->psr.lock);
>
> /* psr1 and psr2 are mutually exclusive.*/
> - if (dev_priv->psr.psr2_enabled)
> + if (intel_dp->psr.psr2_enabled)
> hsw_activate_psr2(intel_dp);
> else
> hsw_activate_psr1(intel_dp);
>
> - dev_priv->psr.active = true;
> + intel_dp->psr.active = true;
> }
>
> static void intel_psr_enable_source(struct intel_dp *intel_dp,
> @@ -902,7 +897,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> hsw_psr_setup_aux(intel_dp);
>
> - if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
> + if (intel_dp->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
> !IS_GEMINILAKE(dev_priv))) {
> i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
> u32 chicken = intel_de_read(dev_priv, reg);
> @@ -926,10 +921,10 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> if (INTEL_GEN(dev_priv) < 11)
> mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
>
> - intel_de_write(dev_priv, EDP_PSR_DEBUG(dev_priv->psr.transcoder),
> + intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder),
> mask);
>
> - psr_irq_control(dev_priv);
> + psr_irq_control(intel_dp);
>
> if (crtc_state->dc3co_exitline) {
> u32 val;
> @@ -947,30 +942,30 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>
> if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
> - dev_priv->psr.psr2_sel_fetch_enabled ?
> + intel_dp->psr.psr2_sel_fetch_enabled ?
> IGNORE_PSR2_HW_TRACKING : 0);
> }
>
> -static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
> +static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> - struct intel_dp *intel_dp = dev_priv->psr.dp;
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct intel_encoder *encoder = &dig_port->base;
> u32 val;
>
> - drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
> + drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
>
> - dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
> - dev_priv->psr.busy_frontbuffer_bits = 0;
> - dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> - dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
> - dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
> + intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> + intel_dp->psr.busy_frontbuffer_bits = 0;
> + intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> + intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
> + intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> /* DC5/DC6 requires at least 6 idle frames */
> val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> - dev_priv->psr.dc3co_exit_delay = val;
> - dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
> + intel_dp->psr.dc3co_exit_delay = val;
> + intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
>
> /*
> * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
> @@ -982,27 +977,27 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
> */
> if (INTEL_GEN(dev_priv) >= 12) {
> val = intel_de_read(dev_priv,
> - TRANS_PSR_IIR(dev_priv->psr.transcoder));
> + TRANS_PSR_IIR(intel_dp->psr.transcoder));
> val &= EDP_PSR_ERROR(0);
> } else {
> val = intel_de_read(dev_priv, EDP_PSR_IIR);
> - val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
> + val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
> }
> if (val) {
> - dev_priv->psr.sink_not_reliable = true;
> + intel_dp->psr.sink_not_reliable = true;
> drm_dbg_kms(&dev_priv->drm,
> "PSR interruption error set, not enabling PSR\n");
> return;
> }
>
> drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> - dev_priv->psr.psr2_enabled ? "2" : "1");
> + intel_dp->psr.psr2_enabled ? "2" : "1");
> intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> - &dev_priv->psr.vsc);
> - intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
> + &intel_dp->psr.vsc);
> + intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
> intel_psr_enable_sink(intel_dp);
> intel_psr_enable_source(intel_dp, crtc_state);
> - dev_priv->psr.enabled = true;
> + intel_dp->psr.enabled = true;
>
> intel_psr_activate(intel_dp);
> }
> @@ -1021,7 +1016,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp)
> + if (!CAN_PSR(intel_dp))
> return;
>
> if (!crtc_state->has_psr)
> @@ -1029,46 +1024,47 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>
> drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
>
> - mutex_lock(&dev_priv->psr.lock);
> - intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
> - mutex_unlock(&dev_priv->psr.lock);
> + mutex_lock(&intel_dp->psr.lock);
> + intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
> + mutex_unlock(&intel_dp->psr.lock);
> }
>
> -static void intel_psr_exit(struct drm_i915_private *dev_priv)
> +static void intel_psr_exit(struct intel_dp *intel_dp)
> {
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> u32 val;
>
> - if (!dev_priv->psr.active) {
> - if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) {
> + if (!intel_dp->psr.active) {
> + if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) {
> val = intel_de_read(dev_priv,
> - EDP_PSR2_CTL(dev_priv->psr.transcoder));
> + EDP_PSR2_CTL(intel_dp->psr.transcoder));
> drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
> }
>
> val = intel_de_read(dev_priv,
> - EDP_PSR_CTL(dev_priv->psr.transcoder));
> + EDP_PSR_CTL(intel_dp->psr.transcoder));
> drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
>
> return;
> }
>
> - if (dev_priv->psr.psr2_enabled) {
> - tgl_disallow_dc3co_on_psr2_exit(dev_priv);
> + if (intel_dp->psr.psr2_enabled) {
> + tgl_disallow_dc3co_on_psr2_exit(intel_dp);
> val = intel_de_read(dev_priv,
> - EDP_PSR2_CTL(dev_priv->psr.transcoder));
> + EDP_PSR2_CTL(intel_dp->psr.transcoder));
> drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
> val &= ~EDP_PSR2_ENABLE;
> intel_de_write(dev_priv,
> - EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
> + EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
> } else {
> val = intel_de_read(dev_priv,
> - EDP_PSR_CTL(dev_priv->psr.transcoder));
> + EDP_PSR_CTL(intel_dp->psr.transcoder));
> drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
> val &= ~EDP_PSR_ENABLE;
> intel_de_write(dev_priv,
> - EDP_PSR_CTL(dev_priv->psr.transcoder), val);
> + EDP_PSR_CTL(intel_dp->psr.transcoder), val);
> }
> - dev_priv->psr.active = false;
> + intel_dp->psr.active = false;
> }
>
> static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> @@ -1077,21 +1073,21 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> i915_reg_t psr_status;
> u32 psr_status_mask;
>
> - lockdep_assert_held(&dev_priv->psr.lock);
> + lockdep_assert_held(&intel_dp->psr.lock);
>
> - if (!dev_priv->psr.enabled)
> + if (!intel_dp->psr.enabled)
> return;
>
> drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
> - dev_priv->psr.psr2_enabled ? "2" : "1");
> + intel_dp->psr.psr2_enabled ? "2" : "1");
>
> - intel_psr_exit(dev_priv);
> + intel_psr_exit(intel_dp);
>
> - if (dev_priv->psr.psr2_enabled) {
> - psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
> + if (intel_dp->psr.psr2_enabled) {
> + psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
> psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> } else {
> - psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder);
> + psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder);
> psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
> }
>
> @@ -1101,7 +1097,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
>
> /* WA 1408330847 */
> - if (dev_priv->psr.psr2_sel_fetch_enabled &&
> + if (intel_dp->psr.psr2_sel_fetch_enabled &&
> (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> @@ -1110,10 +1106,10 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> /* Disable PSR on Sink */
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
>
> - if (dev_priv->psr.psr2_enabled)
> + if (intel_dp->psr.psr2_enabled)
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
>
> - dev_priv->psr.enabled = false;
> + intel_dp->psr.enabled = false;
> }
>
> /**
> @@ -1131,20 +1127,22 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> if (!old_crtc_state->has_psr)
> return;
>
> - if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv)))
> + if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp)))
> return;
>
> - mutex_lock(&dev_priv->psr.lock);
> + mutex_lock(&intel_dp->psr.lock);
>
> intel_psr_disable_locked(intel_dp);
>
> - mutex_unlock(&dev_priv->psr.lock);
> - cancel_work_sync(&dev_priv->psr.work);
> - cancel_delayed_work_sync(&dev_priv->psr.dc3co_work);
> + mutex_unlock(&intel_dp->psr.lock);
> + cancel_work_sync(&intel_dp->psr.work);
> + cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
> }
>
> -static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
> +static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
> {
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> if (IS_TIGERLAKE(dev_priv))
> /*
> * Writes to CURSURFLIVE in TGL are causing IOMMU errors and
> @@ -1158,7 +1156,7 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
> * So using this workaround until this issue is root caused
> * and a better fix is found.
> */
> - intel_psr_exit(dev_priv);
> + intel_psr_exit(intel_dp);
> else if (INTEL_GEN(dev_priv) >= 9)
> /*
> * Display WA #0884: skl+
> @@ -1169,13 +1167,13 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
> * but it makes more sense write to the current active
> * pipe.
> */
> - intel_de_write(dev_priv, CURSURFLIVE(dev_priv->psr.pipe), 0);
> + intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
> else
> /*
> * A write to CURSURFLIVE do not cause HW tracking to exit PSR
> * on older gens so doing the manual exit instead.
> */
> - intel_psr_exit(dev_priv);
> + intel_psr_exit(intel_dp);
> }
>
> void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> @@ -1210,11 +1208,11 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
> }
>
> -void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
> +void intel_psr2_program_trans_man_trk_ctl(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct i915_psr *psr = &dev_priv->psr;
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_psr *psr = &intel_dp->psr;
>
> if (!HAS_PSR2_SEL_FETCH(dev_priv) ||
> !crtc_state->enable_psr2_sel_fetch)
> @@ -1326,13 +1324,13 @@ void intel_psr_update(struct intel_dp *intel_dp,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct i915_psr *psr = &dev_priv->psr;
> + struct intel_psr *psr = &intel_dp->psr;
> bool enable, psr2_enable;
>
> - if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp)
> + if (!CAN_PSR(intel_dp))
> return;
>
> - mutex_lock(&dev_priv->psr.lock);
> + mutex_lock(&intel_dp->psr.lock);
>
> enable = crtc_state->has_psr;
> psr2_enable = crtc_state->has_psr2;
> @@ -1340,15 +1338,15 @@ void intel_psr_update(struct intel_dp *intel_dp,
> if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
> /* Force a PSR exit when enabling CRC to avoid CRC timeouts */
> if (crtc_state->crc_enabled && psr->enabled)
> - psr_force_hw_tracking_exit(dev_priv);
> + psr_force_hw_tracking_exit(intel_dp);
> else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) {
> /*
> * Activate PSR again after a force exit when enabling
> * CRC in older gens
> */
> - if (!dev_priv->psr.active &&
> - !dev_priv->psr.busy_frontbuffer_bits)
> - schedule_work(&dev_priv->psr.work);
> + if (!intel_dp->psr.active &&
> + !intel_dp->psr.busy_frontbuffer_bits)
> + schedule_work(&intel_dp->psr.work);
> }
>
> goto unlock;
> @@ -1358,34 +1356,23 @@ void intel_psr_update(struct intel_dp *intel_dp,
> intel_psr_disable_locked(intel_dp);
>
> if (enable)
> - intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
> + intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
>
> unlock:
> - mutex_unlock(&dev_priv->psr.lock);
> + mutex_unlock(&intel_dp->psr.lock);
> }
>
> /**
> - * intel_psr_wait_for_idle - wait for PSR1 to idle
> - * @new_crtc_state: new CRTC state
> + * psr_wait_for_idle - wait for PSR1 to idle
> + * @intel_dp: Intel DP
> * @out_value: PSR status in case of failure
> *
> - * This function is expected to be called from pipe_update_start() where it is
> - * not expected to race with PSR enable or disable.
> - *
> * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
> + *
> */
> -int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
> - u32 *out_value)
> +static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -
> - if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
> - return 0;
> -
> - /* FIXME: Update this for PSR2 if we need to wait for idle */
> - if (READ_ONCE(dev_priv->psr.psr2_enabled))
> - return 0;
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> /*
> * From bspec: Panel Self Refresh (BDW+)
> @@ -1393,32 +1380,67 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
> * exit training time + 1.5 ms of aux channel handshake. 50 ms is
> * defensive enough to cover everything.
> */
> -
> return __intel_wait_for_register(&dev_priv->uncore,
> - EDP_PSR_STATUS(dev_priv->psr.transcoder),
> + EDP_PSR_STATUS(intel_dp->psr.transcoder),
> EDP_PSR_STATUS_STATE_MASK,
> EDP_PSR_STATUS_STATE_IDLE, 2, 50,
> out_value);
> }
>
> -static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
> +/**
> + * intel_psr_wait_for_idle - wait for PSR1 to idle
> + * @new_crtc_state: new CRTC state
> + *
> + * This function is expected to be called from pipe_update_start() where it is
> + * not expected to race with PSR enable or disable.
> + */
> +void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
> + struct intel_encoder *encoder;
> + u32 psr_status;
> +
> + if (!new_crtc_state->has_psr)
> + return;
> +
> + for_each_intel_dp(&dev_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + if (encoder->type != INTEL_OUTPUT_EDP)
> + continue;
> +
> + /* when the PSR1 is enabled */
> + if (intel_dp->psr.enabled && !intel_dp->psr.psr2_enabled) {
> + if (psr_wait_for_idle(intel_dp, &psr_status))
> + drm_err(&dev_priv->drm,
> + "PSR idle timed out 0x%x, atomic update may fail\n",
> + psr_status);
> +
> + /* only one trancoder can enable PSR1 */
> + break;
> + }
> + }
> +}
> +
> +static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
> {
> i915_reg_t reg;
> u32 mask;
> int err;
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - if (!dev_priv->psr.enabled)
> + if (!intel_dp->psr.enabled)
> return false;
>
> - if (dev_priv->psr.psr2_enabled) {
> - reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
> + if (intel_dp->psr.psr2_enabled) {
> + reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
> mask = EDP_PSR2_STATUS_STATE_MASK;
> } else {
> - reg = EDP_PSR_STATUS(dev_priv->psr.transcoder);
> + reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);
> mask = EDP_PSR_STATUS_STATE_MASK;
> }
>
> - mutex_unlock(&dev_priv->psr.lock);
> + mutex_unlock(&intel_dp->psr.lock);
>
> err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
> if (err)
> @@ -1426,8 +1448,8 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
> "Timed out waiting for PSR Idle for re-enable\n");
>
> /* After the unlocked wait, verify that PSR is still wanted! */
> - mutex_lock(&dev_priv->psr.lock);
> - return err == 0 && dev_priv->psr.enabled;
> + mutex_lock(&intel_dp->psr.lock);
> + return err == 0 && intel_dp->psr.enabled;
> }
>
> static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
> @@ -1493,11 +1515,12 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
> return err;
> }
>
> -int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
> +int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
> {
> const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
> u32 old_mode;
> int ret;
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
> mode > I915_PSR_DEBUG_FORCE_PSR1) {
> @@ -1505,21 +1528,21 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
> return -EINVAL;
> }
>
> - ret = mutex_lock_interruptible(&dev_priv->psr.lock);
> + ret = mutex_lock_interruptible(&intel_dp->psr.lock);
> if (ret)
> return ret;
>
> - old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
> - dev_priv->psr.debug = val;
> + old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
> + intel_dp->psr.debug = val;
>
> /*
> * Do it right away if it's already enabled, otherwise it will be done
> * when enabling the source.
> */
> - if (dev_priv->psr.enabled)
> - psr_irq_control(dev_priv);
> + if (intel_dp->psr.enabled)
> + psr_irq_control(intel_dp);
>
> - mutex_unlock(&dev_priv->psr.lock);
> + mutex_unlock(&intel_dp->psr.lock);
>
> if (old_mode != mode)
> ret = intel_psr_fastset_force(dev_priv);
> @@ -1527,28 +1550,28 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
> return ret;
> }
>
> -static void intel_psr_handle_irq(struct drm_i915_private *dev_priv)
> +static void intel_psr_handle_irq(struct intel_dp *intel_dp)
> {
> - struct i915_psr *psr = &dev_priv->psr;
> + struct intel_psr *psr = &intel_dp->psr;
>
> - intel_psr_disable_locked(psr->dp);
> + intel_psr_disable_locked(intel_dp);
> psr->sink_not_reliable = true;
> /* let's make sure that sink is awaken */
> - drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
> }
>
> static void intel_psr_work(struct work_struct *work)
> {
> - struct drm_i915_private *dev_priv =
> - container_of(work, typeof(*dev_priv), psr.work);
> + struct intel_dp *intel_dp =
> + container_of(work, typeof(*intel_dp), psr.work);
>
> - mutex_lock(&dev_priv->psr.lock);
> + mutex_lock(&intel_dp->psr.lock);
>
> - if (!dev_priv->psr.enabled)
> + if (!intel_dp->psr.enabled)
> goto unlock;
>
> - if (READ_ONCE(dev_priv->psr.irq_aux_error))
> - intel_psr_handle_irq(dev_priv);
> + if (READ_ONCE(intel_dp->psr.irq_aux_error))
> + intel_psr_handle_irq(intel_dp);
>
> /*
> * We have to make sure PSR is ready for re-enable
> @@ -1556,7 +1579,7 @@ static void intel_psr_work(struct work_struct *work)
> * PSR might take some time to get fully disabled
> * and be ready for re-enable.
> */
> - if (!__psr_wait_for_idle_locked(dev_priv))
> + if (!__psr_wait_for_idle_locked(intel_dp))
> goto unlock;
>
> /*
> @@ -1564,12 +1587,12 @@ static void intel_psr_work(struct work_struct *work)
> * recheck. Since psr_flush first clears this and then reschedules we
> * won't ever miss a flush when bailing out here.
> */
> - if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active)
> + if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
> goto unlock;
>
> - intel_psr_activate(dev_priv->psr.dp);
> + intel_psr_activate(intel_dp);
> unlock:
> - mutex_unlock(&dev_priv->psr.lock);
> + mutex_unlock(&intel_dp->psr.lock);
> }
>
> /**
> @@ -1588,27 +1611,35 @@ static void intel_psr_work(struct work_struct *work)
> void intel_psr_invalidate(struct drm_i915_private *dev_priv,
> unsigned frontbuffer_bits, enum fb_op_origin origin)
> {
> - if (!CAN_PSR(dev_priv))
> - return;
> + struct intel_encoder *encoder;
> + struct intel_dp *intel_dp;
>
> - if (origin == ORIGIN_FLIP)
> - return;
> + for_each_intel_dp(&dev_priv->drm, encoder) {
>
> - mutex_lock(&dev_priv->psr.lock);
> - if (!dev_priv->psr.enabled) {
> - mutex_unlock(&dev_priv->psr.lock);
> - return;
> - }
> + intel_dp = enc_to_intel_dp(encoder);
> + if (encoder->type != INTEL_OUTPUT_EDP)
> + continue;
> + if (!CAN_PSR(intel_dp))
> + continue;
> +
> + if (origin == ORIGIN_FLIP)
> + continue;
>
> - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
> - dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
> + mutex_lock(&intel_dp->psr.lock);
> + if (!intel_dp->psr.enabled) {
> + mutex_unlock(&intel_dp->psr.lock);
> + continue;
> + }
>
> - if (frontbuffer_bits)
> - intel_psr_exit(dev_priv);
> + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
> + intel_dp->psr.busy_frontbuffer_bits |= frontbuffer_bits;
>
> - mutex_unlock(&dev_priv->psr.lock);
> -}
> + if (frontbuffer_bits)
> + intel_psr_exit(intel_dp);
>
> + mutex_unlock(&intel_dp->psr.lock);
> + }
> +}
> /*
> * When we will be completely rely on PSR2 S/W tracking in future,
> * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
> @@ -1616,15 +1647,15 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv,
> * accordingly in future.
> */
> static void
> -tgl_dc3co_flush(struct drm_i915_private *dev_priv,
> - unsigned int frontbuffer_bits, enum fb_op_origin origin)
> +tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
> + enum fb_op_origin origin)
> {
> - mutex_lock(&dev_priv->psr.lock);
> + mutex_lock(&intel_dp->psr.lock);
>
> - if (!dev_priv->psr.dc3co_enabled)
> + if (!intel_dp->psr.dc3co_enabled)
> goto unlock;
>
> - if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active)
> + if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
> goto unlock;
>
> /*
> @@ -1632,15 +1663,15 @@ tgl_dc3co_flush(struct drm_i915_private *dev_priv,
> * when delayed work schedules that means display has been idle.
> */
> if (!(frontbuffer_bits &
> - INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe)))
> + INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
> goto unlock;
>
> - tgl_psr2_enable_dc3co(dev_priv);
> - mod_delayed_work(system_wq, &dev_priv->psr.dc3co_work,
> - dev_priv->psr.dc3co_exit_delay);
> + tgl_psr2_enable_dc3co(intel_dp);
> + mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work,
> + intel_dp->psr.dc3co_exit_delay);
>
> unlock:
> - mutex_unlock(&dev_priv->psr.lock);
> + mutex_unlock(&intel_dp->psr.lock);
> }
>
> /**
> @@ -1659,45 +1690,54 @@ tgl_dc3co_flush(struct drm_i915_private *dev_priv,
> void intel_psr_flush(struct drm_i915_private *dev_priv,
> unsigned frontbuffer_bits, enum fb_op_origin origin)
> {
> - if (!CAN_PSR(dev_priv))
> - return;
> -
> - if (origin == ORIGIN_FLIP) {
> - tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin);
> - return;
> - }
> -
> - mutex_lock(&dev_priv->psr.lock);
> - if (!dev_priv->psr.enabled) {
> - mutex_unlock(&dev_priv->psr.lock);
> - return;
> + struct intel_encoder *encoder;
> + struct intel_dp *intel_dp;
> +
> + for_each_intel_dp(&dev_priv->drm, encoder) {
> + intel_dp = enc_to_intel_dp(encoder);
> +
> + if (encoder->type == INTEL_OUTPUT_EDP && CAN_PSR(intel_dp)) {
> + if (origin == ORIGIN_FLIP) {
> + tgl_dc3co_flush(intel_dp, frontbuffer_bits, origin);
> + continue;
> + }
> +
> + mutex_lock(&intel_dp->psr.lock);
> + if (!intel_dp->psr.enabled) {
> + mutex_unlock(&intel_dp->psr.lock);
> + continue;
> + }
> +
> + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
> + intel_dp->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
> +
> + /* By definition flush = invalidate + flush */
> + if (frontbuffer_bits)
> + psr_force_hw_tracking_exit(intel_dp);
> +
> + if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
> + schedule_work(&intel_dp->psr.work);
> + mutex_unlock(&intel_dp->psr.lock);
> + }
> }
> -
> - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
> - dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
> -
> - /* By definition flush = invalidate + flush */
> - if (frontbuffer_bits)
> - psr_force_hw_tracking_exit(dev_priv);
> -
> - if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
> - schedule_work(&dev_priv->psr.work);
> - mutex_unlock(&dev_priv->psr.lock);
> }
>
> /**
> * intel_psr_init - Init basic PSR work and mutex.
> - * @dev_priv: i915 device private
> + * @intel_dp: Intel DP
> *
> - * This function is called only once at driver load to initialize basic
> - * PSR stuff.
> + * This function is called after the initializing connector.
> + * (the initializing of connector treats the handling of connector capabilities)
> + * And it initializes basic PSR stuff for each DP Encoder.
> */
> -void intel_psr_init(struct drm_i915_private *dev_priv)
> +void intel_psr_init(struct intel_dp *intel_dp)
> {
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> if (!HAS_PSR(dev_priv))
> return;
>
> - if (!dev_priv->psr.sink_support)
> + if (!intel_dp->psr.sink_support)
> return;
>
> if (IS_HASWELL(dev_priv))
> @@ -1715,14 +1755,14 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
> /* Set link_standby x link_off defaults */
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> /* HSW and BDW require workarounds that we don't implement. */
> - dev_priv->psr.link_standby = false;
> + intel_dp->psr.link_standby = false;
> else if (INTEL_GEN(dev_priv) < 12)
> /* For new platforms up to TGL let's respect VBT back again */
> - dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
> + intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link;
>
> - INIT_WORK(&dev_priv->psr.work, intel_psr_work);
> - INIT_DELAYED_WORK(&dev_priv->psr.dc3co_work, tgl_dc3co_disable_work);
> - mutex_init(&dev_priv->psr.lock);
> + INIT_WORK(&intel_dp->psr.work, intel_psr_work);
> + INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
> + mutex_init(&intel_dp->psr.lock);
> }
>
> static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
> @@ -1748,7 +1788,7 @@ static void psr_alpm_check(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct drm_dp_aux *aux = &intel_dp->aux;
> - struct i915_psr *psr = &dev_priv->psr;
> + struct intel_psr *psr = &intel_dp->psr;
> u8 val;
> int r;
>
> @@ -1775,7 +1815,7 @@ static void psr_alpm_check(struct intel_dp *intel_dp)
> static void psr_capability_changed_check(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct i915_psr *psr = &dev_priv->psr;
> + struct intel_psr *psr = &intel_dp->psr;
> u8 val;
> int r;
>
> @@ -1799,18 +1839,18 @@ static void psr_capability_changed_check(struct intel_dp *intel_dp)
> void intel_psr_short_pulse(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct i915_psr *psr = &dev_priv->psr;
> + struct intel_psr *psr = &intel_dp->psr;
> u8 status, error_status;
> const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
> DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
> DP_PSR_LINK_CRC_ERROR;
>
> - if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
> + if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp))
> return;
>
> mutex_lock(&psr->lock);
>
> - if (!psr->enabled || psr->dp != intel_dp)
> + if (!psr->enabled)
> goto exit;
>
> if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
> @@ -1853,15 +1893,14 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
>
> bool intel_psr_enabled(struct intel_dp *intel_dp)
> {
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> bool ret;
>
> - if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
> + if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp))
> return false;
>
> - mutex_lock(&dev_priv->psr.lock);
> - ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled);
> - mutex_unlock(&dev_priv->psr.lock);
> + mutex_lock(&intel_dp->psr.lock);
> + ret = intel_dp->psr.enabled;
> + mutex_unlock(&intel_dp->psr.lock);
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 0a517978e8af..03eb19547d09 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -18,7 +18,7 @@ struct intel_atomic_state;
> struct intel_plane_state;
> struct intel_plane;
>
> -#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
> +#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && intel_dp->psr.sink_support)
> void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> void intel_psr_enable(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> @@ -28,24 +28,24 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> void intel_psr_update(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state);
> -int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);
> +int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);
> void intel_psr_invalidate(struct drm_i915_private *dev_priv,
> unsigned frontbuffer_bits,
> enum fb_op_origin origin);
> void intel_psr_flush(struct drm_i915_private *dev_priv,
> unsigned frontbuffer_bits,
> enum fb_op_origin origin);
> -void intel_psr_init(struct drm_i915_private *dev_priv);
> +void intel_psr_init(struct intel_dp *intel_dp);
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state);
> -void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
> +void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
> void intel_psr_short_pulse(struct intel_dp *intel_dp);
> -int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
> - u32 *out_value);
> +void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
> bool intel_psr_enabled(struct intel_dp *intel_dp);
> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> -void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state);
> +void intel_psr2_program_trans_man_trk_ctl(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state);
> void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index b6deeb338477..ccd86f168357 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -92,7 +92,6 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
> bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
> DEFINE_WAIT(wait);
> - u32 psr_status;
>
> if (new_crtc_state->uapi.async_flip)
> return;
> @@ -117,10 +116,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
> * VBL interrupts will start the PSR exit and prevent a PSR
> * re-entry as well.
> */
> - if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
> - drm_err(&dev_priv->drm,
> - "PSR idle timed out 0x%x, atomic update may fail\n",
> - psr_status);
> + intel_psr_wait_for_idle(new_crtc_state);
>
> local_irq_disable();
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 15be8debae54..5a40295260c2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -475,42 +475,6 @@ struct i915_drrs {
> enum drrs_support_type type;
> };
>
> -struct i915_psr {
> - struct mutex lock;
> -
> -#define I915_PSR_DEBUG_MODE_MASK 0x0f
> -#define I915_PSR_DEBUG_DEFAULT 0x00
> -#define I915_PSR_DEBUG_DISABLE 0x01
> -#define I915_PSR_DEBUG_ENABLE 0x02
> -#define I915_PSR_DEBUG_FORCE_PSR1 0x03
> -#define I915_PSR_DEBUG_IRQ 0x10
> -
> - u32 debug;
> - bool sink_support;
> - bool enabled;
> - struct intel_dp *dp;
> - enum pipe pipe;
> - enum transcoder transcoder;
> - bool active;
> - struct work_struct work;
> - unsigned busy_frontbuffer_bits;
> - bool sink_psr2_support;
> - bool link_standby;
> - bool colorimetry_support;
> - bool psr2_enabled;
> - bool psr2_sel_fetch_enabled;
> - u8 sink_sync_latency;
> - ktime_t last_entry_attempt;
> - ktime_t last_exit;
> - bool sink_not_reliable;
> - bool irq_aux_error;
> - u16 su_x_granularity;
> - bool dc3co_enabled;
> - u32 dc3co_exit_delay;
> - struct delayed_work dc3co_work;
> - struct drm_dp_vsc_sdp vsc;
> -};
> -
> #define QUIRK_LVDS_SSC_DISABLE (1<<1)
> #define QUIRK_INVERT_BRIGHTNESS (1<<2)
> #define QUIRK_BACKLIGHT_PRESENT (1<<3)
> @@ -1041,8 +1005,6 @@ struct drm_i915_private {
>
> struct i915_power_domains power_domains;
>
> - struct i915_psr psr;
> -
> struct i915_gpu_error gpu_error;
>
> struct drm_i915_gem_object *vlv_pctx;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e0eb32bd9607..6d43298c46dd 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2057,10 +2057,20 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
> ivb_err_int_handler(dev_priv);
>
> if (de_iir & DE_EDP_PSR_INT_HSW) {
> - u32 psr_iir = I915_READ(EDP_PSR_IIR);
> + struct intel_encoder *encoder;
>
> - intel_psr_irq_handler(dev_priv, psr_iir);
> - I915_WRITE(EDP_PSR_IIR, psr_iir);
> + for_each_intel_dp(&dev_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + if (encoder->type == INTEL_OUTPUT_EDP &&
> + CAN_PSR(intel_dp)) {
> + u32 psr_iir = I915_READ(EDP_PSR_IIR);
> +
> + intel_psr_irq_handler(intel_dp, psr_iir);
> + I915_WRITE(EDP_PSR_IIR, psr_iir);
> + break;
> + }
> + }
> }
>
> if (de_iir & DE_AUX_CHANNEL_A_IVB)
> @@ -2268,21 +2278,34 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> }
>
> if (iir & GEN8_DE_EDP_PSR) {
> + struct intel_encoder *encoder;
> u32 psr_iir;
> i915_reg_t iir_reg;
>
> - if (INTEL_GEN(dev_priv) >= 12)
> - iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder);
> - else
> - iir_reg = EDP_PSR_IIR;
> + for_each_intel_dp(&dev_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> - psr_iir = I915_READ(iir_reg);
> - I915_WRITE(iir_reg, psr_iir);
> + if (INTEL_GEN(dev_priv) >= 12 && CAN_PSR(intel_dp)) {
> + iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder);
> + } else if (encoder->type == INTEL_OUTPUT_EDP &&
> + CAN_PSR(intel_dp)) {
> + iir_reg = EDP_PSR_IIR;
> + } else {
> + continue;
> + }
> +
> + psr_iir = I915_READ(iir_reg);
> + I915_WRITE(iir_reg, psr_iir);
> +
> + if (psr_iir)
> + found = true;
>
> - if (psr_iir)
> - found = true;
> + intel_psr_irq_handler(intel_dp, psr_iir);
>
> - intel_psr_irq_handler(dev_priv, psr_iir);
> + /* prior GEN12 only have one EDP PSR */
> + if (INTEL_GEN(dev_priv) < 12)
> + break;
> + }
> }
>
> if (!found)
> --
> 2.25.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders
2020-12-04 16:38 ` [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Anshuman Gupta
@ 2020-12-11 10:22 ` Mun, Gwan-gyeong
0 siblings, 0 replies; 17+ messages in thread
From: Mun, Gwan-gyeong @ 2020-12-11 10:22 UTC (permalink / raw)
To: Gupta, Anshuman; +Cc: intel-gfx
On Fri, 2020-12-04 at 22:08 +0530, Anshuman Gupta wrote:
> On 2020-11-06 at 15:44:42 +0530, Gwan-gyeong Mun wrote:
> > It is a preliminary work for supporting multiple EDP PSR and
> > DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> > supportable PSR.
> > And this moves and renames the i915_psr structure of
> > drm_i915_private's to
> > intel_dp's intel_psr structure.
> > It also causes changes in PSR interrupt handling routine for
> > supporting
> > multiple transcoders. But it does not change the scenario and
> > timing of
> > enabling and disabling PSR.
> Could you please break this patch, it can be break in following
> parts.
> 1. psr init path
> 2. atomic commit path
> 3. irq path
> 3. debugfs path
>
Hi,
Thank you for checking the patch.
Because the i915_psr structure of drm_i915_private's has moved to
intel_dp's intel_psr structure,
In order to be able to compile the patch, all of the affected code has
been included.
So it's hard to split what you mentioned.
therefore this patch does not include a new feature except supporting
multiple transcoder's psr.
> There are couple of comments, see below.
> > v2: Fix indentation and add comments
> > v3: Remove Blank line
> > v4: Rebased
> >
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 5 +
> > drivers/gpu/drm/i915/display/intel_display.c | 4 -
> > .../drm/i915/display/intel_display_debugfs.c | 111 ++--
> > .../drm/i915/display/intel_display_types.h | 38 ++
> > drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
> > drivers/gpu/drm/i915/display/intel_psr.c | 585 ++++++++++--
> > ------
> > drivers/gpu/drm/i915/display/intel_psr.h | 14 +-
> > drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
> > drivers/gpu/drm/i915/i915_drv.h | 38 --
> > drivers/gpu/drm/i915/i915_irq.c | 47 +-
> > 10 files changed, 491 insertions(+), 380 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 19b16517a502..983781ce3683 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4127,7 +4127,10 @@ static void intel_ddi_update_pipe_dp(struct
> > intel_atomic_state *state,
> >
> > intel_ddi_set_dp_msa(crtc_state, conn_state);
> >
> > + //TODO: move PSR related functions into intel_psr_update()
> > + intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
> > intel_psr_update(intel_dp, crtc_state, conn_state);
> > +
> > intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> > intel_edp_drrs_update(intel_dp, crtc_state);
> >
> > @@ -5275,6 +5278,8 @@ void intel_ddi_init(struct drm_i915_private
> > *dev_priv, enum port port)
> > goto err;
> >
> > dig_port->hpd_pulse = intel_dp_hpd_pulse;
> > +
> > + intel_psr_init(&dig_port->dp);
> IMHO this should be called from intel_dp_init_connector.
Your recommendation seems better, I'll update it.
> > }
> >
> > /* In theory we don't need the encoder->type check, but leave
> > it just in
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 8c4687b19814..466923a54370 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15506,8 +15506,6 @@ static void commit_pipe_config(struct
> > intel_atomic_state *state,
> >
> > if (new_crtc_state->update_pipe)
> > intel_pipe_fastset(old_crtc_state,
> > new_crtc_state);
> > -
> > - intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
> > }
> >
> > if (dev_priv->display.atomic_update_watermarks)
> > @@ -17435,8 +17433,6 @@ static void intel_setup_outputs(struct
> > drm_i915_private *dev_priv)
> > intel_dvo_init(dev_priv);
> > }
> >
> > - intel_psr_init(dev_priv);
> > -
> > for_each_intel_encoder(&dev_priv->drm, encoder) {
> > encoder->base.possible_crtcs =
> > intel_encoder_possible_crtcs(encoder);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index cfb4c1474982..8402e6ac9f76 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -248,18 +248,17 @@ static int i915_psr_sink_status_show(struct
> > seq_file *m, void *data)
> > "sink internal error",
> > };
> > struct drm_connector *connector = m->private;
> > - struct drm_i915_private *dev_priv = to_i915(connector->dev);
> > struct intel_dp *intel_dp =
> > intel_attached_dp(to_intel_connector(connector));
> > int ret;
> >
> > - if (!CAN_PSR(dev_priv)) {
> > - seq_puts(m, "PSR Unsupported\n");
> > + if (connector->status != connector_status_connected)
> > return -ENODEV;
> > - }
> >
> > - if (connector->status != connector_status_connected)
> > + if (!CAN_PSR(intel_dp)) {
> > + seq_puts(m, "PSR Unsupported\n");
> > return -ENODEV;
> > + }
> >
> > ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
> >
> > @@ -279,12 +278,13 @@ static int i915_psr_sink_status_show(struct
> > seq_file *m, void *data)
> > DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
> >
> > static void
> > -psr_source_status(struct drm_i915_private *dev_priv, struct
> > seq_file *m)
> > +psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
> > {
> > u32 val, status_val;
> > const char *status = "unknown";
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > - if (dev_priv->psr.psr2_enabled) {
> > + if (intel_dp->psr.psr2_enabled) {
> > static const char * const live_status[] = {
> > "IDLE",
> > "CAPTURE",
> > @@ -299,7 +299,7 @@ psr_source_status(struct drm_i915_private
> > *dev_priv, struct seq_file *m)
> > "TG_ON"
> > };
> > val = intel_de_read(dev_priv,
> > - EDP_PSR2_STATUS(dev_priv-
> > >psr.transcoder));
> > + EDP_PSR2_STATUS(intel_dp-
> > >psr.transcoder));
> > status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> > EDP_PSR2_STATUS_STATE_SHIFT;
> > if (status_val < ARRAY_SIZE(live_status))
> > @@ -316,7 +316,7 @@ psr_source_status(struct drm_i915_private
> > *dev_priv, struct seq_file *m)
> > "SRDENT_ON",
> > };
> > val = intel_de_read(dev_priv,
> > - EDP_PSR_STATUS(dev_priv-
> > >psr.transcoder));
> > + EDP_PSR_STATUS(intel_dp-
> > >psr.transcoder));
> > status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
> > EDP_PSR_STATUS_STATE_SHIFT;
> > if (status_val < ARRAY_SIZE(live_status))
> > @@ -326,21 +326,18 @@ psr_source_status(struct drm_i915_private
> > *dev_priv, struct seq_file *m)
> > seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
> > }
> >
> > -static int i915_edp_psr_status(struct seq_file *m, void *data)
> > +static int intel_psr_status(struct seq_file *m, struct intel_dp
> > *intel_dp)
> > {
> > - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> > - struct i915_psr *psr = &dev_priv->psr;
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + struct intel_psr *psr = &intel_dp->psr;
> > intel_wakeref_t wakeref;
> > const char *status;
> > bool enabled;
> > u32 val;
> >
> > - if (!HAS_PSR(dev_priv))
> > - return -ENODEV;
> > -
> > seq_printf(m, "Sink support: %s", yesno(psr->sink_support));
> > - if (psr->dp)
> > - seq_printf(m, " [0x%02x]", psr->dp->psr_dpcd[0]);
> > + if (psr->sink_support)
> > + seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
> > seq_puts(m, "\n");
> >
> > if (!psr->sink_support)
> > @@ -364,16 +361,16 @@ static int i915_edp_psr_status(struct
> > seq_file *m, void *data)
> >
> > if (psr->psr2_enabled) {
> > val = intel_de_read(dev_priv,
> > - EDP_PSR2_CTL(dev_priv-
> > >psr.transcoder));
> > + EDP_PSR2_CTL(intel_dp-
> > >psr.transcoder));
> > enabled = val & EDP_PSR2_ENABLE;
> > } else {
> > val = intel_de_read(dev_priv,
> > - EDP_PSR_CTL(dev_priv-
> > >psr.transcoder));
> > + EDP_PSR_CTL(intel_dp-
> > >psr.transcoder));
> > enabled = val & EDP_PSR_ENABLE;
> > }
> > seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
> > enableddisabled(enabled), val);
> > - psr_source_status(dev_priv, m);
> > + psr_source_status(intel_dp, m);
> > seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
> > psr->busy_frontbuffer_bits);
> >
> > @@ -382,7 +379,7 @@ static int i915_edp_psr_status(struct seq_file
> > *m, void *data)
> > */
> > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > val = intel_de_read(dev_priv,
> > - EDP_PSR_PERF_CNT(dev_priv-
> > >psr.transcoder));
> > + EDP_PSR_PERF_CNT(intel_dp-
> > >psr.transcoder));
> > val &= EDP_PSR_PERF_CNT_MASK;
> > seq_printf(m, "Performance counter: %u\n", val);
> > }
> > @@ -403,7 +400,7 @@ static int i915_edp_psr_status(struct seq_file
> > *m, void *data)
> > */
> > for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame +=
> > 3) {
> > val = intel_de_read(dev_priv,
> > - PSR2_SU_STATUS(dev_priv-
> > >psr.transcoder, frame));
> > + PSR2_SU_STATUS(intel_dp-
> > >psr.transcoder, frame));
> > su_frames_val[frame / 3] = val;
> > }
> >
> > @@ -429,23 +426,57 @@ static int i915_edp_psr_status(struct
> > seq_file *m, void *data)
> > return 0;
> > }
> >
> > +static int i915_edp_psr_status(struct seq_file *m, void *data)
> > +{
> > + struct drm_i915_private *dev_priv = node_to_i915(m->private);
> > + struct intel_encoder *encoder;
> > + struct intel_dp *intel_dp = NULL;
> > +
> > + if (!HAS_PSR(dev_priv))
> > + return -ENODEV;
> > +
> > + /* Find the first EDP */
> > + for_each_intel_dp(&dev_priv->drm, encoder) {
> > + if (encoder->type == INTEL_OUTPUT_EDP) {
> > + intel_dp = enc_to_intel_dp(encoder);
> > + break;
> > + }
> > + }
> > +
> > + if (!intel_dp)
> > + return -ENODEV;
> > +
> > + return intel_psr_status(m, intel_dp);
> > +}
> > +
> > static int
> > i915_edp_psr_debug_set(void *data, u64 val)
> > {
> > struct drm_i915_private *dev_priv = data;
> > intel_wakeref_t wakeref;
> > - int ret;
> > + int ret = -ENODEV;
> > + struct intel_encoder *encoder;
> >
> > - if (!CAN_PSR(dev_priv))
> > - return -ENODEV;
> > + if (!HAS_PSR(dev_priv))
> > + return ret;
> >
> > - drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n",
> > val);
> > + for_each_intel_dp(&dev_priv->drm, encoder) {
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >
> > - wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> > + if (!CAN_PSR(intel_dp))
> > + continue;
> >
> > - ret = intel_psr_debug_set(dev_priv, val);
> > + if (encoder->type == INTEL_OUTPUT_EDP) {
> > + drm_dbg_kms(&dev_priv->drm, "Setting PSR debug
> > to %llx\n", val);
> >
> > - intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> > + wakeref = intel_runtime_pm_get(&dev_priv-
> > >runtime_pm);
> > +
> > + // TODO: split to each transcoder's PSR debug
> > state
> > + ret = intel_psr_debug_set(intel_dp, val);
> > +
> > + intel_runtime_pm_put(&dev_priv->runtime_pm,
> > wakeref);
> > + }
> > + }
> >
> > return ret;
> > }
> > @@ -454,12 +485,25 @@ static int
> > i915_edp_psr_debug_get(void *data, u64 *val)
> > {
> > struct drm_i915_private *dev_priv = data;
> > + struct intel_encoder *encoder;
> >
> > - if (!CAN_PSR(dev_priv))
> > + if (!HAS_PSR(dev_priv))
> > return -ENODEV;
> >
> > - *val = READ_ONCE(dev_priv->psr.debug);
> > - return 0;
> > + for_each_intel_dp(&dev_priv->drm, encoder) {
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > + if (!CAN_PSR(intel_dp))
> > + continue;
> > +
> > + // TODO: split to each transcoder's PSR debug state
> > + if (encoder->type == INTEL_OUTPUT_EDP) {
> > + *val = READ_ONCE(intel_dp->psr.debug);
> > + return 0;
> > + }
> > + }
> > +
> > + return -ENODEV;
> > }
> >
> > DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
> > @@ -1103,9 +1147,6 @@ static void drrs_status_per_crtc(struct
> > seq_file *m,
> > /* disable_drrs() will make drrs->dp NULL */
> > if (!drrs->dp) {
> > seq_puts(m, "Idleness DRRS: Disabled\n");
> > - if (dev_priv->psr.enabled)
> > - seq_puts(m,
> > - "\tAs PSR is enabled, DRRS is not
> > enabled\n");
> > mutex_unlock(&drrs->mutex);
> > return;
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index f6f0626649e0..2e40fcbab2aa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1286,6 +1286,42 @@ struct intel_dp_compliance {
> > u8 test_lane_count;
> > };
> >
> > +struct intel_psr {
> > + /* Mutex for PSR state of the transcoder */
> > + struct mutex lock;
> > +
> > +#define I915_PSR_DEBUG_MODE_MASK 0x0f
> > +#define I915_PSR_DEBUG_DEFAULT 0x00
> > +#define I915_PSR_DEBUG_DISABLE 0x01
> > +#define I915_PSR_DEBUG_ENABLE 0x02
> > +#define I915_PSR_DEBUG_FORCE_PSR1 0x03
> > +#define I915_PSR_DEBUG_IRQ 0x10
> > +
> > + u32 debug;
> > + bool sink_support;
> > + bool enabled;
> > + enum pipe pipe;
> > + enum transcoder transcoder;
> > + bool active;
> > + struct work_struct work;
> > + unsigned int busy_frontbuffer_bits;
> > + bool sink_psr2_support;
> > + bool link_standby;
> > + bool colorimetry_support;
> > + bool psr2_enabled;
> > + bool psr2_sel_fetch_enabled;
> > + u8 sink_sync_latency;
> > + ktime_t last_entry_attempt;
> > + ktime_t last_exit;
> > + bool sink_not_reliable;
> > + bool irq_aux_error;
> > + u16 su_x_granularity;
> > + bool dc3co_enabled;
> > + u32 dc3co_exit_delay;
> > + struct delayed_work dc3co_work;
> > + struct drm_dp_vsc_sdp vsc;
> > +};
> > +
> > struct intel_dp {
> > i915_reg_t output_reg;
> > u32 DP;
> > @@ -1406,6 +1442,8 @@ struct intel_dp {
> >
> > bool hobl_failed;
> > bool hobl_active;
> > +
> > + struct intel_psr psr;
> > };
> >
> > enum lspcon_vendor {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 3b0dbda5919a..64abc9d037f8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2640,12 +2640,10 @@ void intel_dp_compute_psr_vsc_sdp(struct
> > intel_dp *intel_dp,
> > const struct drm_connector_state
> > *conn_state,
> > struct drm_dp_vsc_sdp *vsc)
> > {
> > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > -
> > vsc->sdp_type = DP_SDP_VSC;
> >
> > - if (dev_priv->psr.psr2_enabled) {
> > - if (dev_priv->psr.colorimetry_support &&
> > + if (intel_dp->psr.psr2_enabled) {
> > + if (intel_dp->psr.colorimetry_support &&
> > intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > /* [PSR2, +Colorimetry] */
> > intel_dp_compute_vsc_colorimetry(crtc_state,
> > conn_state,
> > @@ -3778,7 +3776,7 @@ bool intel_dp_initial_fastset_check(struct
> > intel_encoder *encoder,
> > return false;
> > }
> >
> > - if (CAN_PSR(i915) && intel_dp_is_edp(intel_dp)) {
> > + if (CAN_PSR(intel_dp) && intel_dp_is_edp(intel_dp)) {
> > drm_dbg_kms(&i915->drm, "Forcing full modeset to
> > compute PSR state\n");
> > crtc_state->uapi.mode_changed = true;
> > return false;
> > @@ -7978,6 +7976,17 @@ static void
> > intel_dp_modeset_retry_work_fn(struct work_struct *work)
> > drm_kms_helper_hotplug_event(connector->dev);
> > }
> >
> > +static void intel_dp_update_pipe(struct intel_atomic_state *state,
> > + struct intel_encoder *encoder,
> > + const struct intel_crtc_state
> > *crtc_state,
> > + const struct drm_connector_state
> > *conn_state)
> > +{
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > + intel_panel_update_backlight(state, encoder, crtc_state,
> > conn_state);
> > + intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
> > +}
> > +
> > bool
> > intel_dp_init_connector(struct intel_digital_port *dig_port,
> > struct intel_connector *intel_connector)
> > @@ -8133,7 +8142,7 @@ bool intel_dp_init(struct drm_i915_private
> > *dev_priv,
> > intel_encoder->get_config = intel_dp_get_config;
> > intel_encoder->sync_state = intel_dp_sync_state;
> > intel_encoder->initial_fastset_check =
> > intel_dp_initial_fastset_check;
> > - intel_encoder->update_pipe = intel_panel_update_backlight;
> > + intel_encoder->update_pipe = intel_dp_update_pipe;
> > intel_encoder->suspend = intel_dp_encoder_suspend;
> > intel_encoder->shutdown = intel_dp_encoder_shutdown;
> > if (IS_CHERRYVIEW(dev_priv)) {
> > @@ -8220,6 +8229,8 @@ bool intel_dp_init(struct drm_i915_private
> > *dev_priv,
> > if (!intel_dp_init_connector(dig_port, intel_connector))
> > goto err_init_connector;
> >
> > + intel_psr_init(&dig_port->dp);
> IMHO this will not get called for DDI encoder intel_dp_init_connector
> is correcr place
> to initialize it.
>
> Thanks,
> Anshuman Gupta.
> > +
> > return true;
> >
> > err_init_connector:
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index b3631b722de3..8d858d56c736 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -79,11 +79,13 @@
> > * use page flips.
> > */
> >
> > -static bool psr_global_enabled(struct drm_i915_private *i915)
> > +static bool psr_global_enabled(struct intel_dp *intel_dp)
> > {
> > - switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> > case I915_PSR_DEBUG_DEFAULT:
> > - return i915->params.enable_psr;
> > + return dev_priv->params.enable_psr;
> > case I915_PSR_DEBUG_DISABLE:
> > return false;
> > default:
> > @@ -91,9 +93,9 @@ static bool psr_global_enabled(struct
> > drm_i915_private *i915)
> > }
> > }
> >
> > -static bool psr2_global_enabled(struct drm_i915_private *dev_priv)
> > +static bool psr2_global_enabled(struct intel_dp *intel_dp)
> > {
> > - switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> > + switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> > case I915_PSR_DEBUG_DISABLE:
> > case I915_PSR_DEBUG_FORCE_PSR1:
> > return false;
> > @@ -102,11 +104,12 @@ static bool psr2_global_enabled(struct
> > drm_i915_private *dev_priv)
> > }
> > }
> >
> > -static void psr_irq_control(struct drm_i915_private *dev_priv)
> > +static void psr_irq_control(struct intel_dp *intel_dp)
> > {
> > enum transcoder trans_shift;
> > u32 mask, val;
> > i915_reg_t imr_reg;
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > /*
> > * gen12+ has registers relative to transcoder and one per
> > transcoder
> > @@ -115,14 +118,14 @@ static void psr_irq_control(struct
> > drm_i915_private *dev_priv)
> > */
> > if (INTEL_GEN(dev_priv) >= 12) {
> > trans_shift = 0;
> > - imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
> > + imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> > } else {
> > - trans_shift = dev_priv->psr.transcoder;
> > + trans_shift = intel_dp->psr.transcoder;
> > imr_reg = EDP_PSR_IMR;
> > }
> >
> > mask = EDP_PSR_ERROR(trans_shift);
> > - if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
> > + if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
> > mask |= EDP_PSR_POST_EXIT(trans_shift) |
> > EDP_PSR_PRE_ENTRY(trans_shift);
> >
> > @@ -171,38 +174,37 @@ static void psr_event_print(struct
> > drm_i915_private *i915,
> > drm_dbg_kms(&i915->drm, "\tPSR disabled\n");
> > }
> >
> > -void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32
> > psr_iir)
> > +void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
> > {
> > - enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> > enum transcoder trans_shift;
> > i915_reg_t imr_reg;
> > ktime_t time_ns = ktime_get();
> >
> > if (INTEL_GEN(dev_priv) >= 12) {
> > trans_shift = 0;
> > - imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
> > + imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
> > } else {
> > - trans_shift = dev_priv->psr.transcoder;
> > + trans_shift = intel_dp->psr.transcoder;
> > imr_reg = EDP_PSR_IMR;
> > }
> >
> > if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
> > - dev_priv->psr.last_entry_attempt = time_ns;
> > - drm_dbg_kms(&dev_priv->drm,
> > - "[transcoder %s] PSR entry attempt in 2
> > vblanks\n",
> > - transcoder_name(cpu_transcoder));
> > + intel_dp->psr.last_entry_attempt = time_ns;
> > + DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2
> > vblanks\n",
> > + transcoder_name(cpu_transcoder));
> > }
> >
> > if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
> > - dev_priv->psr.last_exit = time_ns;
> > - drm_dbg_kms(&dev_priv->drm,
> > - "[transcoder %s] PSR exit completed\n",
> > - transcoder_name(cpu_transcoder));
> > + intel_dp->psr.last_exit = time_ns;
> > + DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
> > + transcoder_name(cpu_transcoder));
> >
> > if (INTEL_GEN(dev_priv) >= 9) {
> > u32 val = intel_de_read(dev_priv,
> > PSR_EVENT(cpu_transcode
> > r));
> > - bool psr2_enabled = dev_priv->psr.psr2_enabled;
> > + bool psr2_enabled = intel_dp->psr.psr2_enabled;
> >
> > intel_de_write(dev_priv,
> > PSR_EVENT(cpu_transcoder),
> > val);
> > @@ -213,10 +215,10 @@ void intel_psr_irq_handler(struct
> > drm_i915_private *dev_priv, u32 psr_iir)
> > if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
> > u32 val;
> >
> > - drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux
> > error\n",
> > + DRM_WARN("[transcoder %s] PSR aux error\n",
> > transcoder_name(cpu_transcoder));
> >
> > - dev_priv->psr.irq_aux_error = true;
> > + intel_dp->psr.irq_aux_error = true;
> >
> > /*
> > * If this interruption is not masked it will keep
> > @@ -230,7 +232,7 @@ void intel_psr_irq_handler(struct
> > drm_i915_private *dev_priv, u32 psr_iir)
> > val |= EDP_PSR_ERROR(trans_shift);
> > intel_de_write(dev_priv, imr_reg, val);
> >
> > - schedule_work(&dev_priv->psr.work);
> > + schedule_work(&intel_dp->psr.work);
> > }
> > }
> >
> > @@ -291,12 +293,6 @@ void intel_psr_init_dpcd(struct intel_dp
> > *intel_dp)
> > struct drm_i915_private *dev_priv =
> > to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
> >
> > - if (dev_priv->psr.dp) {
> > - drm_warn(&dev_priv->drm,
> > - "More than one eDP panel found, PSR support
> > should be extended\n");
> > - return;
> > - }
> > -
> > drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp-
> > >psr_dpcd,
> > sizeof(intel_dp->psr_dpcd));
> >
> > @@ -317,12 +313,10 @@ void intel_psr_init_dpcd(struct intel_dp
> > *intel_dp)
> > return;
> > }
> >
> > - dev_priv->psr.sink_support = true;
> > - dev_priv->psr.sink_sync_latency =
> > + intel_dp->psr.sink_support = true;
> > + intel_dp->psr.sink_sync_latency =
> > intel_dp_get_sink_sync_latency(intel_dp);
> >
> > - dev_priv->psr.dp = intel_dp;
> > -
> > if (INTEL_GEN(dev_priv) >= 9 &&
> > (intel_dp->psr_dpcd[0] ==
> > DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
> > bool y_req = intel_dp->psr_dpcd[1] &
> > @@ -340,14 +334,14 @@ void intel_psr_init_dpcd(struct intel_dp
> > *intel_dp)
> > * Y-coordinate requirement panels we would need to
> > enable
> > * GTC first.
> > */
> > - dev_priv->psr.sink_psr2_support = y_req && alpm;
> > + intel_dp->psr.sink_psr2_support = y_req && alpm;
> > drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
> > - dev_priv->psr.sink_psr2_support ? "" : "not
> > ");
> > + intel_dp->psr.sink_psr2_support ? "" : "not
> > ");
> >
> > - if (dev_priv->psr.sink_psr2_support) {
> > - dev_priv->psr.colorimetry_support =
> > + if (intel_dp->psr.sink_psr2_support) {
> > + intel_dp->psr.colorimetry_support =
> > intel_dp_get_colorimetry_status(intel_d
> > p);
> > - dev_priv->psr.su_x_granularity =
> > + intel_dp->psr.su_x_granularity =
> > intel_dp_get_su_x_granulartiy(intel_dp)
> > ;
> > }
> > }
> > @@ -373,7 +367,7 @@ static void hsw_psr_setup_aux(struct intel_dp
> > *intel_dp)
> > BUILD_BUG_ON(sizeof(aux_msg) > 20);
> > for (i = 0; i < sizeof(aux_msg); i += 4)
> > intel_de_write(dev_priv,
> > - EDP_PSR_AUX_DATA(dev_priv-
> > >psr.transcoder, i >> 2),
> > + EDP_PSR_AUX_DATA(intel_dp-
> > >psr.transcoder, i >> 2),
> > intel_dp_pack_aux(&aux_msg[i],
> > sizeof(aux_msg) - i));
> >
> > aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp,
> > 0);
> > @@ -384,7 +378,7 @@ static void hsw_psr_setup_aux(struct intel_dp
> > *intel_dp)
> >
> > /* Select only valid bits for SRD_AUX_CTL */
> > aux_ctl &= psr_aux_mask;
> > - intel_de_write(dev_priv, EDP_PSR_AUX_CTL(dev_priv-
> > >psr.transcoder),
> > + intel_de_write(dev_priv, EDP_PSR_AUX_CTL(intel_dp-
> > >psr.transcoder),
> > aux_ctl);
> > }
> >
> > @@ -394,14 +388,14 @@ static void intel_psr_enable_sink(struct
> > intel_dp *intel_dp)
> > u8 dpcd_val = DP_PSR_ENABLE;
> >
> > /* Enable ALPM at sink for psr2 */
> > - if (dev_priv->psr.psr2_enabled) {
> > + if (intel_dp->psr.psr2_enabled) {
> > drm_dp_dpcd_writeb(&intel_dp->aux,
> > DP_RECEIVER_ALPM_CONFIG,
> > DP_ALPM_ENABLE |
> > DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> >
> > dpcd_val |= DP_PSR_ENABLE_PSR2 |
> > DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> > } else {
> > - if (dev_priv->psr.link_standby)
> > + if (intel_dp->psr.link_standby)
> > dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> >
> > if (INTEL_GEN(dev_priv) >= 8)
> > @@ -464,7 +458,7 @@ static u8 psr_compute_idle_frames(struct
> > intel_dp *intel_dp)
> > * off-by-one issue that HW has in some cases.
> > */
> > idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > - idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> > + 1);
> > + idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency
> > + 1);
> >
> > if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
> > idle_frames = 0xf;
> > @@ -484,7 +478,7 @@ static void hsw_activate_psr1(struct intel_dp
> > *intel_dp)
> > if (IS_HASWELL(dev_priv))
> > val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> >
> > - if (dev_priv->psr.link_standby)
> > + if (intel_dp->psr.link_standby)
> > val |= EDP_PSR_LINK_STANDBY;
> >
> > val |= intel_psr1_get_tp_time(intel_dp);
> > @@ -492,9 +486,9 @@ static void hsw_activate_psr1(struct intel_dp
> > *intel_dp)
> > if (INTEL_GEN(dev_priv) >= 8)
> > val |= EDP_PSR_CRC_ENABLE;
> >
> > - val |= (intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv-
> > >psr.transcoder)) &
> > + val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp-
> > >psr.transcoder)) &
> > EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
> > - intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder),
> > val);
> > + intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder),
> > val);
> > }
> >
> > static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
> > @@ -529,7 +523,7 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > val |= EDP_Y_COORDINATE_ENABLE;
> >
> > - val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency
> > + 1);
> > + val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency
> > + 1);
> > val |= intel_psr2_get_tp_time(intel_dp);
> >
> > if (INTEL_GEN(dev_priv) >= 12) {
> > @@ -548,7 +542,7 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> > val |= EDP_PSR2_FAST_WAKE(7);
> > }
> >
> > - if (dev_priv->psr.psr2_sel_fetch_enabled) {
> > + if (intel_dp->psr.psr2_sel_fetch_enabled) {
> > /* WA 1408330847 */
> > if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0,
> > TGL_REVID_A0) ||
> > IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> > @@ -557,20 +551,20 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> > DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> >
> > intel_de_write(dev_priv,
> > - PSR2_MAN_TRK_CTL(dev_priv-
> > >psr.transcoder),
> > + PSR2_MAN_TRK_CTL(intel_dp-
> > >psr.transcoder),
> > PSR2_MAN_TRK_CTL_ENABLE);
> > } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> > intel_de_write(dev_priv,
> > - PSR2_MAN_TRK_CTL(dev_priv-
> > >psr.transcoder), 0);
> > + PSR2_MAN_TRK_CTL(intel_dp-
> > >psr.transcoder), 0);
> > }
> >
> > /*
> > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec
> > is
> > * recommending keep this bit unset while PSR2 is enabled.
> > */
> > - intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder),
> > 0);
> > + intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder),
> > 0);
> >
> > - intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv-
> > >psr.transcoder), val);
> > + intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp-
> > >psr.transcoder), val);
> > }
> >
> > static bool
> > @@ -593,55 +587,58 @@ static u32 intel_get_frame_time_us(const
> > struct intel_crtc_state *cstate)
> > drm_mode_vrefresh(&cstate-
> > >hw.adjusted_mode));
> > }
> >
> > -static void psr2_program_idle_frames(struct drm_i915_private
> > *dev_priv,
> > +static void psr2_program_idle_frames(struct intel_dp *intel_dp,
> > u32 idle_frames)
> > {
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > u32 val;
> >
> > idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
> > - val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv-
> > >psr.transcoder));
> > + val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp-
> > >psr.transcoder));
> > val &= ~EDP_PSR2_IDLE_FRAME_MASK;
> > val |= idle_frames;
> > - intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv-
> > >psr.transcoder), val);
> > + intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp-
> > >psr.transcoder), val);
> > }
> >
> > -static void tgl_psr2_enable_dc3co(struct drm_i915_private
> > *dev_priv)
> > +static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
> > {
> > - psr2_program_idle_frames(dev_priv, 0);
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + psr2_program_idle_frames(intel_dp, 0);
> > intel_display_power_set_target_dc_state(dev_priv,
> > DC_STATE_EN_DC3CO);
> > }
> >
> > -static void tgl_psr2_disable_dc3co(struct drm_i915_private
> > *dev_priv)
> > +static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
> > {
> > - struct intel_dp *intel_dp = dev_priv->psr.dp;
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > intel_display_power_set_target_dc_state(dev_priv,
> > DC_STATE_EN_UPTO_DC6);
> > - psr2_program_idle_frames(dev_priv,
> > psr_compute_idle_frames(intel_dp));
> > + psr2_program_idle_frames(intel_dp,
> > psr_compute_idle_frames(intel_dp));
> > }
> >
> > static void tgl_dc3co_disable_work(struct work_struct *work)
> > {
> > - struct drm_i915_private *dev_priv =
> > - container_of(work, typeof(*dev_priv),
> > psr.dc3co_work.work);
> > + struct intel_dp *intel_dp =
> > + container_of(work, typeof(*intel_dp),
> > psr.dc3co_work.work);
> >
> > - mutex_lock(&dev_priv->psr.lock);
> > + mutex_lock(&intel_dp->psr.lock);
> > /* If delayed work is pending, it is not idle */
> > - if (delayed_work_pending(&dev_priv->psr.dc3co_work))
> > + if (delayed_work_pending(&intel_dp->psr.dc3co_work))
> > goto unlock;
> >
> > - tgl_psr2_disable_dc3co(dev_priv);
> > + tgl_psr2_disable_dc3co(intel_dp);
> > unlock:
> > - mutex_unlock(&dev_priv->psr.lock);
> > + mutex_unlock(&intel_dp->psr.lock);
> > }
> >
> > -static void tgl_disallow_dc3co_on_psr2_exit(struct
> > drm_i915_private *dev_priv)
> > +static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp
> > *intel_dp)
> > {
> > - if (!dev_priv->psr.dc3co_enabled)
> > + if (!intel_dp->psr.dc3co_enabled)
> > return;
> >
> > - cancel_delayed_work(&dev_priv->psr.dc3co_work);
> > + cancel_delayed_work(&intel_dp->psr.dc3co_work);
> > /* Before PSR2 exit disallow dc3co*/
> > - tgl_psr2_disable_dc3co(dev_priv);
> > + tgl_psr2_disable_dc3co(intel_dp);
> > }
> >
> > static void
> > @@ -714,7 +711,7 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> > int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> > int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
> >
> > - if (!dev_priv->psr.sink_psr2_support)
> > + if (!intel_dp->psr.sink_psr2_support)
> > return false;
> >
> > if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder))
> > {
> > @@ -724,7 +721,7 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> > return false;
> > }
> >
> > - if (!psr2_global_enabled(dev_priv)) {
> > + if (!psr2_global_enabled(intel_dp)) {
> > drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
> > return false;
> > }
> > @@ -773,10 +770,10 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> > * only need to validate the SU block width is a multiple of
> > * x granularity.
> > */
> > - if (crtc_hdisplay % dev_priv->psr.su_x_granularity) {
> > + if (crtc_hdisplay % intel_dp->psr.su_x_granularity) {
> > drm_dbg_kms(&dev_priv->drm,
> > "PSR2 not enabled, hdisplay(%d) not
> > multiple of %d\n",
> > - crtc_hdisplay, dev_priv-
> > >psr.su_x_granularity);
> > + crtc_hdisplay, intel_dp-
> > >psr.su_x_granularity);
> > return false;
> > }
> >
> > @@ -811,13 +808,10 @@ void intel_psr_compute_config(struct intel_dp
> > *intel_dp,
> > &crtc_state->hw.adjusted_mode;
> > int psr_setup_time;
> >
> > - if (!CAN_PSR(dev_priv))
> > - return;
> > -
> > - if (intel_dp != dev_priv->psr.dp)
> > + if (!CAN_PSR(intel_dp))
> > return;
> >
> > - if (!psr_global_enabled(dev_priv)) {
> > + if (!psr_global_enabled(intel_dp)) {
> > drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
> > return;
> > }
> > @@ -834,7 +828,7 @@ void intel_psr_compute_config(struct intel_dp
> > *intel_dp,
> > return;
> > }
> >
> > - if (dev_priv->psr.sink_not_reliable) {
> > + if (intel_dp->psr.sink_not_reliable) {
> > drm_dbg_kms(&dev_priv->drm,
> > "PSR sink implementation is not
> > reliable\n");
> > return;
> > @@ -870,23 +864,24 @@ void intel_psr_compute_config(struct intel_dp
> > *intel_dp,
> > static void intel_psr_activate(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + enum transcoder transcoder = intel_dp->psr.transcoder;
> >
> > - if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder))
> > + if (transcoder_has_psr2(dev_priv, transcoder))
> > drm_WARN_ON(&dev_priv->drm,
> > - intel_de_read(dev_priv,
> > EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
> > + intel_de_read(dev_priv,
> > EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE);
> >
> > drm_WARN_ON(&dev_priv->drm,
> > - intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv-
> > >psr.transcoder)) & EDP_PSR_ENABLE);
> > - drm_WARN_ON(&dev_priv->drm, dev_priv->psr.active);
> > - lockdep_assert_held(&dev_priv->psr.lock);
> > + intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) &
> > EDP_PSR_ENABLE);
> > + drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
> > + lockdep_assert_held(&intel_dp->psr.lock);
> >
> > /* psr1 and psr2 are mutually exclusive.*/
> > - if (dev_priv->psr.psr2_enabled)
> > + if (intel_dp->psr.psr2_enabled)
> > hsw_activate_psr2(intel_dp);
> > else
> > hsw_activate_psr1(intel_dp);
> >
> > - dev_priv->psr.active = true;
> > + intel_dp->psr.active = true;
> > }
> >
> > static void intel_psr_enable_source(struct intel_dp *intel_dp,
> > @@ -902,7 +897,7 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > hsw_psr_setup_aux(intel_dp);
> >
> > - if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
> > + if (intel_dp->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
> > !IS_GEMINILAKE(dev_priv))) {
> > i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
> > u32 chicken = intel_de_read(dev_priv, reg);
> > @@ -926,10 +921,10 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> > if (INTEL_GEN(dev_priv) < 11)
> > mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
> >
> > - intel_de_write(dev_priv, EDP_PSR_DEBUG(dev_priv-
> > >psr.transcoder),
> > + intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp-
> > >psr.transcoder),
> > mask);
> >
> > - psr_irq_control(dev_priv);
> > + psr_irq_control(intel_dp);
> >
> > if (crtc_state->dc3co_exitline) {
> > u32 val;
> > @@ -947,30 +942,30 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> >
> > if (HAS_PSR_HW_TRACKING(dev_priv) &&
> > HAS_PSR2_SEL_FETCH(dev_priv))
> > intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > IGNORE_PSR2_HW_TRACKING,
> > - dev_priv->psr.psr2_sel_fetch_enabled ?
> > + intel_dp->psr.psr2_sel_fetch_enabled ?
> > IGNORE_PSR2_HW_TRACKING : 0);
> > }
> >
> > -static void intel_psr_enable_locked(struct drm_i915_private
> > *dev_priv,
> > +static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > const struct intel_crtc_state
> > *crtc_state,
> > const struct drm_connector_state
> > *conn_state)
> > {
> > - struct intel_dp *intel_dp = dev_priv->psr.dp;
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > struct intel_encoder *encoder = &dig_port->base;
> > u32 val;
> >
> > - drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
> > + drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> >
> > - dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
> > - dev_priv->psr.busy_frontbuffer_bits = 0;
> > - dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)-
> > >pipe;
> > - dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
> > - dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
> > + intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > + intel_dp->psr.busy_frontbuffer_bits = 0;
> > + intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)-
> > >pipe;
> > + intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
> > + intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> > /* DC5/DC6 requires at least 6 idle frames */
> > val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > 6);
> > - dev_priv->psr.dc3co_exit_delay = val;
> > - dev_priv->psr.psr2_sel_fetch_enabled = crtc_state-
> > >enable_psr2_sel_fetch;
> > + intel_dp->psr.dc3co_exit_delay = val;
> > + intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> > >enable_psr2_sel_fetch;
> >
> > /*
> > * If a PSR error happened and the driver is reloaded, the
> > EDP_PSR_IIR
> > @@ -982,27 +977,27 @@ static void intel_psr_enable_locked(struct
> > drm_i915_private *dev_priv,
> > */
> > if (INTEL_GEN(dev_priv) >= 12) {
> > val = intel_de_read(dev_priv,
> > - TRANS_PSR_IIR(dev_priv-
> > >psr.transcoder));
> > + TRANS_PSR_IIR(intel_dp-
> > >psr.transcoder));
> > val &= EDP_PSR_ERROR(0);
> > } else {
> > val = intel_de_read(dev_priv, EDP_PSR_IIR);
> > - val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
> > + val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
> > }
> > if (val) {
> > - dev_priv->psr.sink_not_reliable = true;
> > + intel_dp->psr.sink_not_reliable = true;
> > drm_dbg_kms(&dev_priv->drm,
> > "PSR interruption error set, not enabling
> > PSR\n");
> > return;
> > }
> >
> > drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> > - dev_priv->psr.psr2_enabled ? "2" : "1");
> > + intel_dp->psr.psr2_enabled ? "2" : "1");
> > intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> > - &dev_priv->psr.vsc);
> > - intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv-
> > >psr.vsc);
> > + &intel_dp->psr.vsc);
> > + intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp-
> > >psr.vsc);
> > intel_psr_enable_sink(intel_dp);
> > intel_psr_enable_source(intel_dp, crtc_state);
> > - dev_priv->psr.enabled = true;
> > + intel_dp->psr.enabled = true;
> >
> > intel_psr_activate(intel_dp);
> > }
> > @@ -1021,7 +1016,7 @@ void intel_psr_enable(struct intel_dp
> > *intel_dp,
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > - if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp)
> > + if (!CAN_PSR(intel_dp))
> > return;
> >
> > if (!crtc_state->has_psr)
> > @@ -1029,46 +1024,47 @@ void intel_psr_enable(struct intel_dp
> > *intel_dp,
> >
> > drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
> >
> > - mutex_lock(&dev_priv->psr.lock);
> > - intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
> > - mutex_unlock(&dev_priv->psr.lock);
> > + mutex_lock(&intel_dp->psr.lock);
> > + intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
> > + mutex_unlock(&intel_dp->psr.lock);
> > }
> >
> > -static void intel_psr_exit(struct drm_i915_private *dev_priv)
> > +static void intel_psr_exit(struct intel_dp *intel_dp)
> > {
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > u32 val;
> >
> > - if (!dev_priv->psr.active) {
> > - if (transcoder_has_psr2(dev_priv, dev_priv-
> > >psr.transcoder)) {
> > + if (!intel_dp->psr.active) {
> > + if (transcoder_has_psr2(dev_priv, intel_dp-
> > >psr.transcoder)) {
> > val = intel_de_read(dev_priv,
> > - EDP_PSR2_CTL(dev_priv-
> > >psr.transcoder));
> > + EDP_PSR2_CTL(intel_dp-
> > >psr.transcoder));
> > drm_WARN_ON(&dev_priv->drm, val &
> > EDP_PSR2_ENABLE);
> > }
> >
> > val = intel_de_read(dev_priv,
> > - EDP_PSR_CTL(dev_priv-
> > >psr.transcoder));
> > + EDP_PSR_CTL(intel_dp-
> > >psr.transcoder));
> > drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
> >
> > return;
> > }
> >
> > - if (dev_priv->psr.psr2_enabled) {
> > - tgl_disallow_dc3co_on_psr2_exit(dev_priv);
> > + if (intel_dp->psr.psr2_enabled) {
> > + tgl_disallow_dc3co_on_psr2_exit(intel_dp);
> > val = intel_de_read(dev_priv,
> > - EDP_PSR2_CTL(dev_priv-
> > >psr.transcoder));
> > + EDP_PSR2_CTL(intel_dp-
> > >psr.transcoder));
> > drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
> > val &= ~EDP_PSR2_ENABLE;
> > intel_de_write(dev_priv,
> > - EDP_PSR2_CTL(dev_priv->psr.transcoder),
> > val);
> > + EDP_PSR2_CTL(intel_dp->psr.transcoder),
> > val);
> > } else {
> > val = intel_de_read(dev_priv,
> > - EDP_PSR_CTL(dev_priv-
> > >psr.transcoder));
> > + EDP_PSR_CTL(intel_dp-
> > >psr.transcoder));
> > drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
> > val &= ~EDP_PSR_ENABLE;
> > intel_de_write(dev_priv,
> > - EDP_PSR_CTL(dev_priv->psr.transcoder),
> > val);
> > + EDP_PSR_CTL(intel_dp->psr.transcoder),
> > val);
> > }
> > - dev_priv->psr.active = false;
> > + intel_dp->psr.active = false;
> > }
> >
> > static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> > @@ -1077,21 +1073,21 @@ static void intel_psr_disable_locked(struct
> > intel_dp *intel_dp)
> > i915_reg_t psr_status;
> > u32 psr_status_mask;
> >
> > - lockdep_assert_held(&dev_priv->psr.lock);
> > + lockdep_assert_held(&intel_dp->psr.lock);
> >
> > - if (!dev_priv->psr.enabled)
> > + if (!intel_dp->psr.enabled)
> > return;
> >
> > drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
> > - dev_priv->psr.psr2_enabled ? "2" : "1");
> > + intel_dp->psr.psr2_enabled ? "2" : "1");
> >
> > - intel_psr_exit(dev_priv);
> > + intel_psr_exit(intel_dp);
> >
> > - if (dev_priv->psr.psr2_enabled) {
> > - psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
> > + if (intel_dp->psr.psr2_enabled) {
> > + psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
> > psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> > } else {
> > - psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder);
> > + psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder);
> > psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
> > }
> >
> > @@ -1101,7 +1097,7 @@ static void intel_psr_disable_locked(struct
> > intel_dp *intel_dp)
> > drm_err(&dev_priv->drm, "Timed out waiting PSR idle
> > state\n");
> >
> > /* WA 1408330847 */
> > - if (dev_priv->psr.psr2_sel_fetch_enabled &&
> > + if (intel_dp->psr.psr2_sel_fetch_enabled &&
> > (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> > IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> > intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > @@ -1110,10 +1106,10 @@ static void intel_psr_disable_locked(struct
> > intel_dp *intel_dp)
> > /* Disable PSR on Sink */
> > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
> >
> > - if (dev_priv->psr.psr2_enabled)
> > + if (intel_dp->psr.psr2_enabled)
> > drm_dp_dpcd_writeb(&intel_dp->aux,
> > DP_RECEIVER_ALPM_CONFIG, 0);
> >
> > - dev_priv->psr.enabled = false;
> > + intel_dp->psr.enabled = false;
> > }
> >
> > /**
> > @@ -1131,20 +1127,22 @@ void intel_psr_disable(struct intel_dp
> > *intel_dp,
> > if (!old_crtc_state->has_psr)
> > return;
> >
> > - if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv)))
> > + if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp)))
> > return;
> >
> > - mutex_lock(&dev_priv->psr.lock);
> > + mutex_lock(&intel_dp->psr.lock);
> >
> > intel_psr_disable_locked(intel_dp);
> >
> > - mutex_unlock(&dev_priv->psr.lock);
> > - cancel_work_sync(&dev_priv->psr.work);
> > - cancel_delayed_work_sync(&dev_priv->psr.dc3co_work);
> > + mutex_unlock(&intel_dp->psr.lock);
> > + cancel_work_sync(&intel_dp->psr.work);
> > + cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
> > }
> >
> > -static void psr_force_hw_tracking_exit(struct drm_i915_private
> > *dev_priv)
> > +static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
> > {
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > if (IS_TIGERLAKE(dev_priv))
> > /*
> > * Writes to CURSURFLIVE in TGL are causing IOMMU
> > errors and
> > @@ -1158,7 +1156,7 @@ static void psr_force_hw_tracking_exit(struct
> > drm_i915_private *dev_priv)
> > * So using this workaround until this issue is root
> > caused
> > * and a better fix is found.
> > */
> > - intel_psr_exit(dev_priv);
> > + intel_psr_exit(intel_dp);
> > else if (INTEL_GEN(dev_priv) >= 9)
> > /*
> > * Display WA #0884: skl+
> > @@ -1169,13 +1167,13 @@ static void
> > psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
> > * but it makes more sense write to the current active
> > * pipe.
> > */
> > - intel_de_write(dev_priv, CURSURFLIVE(dev_priv-
> > >psr.pipe), 0);
> > + intel_de_write(dev_priv, CURSURFLIVE(intel_dp-
> > >psr.pipe), 0);
> > else
> > /*
> > * A write to CURSURFLIVE do not cause HW tracking to
> > exit PSR
> > * on older gens so doing the manual exit instead.
> > */
> > - intel_psr_exit(dev_priv);
> > + intel_psr_exit(intel_dp);
> > }
> >
> > void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > @@ -1210,11 +1208,11 @@ void
> > intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane-
> > >id), val);
> > }
> >
> > -void intel_psr2_program_trans_man_trk_ctl(const struct
> > intel_crtc_state *crtc_state)
> > +void intel_psr2_program_trans_man_trk_ctl(struct intel_dp
> > *intel_dp,
> > + const struct intel_crtc_state
> > *crtc_state)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > - struct i915_psr *psr = &dev_priv->psr;
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + struct intel_psr *psr = &intel_dp->psr;
> >
> > if (!HAS_PSR2_SEL_FETCH(dev_priv) ||
> > !crtc_state->enable_psr2_sel_fetch)
> > @@ -1326,13 +1324,13 @@ void intel_psr_update(struct intel_dp
> > *intel_dp,
> > const struct drm_connector_state *conn_state)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > - struct i915_psr *psr = &dev_priv->psr;
> > + struct intel_psr *psr = &intel_dp->psr;
> > bool enable, psr2_enable;
> >
> > - if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp)
> > + if (!CAN_PSR(intel_dp))
> > return;
> >
> > - mutex_lock(&dev_priv->psr.lock);
> > + mutex_lock(&intel_dp->psr.lock);
> >
> > enable = crtc_state->has_psr;
> > psr2_enable = crtc_state->has_psr2;
> > @@ -1340,15 +1338,15 @@ void intel_psr_update(struct intel_dp
> > *intel_dp,
> > if (enable == psr->enabled && psr2_enable == psr->psr2_enabled)
> > {
> > /* Force a PSR exit when enabling CRC to avoid CRC
> > timeouts */
> > if (crtc_state->crc_enabled && psr->enabled)
> > - psr_force_hw_tracking_exit(dev_priv);
> > + psr_force_hw_tracking_exit(intel_dp);
> > else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) {
> > /*
> > * Activate PSR again after a force exit when
> > enabling
> > * CRC in older gens
> > */
> > - if (!dev_priv->psr.active &&
> > - !dev_priv->psr.busy_frontbuffer_bits)
> > - schedule_work(&dev_priv->psr.work);
> > + if (!intel_dp->psr.active &&
> > + !intel_dp->psr.busy_frontbuffer_bits)
> > + schedule_work(&intel_dp->psr.work);
> > }
> >
> > goto unlock;
> > @@ -1358,34 +1356,23 @@ void intel_psr_update(struct intel_dp
> > *intel_dp,
> > intel_psr_disable_locked(intel_dp);
> >
> > if (enable)
> > - intel_psr_enable_locked(dev_priv, crtc_state,
> > conn_state);
> > + intel_psr_enable_locked(intel_dp, crtc_state,
> > conn_state);
> >
> > unlock:
> > - mutex_unlock(&dev_priv->psr.lock);
> > + mutex_unlock(&intel_dp->psr.lock);
> > }
> >
> > /**
> > - * intel_psr_wait_for_idle - wait for PSR1 to idle
> > - * @new_crtc_state: new CRTC state
> > + * psr_wait_for_idle - wait for PSR1 to idle
> > + * @intel_dp: Intel DP
> > * @out_value: PSR status in case of failure
> > *
> > - * This function is expected to be called from pipe_update_start()
> > where it is
> > - * not expected to race with PSR enable or disable.
> > - *
> > * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
> > + *
> > */
> > -int intel_psr_wait_for_idle(const struct intel_crtc_state
> > *new_crtc_state,
> > - u32 *out_value)
> > +static int psr_wait_for_idle(struct intel_dp *intel_dp, u32
> > *out_value)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state-
> > >uapi.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > -
> > - if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
> > - return 0;
> > -
> > - /* FIXME: Update this for PSR2 if we need to wait for idle */
> > - if (READ_ONCE(dev_priv->psr.psr2_enabled))
> > - return 0;
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > /*
> > * From bspec: Panel Self Refresh (BDW+)
> > @@ -1393,32 +1380,67 @@ int intel_psr_wait_for_idle(const struct
> > intel_crtc_state *new_crtc_state,
> > * exit training time + 1.5 ms of aux channel handshake. 50 ms
> > is
> > * defensive enough to cover everything.
> > */
> > -
> > return __intel_wait_for_register(&dev_priv->uncore,
> > - EDP_PSR_STATUS(dev_priv-
> > >psr.transcoder),
> > + EDP_PSR_STATUS(intel_dp-
> > >psr.transcoder),
> > EDP_PSR_STATUS_STATE_MASK,
> > EDP_PSR_STATUS_STATE_IDLE, 2,
> > 50,
> > out_value);
> > }
> >
> > -static bool __psr_wait_for_idle_locked(struct drm_i915_private
> > *dev_priv)
> > +/**
> > + * intel_psr_wait_for_idle - wait for PSR1 to idle
> > + * @new_crtc_state: new CRTC state
> > + *
> > + * This function is expected to be called from pipe_update_start()
> > where it is
> > + * not expected to race with PSR enable or disable.
> > + */
> > +void intel_psr_wait_for_idle(const struct intel_crtc_state
> > *new_crtc_state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(new_crtc_state-
> > >uapi.crtc->dev);
> > + struct intel_encoder *encoder;
> > + u32 psr_status;
> > +
> > + if (!new_crtc_state->has_psr)
> > + return;
> > +
> > + for_each_intel_dp(&dev_priv->drm, encoder) {
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > + if (encoder->type != INTEL_OUTPUT_EDP)
> > + continue;
> > +
> > + /* when the PSR1 is enabled */
> > + if (intel_dp->psr.enabled && !intel_dp-
> > >psr.psr2_enabled) {
> > + if (psr_wait_for_idle(intel_dp, &psr_status))
> > + drm_err(&dev_priv->drm,
> > + "PSR idle timed out 0x%x,
> > atomic update may fail\n",
> > + psr_status);
> > +
> > + /* only one trancoder can enable PSR1 */
> > + break;
> > + }
> > + }
> > +}
> > +
> > +static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
> > {
> > i915_reg_t reg;
> > u32 mask;
> > int err;
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > - if (!dev_priv->psr.enabled)
> > + if (!intel_dp->psr.enabled)
> > return false;
> >
> > - if (dev_priv->psr.psr2_enabled) {
> > - reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
> > + if (intel_dp->psr.psr2_enabled) {
> > + reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
> > mask = EDP_PSR2_STATUS_STATE_MASK;
> > } else {
> > - reg = EDP_PSR_STATUS(dev_priv->psr.transcoder);
> > + reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);
> > mask = EDP_PSR_STATUS_STATE_MASK;
> > }
> >
> > - mutex_unlock(&dev_priv->psr.lock);
> > + mutex_unlock(&intel_dp->psr.lock);
> >
> > err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
> > if (err)
> > @@ -1426,8 +1448,8 @@ static bool __psr_wait_for_idle_locked(struct
> > drm_i915_private *dev_priv)
> > "Timed out waiting for PSR Idle for re-
> > enable\n");
> >
> > /* After the unlocked wait, verify that PSR is still wanted! */
> > - mutex_lock(&dev_priv->psr.lock);
> > - return err == 0 && dev_priv->psr.enabled;
> > + mutex_lock(&intel_dp->psr.lock);
> > + return err == 0 && intel_dp->psr.enabled;
> > }
> >
> > static int intel_psr_fastset_force(struct drm_i915_private
> > *dev_priv)
> > @@ -1493,11 +1515,12 @@ static int intel_psr_fastset_force(struct
> > drm_i915_private *dev_priv)
> > return err;
> > }
> >
> > -int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64
> > val)
> > +int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
> > {
> > const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
> > u32 old_mode;
> > int ret;
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
> > mode > I915_PSR_DEBUG_FORCE_PSR1) {
> > @@ -1505,21 +1528,21 @@ int intel_psr_debug_set(struct
> > drm_i915_private *dev_priv, u64 val)
> > return -EINVAL;
> > }
> >
> > - ret = mutex_lock_interruptible(&dev_priv->psr.lock);
> > + ret = mutex_lock_interruptible(&intel_dp->psr.lock);
> > if (ret)
> > return ret;
> >
> > - old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
> > - dev_priv->psr.debug = val;
> > + old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
> > + intel_dp->psr.debug = val;
> >
> > /*
> > * Do it right away if it's already enabled, otherwise it will
> > be done
> > * when enabling the source.
> > */
> > - if (dev_priv->psr.enabled)
> > - psr_irq_control(dev_priv);
> > + if (intel_dp->psr.enabled)
> > + psr_irq_control(intel_dp);
> >
> > - mutex_unlock(&dev_priv->psr.lock);
> > + mutex_unlock(&intel_dp->psr.lock);
> >
> > if (old_mode != mode)
> > ret = intel_psr_fastset_force(dev_priv);
> > @@ -1527,28 +1550,28 @@ int intel_psr_debug_set(struct
> > drm_i915_private *dev_priv, u64 val)
> > return ret;
> > }
> >
> > -static void intel_psr_handle_irq(struct drm_i915_private
> > *dev_priv)
> > +static void intel_psr_handle_irq(struct intel_dp *intel_dp)
> > {
> > - struct i915_psr *psr = &dev_priv->psr;
> > + struct intel_psr *psr = &intel_dp->psr;
> >
> > - intel_psr_disable_locked(psr->dp);
> > + intel_psr_disable_locked(intel_dp);
> > psr->sink_not_reliable = true;
> > /* let's make sure that sink is awaken */
> > - drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER,
> > DP_SET_POWER_D0);
> > + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> > DP_SET_POWER_D0);
> > }
> >
> > static void intel_psr_work(struct work_struct *work)
> > {
> > - struct drm_i915_private *dev_priv =
> > - container_of(work, typeof(*dev_priv), psr.work);
> > + struct intel_dp *intel_dp =
> > + container_of(work, typeof(*intel_dp), psr.work);
> >
> > - mutex_lock(&dev_priv->psr.lock);
> > + mutex_lock(&intel_dp->psr.lock);
> >
> > - if (!dev_priv->psr.enabled)
> > + if (!intel_dp->psr.enabled)
> > goto unlock;
> >
> > - if (READ_ONCE(dev_priv->psr.irq_aux_error))
> > - intel_psr_handle_irq(dev_priv);
> > + if (READ_ONCE(intel_dp->psr.irq_aux_error))
> > + intel_psr_handle_irq(intel_dp);
> >
> > /*
> > * We have to make sure PSR is ready for re-enable
> > @@ -1556,7 +1579,7 @@ static void intel_psr_work(struct work_struct
> > *work)
> > * PSR might take some time to get fully disabled
> > * and be ready for re-enable.
> > */
> > - if (!__psr_wait_for_idle_locked(dev_priv))
> > + if (!__psr_wait_for_idle_locked(intel_dp))
> > goto unlock;
> >
> > /*
> > @@ -1564,12 +1587,12 @@ static void intel_psr_work(struct
> > work_struct *work)
> > * recheck. Since psr_flush first clears this and then
> > reschedules we
> > * won't ever miss a flush when bailing out here.
> > */
> > - if (dev_priv->psr.busy_frontbuffer_bits || dev_priv-
> > >psr.active)
> > + if (intel_dp->psr.busy_frontbuffer_bits || intel_dp-
> > >psr.active)
> > goto unlock;
> >
> > - intel_psr_activate(dev_priv->psr.dp);
> > + intel_psr_activate(intel_dp);
> > unlock:
> > - mutex_unlock(&dev_priv->psr.lock);
> > + mutex_unlock(&intel_dp->psr.lock);
> > }
> >
> > /**
> > @@ -1588,27 +1611,35 @@ static void intel_psr_work(struct
> > work_struct *work)
> > void intel_psr_invalidate(struct drm_i915_private *dev_priv,
> > unsigned frontbuffer_bits, enum fb_op_origin
> > origin)
> > {
> > - if (!CAN_PSR(dev_priv))
> > - return;
> > + struct intel_encoder *encoder;
> > + struct intel_dp *intel_dp;
> >
> > - if (origin == ORIGIN_FLIP)
> > - return;
> > + for_each_intel_dp(&dev_priv->drm, encoder) {
> >
> > - mutex_lock(&dev_priv->psr.lock);
> > - if (!dev_priv->psr.enabled) {
> > - mutex_unlock(&dev_priv->psr.lock);
> > - return;
> > - }
> > + intel_dp = enc_to_intel_dp(encoder);
> > + if (encoder->type != INTEL_OUTPUT_EDP)
> > + continue;
> > + if (!CAN_PSR(intel_dp))
> > + continue;
> > +
> > + if (origin == ORIGIN_FLIP)
> > + continue;
> >
> > - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv-
> > >psr.pipe);
> > - dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
> > + mutex_lock(&intel_dp->psr.lock);
> > + if (!intel_dp->psr.enabled) {
> > + mutex_unlock(&intel_dp->psr.lock);
> > + continue;
> > + }
> >
> > - if (frontbuffer_bits)
> > - intel_psr_exit(dev_priv);
> > + frontbuffer_bits &=
> > INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
> > + intel_dp->psr.busy_frontbuffer_bits |=
> > frontbuffer_bits;
> >
> > - mutex_unlock(&dev_priv->psr.lock);
> > -}
> > + if (frontbuffer_bits)
> > + intel_psr_exit(intel_dp);
> >
> > + mutex_unlock(&intel_dp->psr.lock);
> > + }
> > +}
> > /*
> > * When we will be completely rely on PSR2 S/W tracking in future,
> > * intel_psr_flush() will invalidate and flush the PSR for
> > ORIGIN_FLIP
> > @@ -1616,15 +1647,15 @@ void intel_psr_invalidate(struct
> > drm_i915_private *dev_priv,
> > * accordingly in future.
> > */
> > static void
> > -tgl_dc3co_flush(struct drm_i915_private *dev_priv,
> > - unsigned int frontbuffer_bits, enum fb_op_origin
> > origin)
> > +tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int
> > frontbuffer_bits,
> > + enum fb_op_origin origin)
> > {
> > - mutex_lock(&dev_priv->psr.lock);
> > + mutex_lock(&intel_dp->psr.lock);
> >
> > - if (!dev_priv->psr.dc3co_enabled)
> > + if (!intel_dp->psr.dc3co_enabled)
> > goto unlock;
> >
> > - if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active)
> > + if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
> > goto unlock;
> >
> > /*
> > @@ -1632,15 +1663,15 @@ tgl_dc3co_flush(struct drm_i915_private
> > *dev_priv,
> > * when delayed work schedules that means display has been
> > idle.
> > */
> > if (!(frontbuffer_bits &
> > - INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe)))
> > + INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
> > goto unlock;
> >
> > - tgl_psr2_enable_dc3co(dev_priv);
> > - mod_delayed_work(system_wq, &dev_priv->psr.dc3co_work,
> > - dev_priv->psr.dc3co_exit_delay);
> > + tgl_psr2_enable_dc3co(intel_dp);
> > + mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work,
> > + intel_dp->psr.dc3co_exit_delay);
> >
> > unlock:
> > - mutex_unlock(&dev_priv->psr.lock);
> > + mutex_unlock(&intel_dp->psr.lock);
> > }
> >
> > /**
> > @@ -1659,45 +1690,54 @@ tgl_dc3co_flush(struct drm_i915_private
> > *dev_priv,
> > void intel_psr_flush(struct drm_i915_private *dev_priv,
> > unsigned frontbuffer_bits, enum fb_op_origin
> > origin)
> > {
> > - if (!CAN_PSR(dev_priv))
> > - return;
> > -
> > - if (origin == ORIGIN_FLIP) {
> > - tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin);
> > - return;
> > - }
> > -
> > - mutex_lock(&dev_priv->psr.lock);
> > - if (!dev_priv->psr.enabled) {
> > - mutex_unlock(&dev_priv->psr.lock);
> > - return;
> > + struct intel_encoder *encoder;
> > + struct intel_dp *intel_dp;
> > +
> > + for_each_intel_dp(&dev_priv->drm, encoder) {
> > + intel_dp = enc_to_intel_dp(encoder);
> > +
> > + if (encoder->type == INTEL_OUTPUT_EDP &&
> > CAN_PSR(intel_dp)) {
> > + if (origin == ORIGIN_FLIP) {
> > + tgl_dc3co_flush(intel_dp,
> > frontbuffer_bits, origin);
> > + continue;
> > + }
> > +
> > + mutex_lock(&intel_dp->psr.lock);
> > + if (!intel_dp->psr.enabled) {
> > + mutex_unlock(&intel_dp->psr.lock);
> > + continue;
> > + }
> > +
> > + frontbuffer_bits &=
> > INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
> > + intel_dp->psr.busy_frontbuffer_bits &=
> > ~frontbuffer_bits;
> > +
> > + /* By definition flush = invalidate + flush */
> > + if (frontbuffer_bits)
> > + psr_force_hw_tracking_exit(intel_dp);
> > +
> > + if (!intel_dp->psr.active && !intel_dp-
> > >psr.busy_frontbuffer_bits)
> > + schedule_work(&intel_dp->psr.work);
> > + mutex_unlock(&intel_dp->psr.lock);
> > + }
> > }
> > -
> > - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv-
> > >psr.pipe);
> > - dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
> > -
> > - /* By definition flush = invalidate + flush */
> > - if (frontbuffer_bits)
> > - psr_force_hw_tracking_exit(dev_priv);
> > -
> > - if (!dev_priv->psr.active && !dev_priv-
> > >psr.busy_frontbuffer_bits)
> > - schedule_work(&dev_priv->psr.work);
> > - mutex_unlock(&dev_priv->psr.lock);
> > }
> >
> > /**
> > * intel_psr_init - Init basic PSR work and mutex.
> > - * @dev_priv: i915 device private
> > + * @intel_dp: Intel DP
> > *
> > - * This function is called only once at driver load to initialize
> > basic
> > - * PSR stuff.
> > + * This function is called after the initializing connector.
> > + * (the initializing of connector treats the handling of connector
> > capabilities)
> > + * And it initializes basic PSR stuff for each DP Encoder.
> > */
> > -void intel_psr_init(struct drm_i915_private *dev_priv)
> > +void intel_psr_init(struct intel_dp *intel_dp)
> > {
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > if (!HAS_PSR(dev_priv))
> > return;
> >
> > - if (!dev_priv->psr.sink_support)
> > + if (!intel_dp->psr.sink_support)
> > return;
> >
> > if (IS_HASWELL(dev_priv))
> > @@ -1715,14 +1755,14 @@ void intel_psr_init(struct drm_i915_private
> > *dev_priv)
> > /* Set link_standby x link_off defaults */
> > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > /* HSW and BDW require workarounds that we don't
> > implement. */
> > - dev_priv->psr.link_standby = false;
> > + intel_dp->psr.link_standby = false;
> > else if (INTEL_GEN(dev_priv) < 12)
> > /* For new platforms up to TGL let's respect VBT back
> > again */
> > - dev_priv->psr.link_standby = dev_priv-
> > >vbt.psr.full_link;
> > + intel_dp->psr.link_standby = dev_priv-
> > >vbt.psr.full_link;
> >
> > - INIT_WORK(&dev_priv->psr.work, intel_psr_work);
> > - INIT_DELAYED_WORK(&dev_priv->psr.dc3co_work,
> > tgl_dc3co_disable_work);
> > - mutex_init(&dev_priv->psr.lock);
> > + INIT_WORK(&intel_dp->psr.work, intel_psr_work);
> > + INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work,
> > tgl_dc3co_disable_work);
> > + mutex_init(&intel_dp->psr.lock);
> > }
> >
> > static int psr_get_status_and_error_status(struct intel_dp
> > *intel_dp,
> > @@ -1748,7 +1788,7 @@ static void psr_alpm_check(struct intel_dp
> > *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > struct drm_dp_aux *aux = &intel_dp->aux;
> > - struct i915_psr *psr = &dev_priv->psr;
> > + struct intel_psr *psr = &intel_dp->psr;
> > u8 val;
> > int r;
> >
> > @@ -1775,7 +1815,7 @@ static void psr_alpm_check(struct intel_dp
> > *intel_dp)
> > static void psr_capability_changed_check(struct intel_dp
> > *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > - struct i915_psr *psr = &dev_priv->psr;
> > + struct intel_psr *psr = &intel_dp->psr;
> > u8 val;
> > int r;
> >
> > @@ -1799,18 +1839,18 @@ static void
> > psr_capability_changed_check(struct intel_dp *intel_dp)
> > void intel_psr_short_pulse(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > - struct i915_psr *psr = &dev_priv->psr;
> > + struct intel_psr *psr = &intel_dp->psr;
> > u8 status, error_status;
> > const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
> > DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
> > DP_PSR_LINK_CRC_ERROR;
> >
> > - if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
> > + if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp))
> > return;
> >
> > mutex_lock(&psr->lock);
> >
> > - if (!psr->enabled || psr->dp != intel_dp)
> > + if (!psr->enabled)
> > goto exit;
> >
> > if (psr_get_status_and_error_status(intel_dp, &status,
> > &error_status)) {
> > @@ -1853,15 +1893,14 @@ void intel_psr_short_pulse(struct intel_dp
> > *intel_dp)
> >
> > bool intel_psr_enabled(struct intel_dp *intel_dp)
> > {
> > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > bool ret;
> >
> > - if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
> > + if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp))
> > return false;
> >
> > - mutex_lock(&dev_priv->psr.lock);
> > - ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled);
> > - mutex_unlock(&dev_priv->psr.lock);
> > + mutex_lock(&intel_dp->psr.lock);
> > + ret = intel_dp->psr.enabled;
> > + mutex_unlock(&intel_dp->psr.lock);
> >
> > return ret;
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index 0a517978e8af..03eb19547d09 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -18,7 +18,7 @@ struct intel_atomic_state;
> > struct intel_plane_state;
> > struct intel_plane;
> >
> > -#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv-
> > >psr.sink_support)
> > +#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) &&
> > intel_dp->psr.sink_support)
> > void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> > void intel_psr_enable(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state,
> > @@ -28,24 +28,24 @@ void intel_psr_disable(struct intel_dp
> > *intel_dp,
> > void intel_psr_update(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state,
> > const struct drm_connector_state *conn_state);
> > -int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64
> > value);
> > +int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);
> > void intel_psr_invalidate(struct drm_i915_private *dev_priv,
> > unsigned frontbuffer_bits,
> > enum fb_op_origin origin);
> > void intel_psr_flush(struct drm_i915_private *dev_priv,
> > unsigned frontbuffer_bits,
> > enum fb_op_origin origin);
> > -void intel_psr_init(struct drm_i915_private *dev_priv);
> > +void intel_psr_init(struct intel_dp *intel_dp);
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state);
> > -void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32
> > psr_iir);
> > +void intel_psr_irq_handler(struct intel_dp *intel_dp, u32
> > psr_iir);
> > void intel_psr_short_pulse(struct intel_dp *intel_dp);
> > -int intel_psr_wait_for_idle(const struct intel_crtc_state
> > *new_crtc_state,
> > - u32 *out_value);
> > +void intel_psr_wait_for_idle(const struct intel_crtc_state
> > *new_crtc_state);
> > bool intel_psr_enabled(struct intel_dp *intel_dp);
> > int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
> > -void intel_psr2_program_trans_man_trk_ctl(const struct
> > intel_crtc_state *crtc_state);
> > +void intel_psr2_program_trans_man_trk_ctl(struct intel_dp
> > *intel_dp,
> > + const struct intel_crtc_state
> > *crtc_state);
> > void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > const struct intel_crtc_state
> > *crtc_state,
> > const struct intel_plane_state
> > *plane_state,
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index b6deeb338477..ccd86f168357 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -92,7 +92,6 @@ void intel_pipe_update_start(const struct
> > intel_crtc_state *new_crtc_state)
> > bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) ||
> > IS_CHERRYVIEW(dev_priv)) &&
> > intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
> > DEFINE_WAIT(wait);
> > - u32 psr_status;
> >
> > if (new_crtc_state->uapi.async_flip)
> > return;
> > @@ -117,10 +116,7 @@ void intel_pipe_update_start(const struct
> > intel_crtc_state *new_crtc_state)
> > * VBL interrupts will start the PSR exit and prevent a PSR
> > * re-entry as well.
> > */
> > - if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
> > - drm_err(&dev_priv->drm,
> > - "PSR idle timed out 0x%x, atomic update may
> > fail\n",
> > - psr_status);
> > + intel_psr_wait_for_idle(new_crtc_state);
> >
> > local_irq_disable();
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 15be8debae54..5a40295260c2 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -475,42 +475,6 @@ struct i915_drrs {
> > enum drrs_support_type type;
> > };
> >
> > -struct i915_psr {
> > - struct mutex lock;
> > -
> > -#define I915_PSR_DEBUG_MODE_MASK 0x0f
> > -#define I915_PSR_DEBUG_DEFAULT 0x00
> > -#define I915_PSR_DEBUG_DISABLE 0x01
> > -#define I915_PSR_DEBUG_ENABLE 0x02
> > -#define I915_PSR_DEBUG_FORCE_PSR1 0x03
> > -#define I915_PSR_DEBUG_IRQ 0x10
> > -
> > - u32 debug;
> > - bool sink_support;
> > - bool enabled;
> > - struct intel_dp *dp;
> > - enum pipe pipe;
> > - enum transcoder transcoder;
> > - bool active;
> > - struct work_struct work;
> > - unsigned busy_frontbuffer_bits;
> > - bool sink_psr2_support;
> > - bool link_standby;
> > - bool colorimetry_support;
> > - bool psr2_enabled;
> > - bool psr2_sel_fetch_enabled;
> > - u8 sink_sync_latency;
> > - ktime_t last_entry_attempt;
> > - ktime_t last_exit;
> > - bool sink_not_reliable;
> > - bool irq_aux_error;
> > - u16 su_x_granularity;
> > - bool dc3co_enabled;
> > - u32 dc3co_exit_delay;
> > - struct delayed_work dc3co_work;
> > - struct drm_dp_vsc_sdp vsc;
> > -};
> > -
> > #define QUIRK_LVDS_SSC_DISABLE (1<<1)
> > #define QUIRK_INVERT_BRIGHTNESS (1<<2)
> > #define QUIRK_BACKLIGHT_PRESENT (1<<3)
> > @@ -1041,8 +1005,6 @@ struct drm_i915_private {
> >
> > struct i915_power_domains power_domains;
> >
> > - struct i915_psr psr;
> > -
> > struct i915_gpu_error gpu_error;
> >
> > struct drm_i915_gem_object *vlv_pctx;
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index e0eb32bd9607..6d43298c46dd 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2057,10 +2057,20 @@ static void ivb_display_irq_handler(struct
> > drm_i915_private *dev_priv,
> > ivb_err_int_handler(dev_priv);
> >
> > if (de_iir & DE_EDP_PSR_INT_HSW) {
> > - u32 psr_iir = I915_READ(EDP_PSR_IIR);
> > + struct intel_encoder *encoder;
> >
> > - intel_psr_irq_handler(dev_priv, psr_iir);
> > - I915_WRITE(EDP_PSR_IIR, psr_iir);
> > + for_each_intel_dp(&dev_priv->drm, encoder) {
> > + struct intel_dp *intel_dp =
> > enc_to_intel_dp(encoder);
> > +
> > + if (encoder->type == INTEL_OUTPUT_EDP &&
> > + CAN_PSR(intel_dp)) {
> > + u32 psr_iir = I915_READ(EDP_PSR_IIR);
> > +
> > + intel_psr_irq_handler(intel_dp,
> > psr_iir);
> > + I915_WRITE(EDP_PSR_IIR, psr_iir);
> > + break;
> > + }
> > + }
> > }
> >
> > if (de_iir & DE_AUX_CHANNEL_A_IVB)
> > @@ -2268,21 +2278,34 @@ gen8_de_misc_irq_handler(struct
> > drm_i915_private *dev_priv, u32 iir)
> > }
> >
> > if (iir & GEN8_DE_EDP_PSR) {
> > + struct intel_encoder *encoder;
> > u32 psr_iir;
> > i915_reg_t iir_reg;
> >
> > - if (INTEL_GEN(dev_priv) >= 12)
> > - iir_reg = TRANS_PSR_IIR(dev_priv-
> > >psr.transcoder);
> > - else
> > - iir_reg = EDP_PSR_IIR;
> > + for_each_intel_dp(&dev_priv->drm, encoder) {
> > + struct intel_dp *intel_dp =
> > enc_to_intel_dp(encoder);
> >
> > - psr_iir = I915_READ(iir_reg);
> > - I915_WRITE(iir_reg, psr_iir);
> > + if (INTEL_GEN(dev_priv) >= 12 &&
> > CAN_PSR(intel_dp)) {
> > + iir_reg = TRANS_PSR_IIR(intel_dp-
> > >psr.transcoder);
> > + } else if (encoder->type == INTEL_OUTPUT_EDP &&
> > + CAN_PSR(intel_dp)) {
> > + iir_reg = EDP_PSR_IIR;
> > + } else {
> > + continue;
> > + }
> > +
> > + psr_iir = I915_READ(iir_reg);
> > + I915_WRITE(iir_reg, psr_iir);
> > +
> > + if (psr_iir)
> > + found = true;
> >
> > - if (psr_iir)
> > - found = true;
> > + intel_psr_irq_handler(intel_dp, psr_iir);
> >
> > - intel_psr_irq_handler(dev_priv, psr_iir);
> > + /* prior GEN12 only have one EDP PSR */
> > + if (INTEL_GEN(dev_priv) < 12)
> > + break;
> > + }
> > }
> >
> > if (!found)
> > --
> > 2.25.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
2020-11-18 11:11 ` Jani Nikula
@ 2020-12-11 10:45 ` Mun, Gwan-gyeong
0 siblings, 0 replies; 17+ messages in thread
From: Mun, Gwan-gyeong @ 2020-12-11 10:45 UTC (permalink / raw)
To: intel-gfx, jani.nikula
On Wed, 2020-11-18 at 13:11 +0200, Jani Nikula wrote:
> On Fri, 06 Nov 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> wrote:
> > In order to support the PSR state of each transcoder, it adds
> > i915_psr_status to sub-directory of each transcoder.
> >
> > v2: Change using of Symbolic permissions 'S_IRUGO' to using of
> > octal
> > permissions '0444'
> >
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > .../drm/i915/display/intel_display_debugfs.c | 23
> > +++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 8402e6ac9f76..37805615a221 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -2093,6 +2093,23 @@ static int
> > i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
> > }
> > DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
> >
> > +static int i915_psr_status_show(struct seq_file *m, void *data)
> > +{
> > + struct drm_connector *connector = m->private;
> > + struct intel_dp *intel_dp =
> > + intel_attached_dp(to_intel_connector(connector));
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + if (connector->status != connector_status_connected)
> > + return -ENODEV;
> > +
> > + if (!HAS_PSR(dev_priv))
> > + return -ENODEV;
> > +
> > + return intel_psr_status(m, intel_dp);
> > +}
> > +DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
> > +
> > #define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n")
> > : \
> > seq_puts(m, "LPSP: incapable\n"))
> >
> > @@ -2268,6 +2285,12 @@ int intel_connector_debugfs_add(struct
> > drm_connector *connector)
> > connector,
> > &i915_psr_sink_status_fops);
> > }
> >
> > + if (INTEL_GEN(dev_priv) >= 12 &&
>
> I'd add this for all generations to unify the debugfs, and eventually
> phase out the non connector specific debugfs file.
>
> And I'd add HAS_PSR() check here to not create the file if it's not
> possible instead of having the check in i915_psr_status_show().
>
Hi Jani,
Thank you for checking the patch.
I'll update the code as per your recommendations.
> BR,
> Jani.
>
> > + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> > + debugfs_create_file("i915_psr_status", 0444, root,
> > + connector, &i915_psr_status_fops);
> > + }
> > +
> > if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort
> > ||
> > connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> > connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
2020-12-04 16:06 ` Anshuman Gupta
@ 2020-12-11 10:50 ` Mun, Gwan-gyeong
0 siblings, 0 replies; 17+ messages in thread
From: Mun, Gwan-gyeong @ 2020-12-11 10:50 UTC (permalink / raw)
To: Gupta, Anshuman, jani.nikula; +Cc: intel-gfx
On Fri, 2020-12-04 at 21:36 +0530, Anshuman Gupta wrote:
> On 2020-11-18 at 16:42:29 +0530, Jani Nikula wrote:
> > On Fri, 06 Nov 2020, Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > wrote:
> > > In order to support the PSR state of each transcoder, it adds
> > > i915_psr_status to sub-directory of each transcoder.
> > >
> > > v2: Change using of Symbolic permissions 'S_IRUGO' to using of
> > > octal
> > > permissions '0444'
> > >
> > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_debugfs.c | 23
> > > +++++++++++++++++++
> > > 1 file changed, 23 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > index 8402e6ac9f76..37805615a221 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > @@ -2093,6 +2093,23 @@ static int
> > > i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
> > > }
> > > DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
> > >
> > > +static int i915_psr_status_show(struct seq_file *m, void *data)
> > > +{
> > > + struct drm_connector *connector = m->private;
> > > + struct intel_dp *intel_dp =
> > > + intel_attached_dp(to_intel_connector(connector));
> > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > +
> > > + if (connector->status != connector_status_connected)
> >
> > How's this possible for eDP, btw?
> >
When I wrote the code first it was considered PanelReplay of DP spec.
for now it is not needed for edp.
> > BR,
> > Jani.
> >
> > > + return -ENODEV;
> > > +
> > > + if (!HAS_PSR(dev_priv))
> > > + return -ENODEV;
> > > +
> > > + return intel_psr_status(m, intel_dp);
> > > +}
> > > +DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
> > > +
> > > #define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP:
> > > capable\n") : \
> > > seq_puts(m, "LPSP: incapable\n"))
> > >
> > > @@ -2268,6 +2285,12 @@ int intel_connector_debugfs_add(struct
> > > drm_connector *connector)
> > > connector,
> > > &i915_psr_sink_status_fops);
> > > }
> > >
> > > + if (INTEL_GEN(dev_priv) >= 12 &&
> > > + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> Hi GG
> IMHO this should connector->connector_type == DRM_MODE_CONNECTOR_eDP
> || connector->connector_type == DRM_MODE_SUBCONNECTOR_DisplayPort
> to support DP Panel Reply, i read somewere DP panel reply is PSR with
> Link Full ON ?
> I believe this would be the reason to keep file name as
> "i915_psr_status" instead of i915_edp_psr_status?
Hi Anshuman,
Yes, the file name (i915_psr_status) was considered for DP PanelReplay
too.
But for now, i915 is not supported PanelReplay yet, it would be better
to limit it to edp.
When the PanelReplay is ready I'll update here too.
> Thanks,
> Anshuman.
> > > + debugfs_create_file("i915_psr_status", 0444, root,
> > > + connector, &i915_psr_status_fops);
> > > + }
> > > +
> > > if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort
> > > ||
> > > connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> > > connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2020-12-11 10:50 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-06 10:14 [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Gwan-gyeong Mun
2020-11-06 10:14 ` [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs Gwan-gyeong Mun
2020-11-18 11:11 ` Jani Nikula
2020-12-11 10:45 ` Mun, Gwan-gyeong
2020-11-18 11:12 ` Jani Nikula
2020-12-04 16:06 ` Anshuman Gupta
2020-12-11 10:50 ` Mun, Gwan-gyeong
2020-11-06 12:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders Patchwork
2020-11-06 12:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-06 12:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-06 15:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-11-10 19:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/2] drm/i915/display: Support PSR Multiple Transcoders (rev2) Patchwork
2020-11-10 19:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-10 20:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-10 23:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-12-04 16:38 ` [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders Anshuman Gupta
2020-12-11 10:22 ` Mun, Gwan-gyeong
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